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MC3S12RG128
Data Sheet
HCS12 Microcontrollers
MC3S12RG128V1 Rev. 1.05 11/2006
freescale.com
MC3S12RG128 Data Sheet
covers MC3S12RB128, MC3S12R64
MC3S12RG128V1 Rev. 1.05 11/2006
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ The following revision history table summarizes changes contained in this document.
Revision History
Date September, 2005 September, 2005 October, 2005 November, 2005 February, 2006 November, 2006 Revision Level 01.00 01.01 new book added MC3S12R64 corrected MC3S12RG128 block diagram updated SCIV2 chapter corrected MC3S12R64 memory map diagram, added warning about 8K RAM mapping updated MSCANV2 chapter added MC3S12RB128 updated ROM64KX16, SCI chapters updated electrical specification updated ATD10B8C, IIC chapters corrected duplicated offsets in device register map removed references to the INITEE register and marked it as "reserved" (there is no EEPROM on this device) Description
01.02
01.03 01.04
01.05
FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash(R) technology licensed from SST. (c) Freescale Semiconductor, Inc., 2005, 2006. All rights reserved. MC3S12RG128 Data Sheet, Rev. 1.05 4 Freescale Semiconductor
Contents
Section Number Title Chapter 1 Device Overview (MC3S12RG128V1)
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.1.4 Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.1.5 Logical Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.1.6 Device Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.1.7 Part ID Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 1.2.1 Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 1.2.2 Signal Properties Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 1.2.3 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 1.2.4 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 System Clock Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Chip Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 1.4.1 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 1.5.1 User Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 1.5.2 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Resets and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 1.6.1 Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 1.6.2 Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Page
1.2
1.3 1.4 1.5
1.6
Chapter 2 Port Integration Module (PIM3RG128V1) Block Description
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 2.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 2.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 2.2.1 Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 2.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 2.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 2.4.1 I/O Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 2.4.2 Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
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2.2 2.3
2.4
Section Number
2.4.3 2.4.4 2.4.5 2.4.6 2.4.7 2.4.8 2.4.9 2.4.10 2.4.11 2.4.12 2.4.13 2.4.14 2.4.15
Title
Page
Data Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Reduced Drive Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Pull Device Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Polarity Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Port T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Port S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Port M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Port P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Port H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Port J . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Port A, B, E, K, and BKGD Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 External Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Chapter 3 Module Mapping Control (MMCV5) Block Description
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 3.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 3.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 3.3.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 3.4.1 Bus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 3.4.2 Address Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 3.4.3 Memory Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
3.2 3.3 3.4
Chapter 4 Multiplexed External Bus Interface (MEBIV3) Block Description
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 4.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 4.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 4.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 4.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 4.4.1 Detecting Access Type from External Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 4.4.2 Stretched Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 4.4.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
4.2 4.3
4.4
MC3S12RG128 Data Sheet, Rev. 1.05 6 Freescale Semiconductor
Section Number
4.4.4 4.4.5
Title
Page
Internal Visibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Chapter 5 Interrupt (INTV1) Block Description
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 5.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 5.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 5.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 5.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 5.4.1 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 5.6.1 Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 5.6.2 Highest Priority I-Bit Maskable Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 5.6.3 Interrupt Priority Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Exception Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
5.2 5.3
5.4 5.5 5.6
5.7
Chapter 6 Background Debug Module (BDMV4) Block Description
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 6.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 6.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 6.2.1 BKGD -- Background Interface Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 6.2.2 TAGHI -- High Byte Instruction Tagging Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 6.2.3 TAGLO -- Low Byte Instruction Tagging Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 6.3.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 6.4.1 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 6.4.2 Enabling and Activating BDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 6.4.3 BDM Hardware Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 6.4.4 Standard BDM Firmware Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 6.4.5 BDM Command Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 6.4.6 BDM Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 6.4.7 Serial Interface Hardware Handshake Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 6.4.8 Hardware Handshake Abort Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 6.4.9 SYNC -- Request Timed Reference Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
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6.2
6.3 6.4
Section Number
6.4.10 6.4.11 6.4.12 6.4.13 6.4.14
Title
Page
Instruction Tracing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Instruction Tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 Serial Communication Time-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 Operation in Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Operation in Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Chapter 7 Breakpoint Module (BKPV1) Block Description
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 7.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 7.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 7.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 7.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 7.4.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 7.4.2 Breakpoint Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
7.2 7.3 7.4
Chapter 8 Analog-to-Digital Converter (ATD10B8CV3)
8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 8.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 8.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 8.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 8.2.1 ANx (x = 7, 6, 5, 4, 3, 2, 1, 0) -- Analog Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 8.2.2 ETRIG3, ETRIG2, ETRIG1, and ETRIG0 -- External Trigger Pins . . . . . . . . . . . . . . 214 8.2.3 VRH and VRL -- High and Low Reference Voltage Pins . . . . . . . . . . . . . . . . . . . . . . . . 214 8.2.4 VDDA and VSSA -- Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 8.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 8.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 8.4.1 Analog Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 8.4.2 Digital Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 8.5.1 Setting up and starting an A/D conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 8.5.2 Aborting an A/D conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
8.2
8.3
8.4
8.5
8.6 8.7
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Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 9.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 9.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 9.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 9.2.1 VDDPLL, VSSPLL -- PLL Operating Voltage, PLL Ground . . . . . . . . . . . . . . . . . . . . . . 243 9.2.2 XFC -- PLL Loop Filter Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 9.2.3 RESET -- Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 9.3.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 9.4.1 Phase Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 9.4.2 System Clocks Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 9.4.3 Clock Monitor (CM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 9.4.4 Clock Quality Checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 9.4.5 Computer Operating Properly Watchdog (COP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 9.4.6 Real-Time Interrupt (RTI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 9.4.7 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 9.4.8 Low-Power Operation in Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 9.4.9 Low-Power Operation in Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 9.4.10 Low-Power Operation in Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 9.5.1 Clock Monitor Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 9.5.2 Computer Operating Properly Watchdog (COP) Reset . . . . . . . . . . . . . . . . . . . . . . . . . 274 9.5.3 Power-On Reset, Low Voltage Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 9.6.1 Real-Time Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 9.6.2 PLL Lock Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 9.6.3 Self-Clock Mode Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
9.2
9.3 9.4
9.5
9.6
Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 10.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 10.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 10.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 10.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 10.2.1 IOC7 -- Input Capture and Output Compare Channel 7 . . . . . . . . . . . . . . . . . . . . . . . . 279 10.2.2 IOC6 -- Input Capture and Output Compare Channel 6 . . . . . . . . . . . . . . . . . . . . . . . . 279 10.2.3 IOC5 -- Input Capture and Output Compare Channel 5 . . . . . . . . . . . . . . . . . . . . . . . . 279
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10.3
10.4 10.5 10.6
10.2.4 IOC4 -- Input Capture and Output Compare Channel 4 . . . . . . . . . . . . . . . . . . . . . . . . 279 10.2.5 IOC3 -- Input Capture and Output Compare Channel 3 . . . . . . . . . . . . . . . . . . . . . . . . 279 10.2.6 IOC2 -- Input Capture and Output Compare Channel 2 . . . . . . . . . . . . . . . . . . . . . . . . 279 10.2.7 IOC1 -- Input Capture and Output Compare Channel 1 . . . . . . . . . . . . . . . . . . . . . . . . 279 10.2.8 IOC0 -- Input Capture and Output Compare Channel 0 . . . . . . . . . . . . . . . . . . . . . . . . 279 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 10.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 10.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 10.4.1 Enhanced Capture Timer Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 10.6.1 Channel [7:0] Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 10.6.2 Modulus Counter Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 10.6.3 Pulse Accumulator B Overflow Interrupt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 10.6.4 Pulse Accumulator A Input Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 10.6.5 Pulse Accumulator A Overflow Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 10.6.6 Timer Overflow Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
Chapter 11 Inter-Integrated Circuit (IICV2) Block Description
11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 11.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 11.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 11.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 11.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 11.2.1 IIC_SCL -- Serial Clock Line Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 11.2.2 IIC_SDA -- Serial Data Line Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 11.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 11.3.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 11.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 11.4.1 I-Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 11.4.2 Operation in Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 11.4.3 Operation in Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 11.4.4 Operation in Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 11.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 11.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 11.7 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 11.7.1 IIC Programming Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
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Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 12.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 12.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 12.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 12.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 12.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 12.2.1 RXCAN -- CAN Receiver Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 12.2.2 TXCAN -- CAN Transmitter Output Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 12.2.3 CAN System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 12.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 12.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 12.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 12.3.3 Programmer's Model of Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370 12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 12.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 12.4.2 Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380 12.4.3 Identifier Acceptance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 12.4.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 12.4.5 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390 12.4.6 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 12.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 12.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 12.5.1 MSCAN initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
Chapter 13 Oscillator (OSCV2) Block Description
13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399 13.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399 13.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399 13.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 13.2.1 VDDPLL and VSSPLL -- PLL Operating Voltage, PLL Ground . . . . . . . . . . . . . . . . . . . 400 13.2.2 EXTAL and XTAL -- Clock/Crystal Source Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 13.2.3 XCLKS -- Colpitts/Pierce Oscillator Selection Signal . . . . . . . . . . . . . . . . . . . . . . . . . 401 13.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402 13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402 13.4.1 Amplitude Limitation Control (ALC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402 13.4.2 Clock Monitor (CM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402 13.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
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Title Chapter 14 Pulse-Width Modulator (PWM8B8CV1)
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14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403 14.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403 14.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403 14.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404 14.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404 14.2.1 PWM7 -- PWM Channel 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404 14.2.2 PWM6 -- PWM Channel 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404 14.2.3 PWM5 -- PWM Channel 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405 14.2.4 PWM4 -- PWM Channel 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405 14.2.5 PWM3 -- PWM Channel 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405 14.2.6 PWM3 -- PWM Channel 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405 14.2.7 PWM3 -- PWM Channel 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405 14.2.8 PWM3 -- PWM Channel 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405 14.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405 14.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405 14.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406 14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 14.4.1 PWM Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 14.4.2 PWM Channel Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424 14.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432 14.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
Chapter 15 Read-Only Memory 64K x 16 (ROM64KX16V1) Block Description
15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 15.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 15.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 15.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 15.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436 15.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436 15.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436 15.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 15.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 15.3.3 Non-volatile Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440 15.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440 15.4.1 ROM Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440 15.5 Initialization Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441 15.5.1 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441
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15.5.2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442
Chapter 16 Serial Communications Interface (SCIV2) Block Description
16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 16.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 16.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 16.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444 16.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445 16.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445 16.2.1 TXD-SCI Transmit Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445 16.2.2 RXD-SCI Receive Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445 16.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446 16.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446 16.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446 16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454 16.4.1 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455 16.4.2 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456 16.4.3 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457 16.4.4 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 16.4.5 Single-Wire Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469 16.4.6 Loop Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469 16.5 Initialization Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469 16.5.1 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469 16.5.2 Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 16.5.3 Recovery from Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471
Chapter 17 Serial Peripheral Interface (SPIV3) Block Description
17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477 17.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477 17.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477 17.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478 17.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478 17.2.1 MOSI -- Master Out/Slave In Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478 17.2.2 MISO -- Master In/Slave Out Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479 17.2.3 SS -- Slave Select Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479 17.2.4 SCK -- Serial Clock Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479 17.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479 17.3.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480
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17.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487 17.4.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488 17.4.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 17.4.3 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490 17.4.4 SPI Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493 17.4.5 Special Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494 17.4.6 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 17.4.7 Operation in Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 17.4.8 Operation in Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 17.4.9 Operation in Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 17.5 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497 17.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497 17.6.1 MODF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497 17.6.2 SPIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497 17.6.3 SPTEF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497
Chapter 18 Dual Output Voltage Regulator (VREG3V3V2) Block Description
18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499 18.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499 18.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499 18.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 18.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501 18.2.1 VDDR, VSSR -- Regulator Power Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501 18.2.2 VDDA, VSSA -- Regulator Reference Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501 18.2.3 VDD, VSS -- Regulator Output1 (Core Logic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502 18.2.4 VDDPLL, VSSPLL -- Regulator Output2 (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502 18.2.5 VREGEN -- Optional Regulator Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502 18.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503 18.3.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503 18.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503 18.4.1 REG -- Regulator Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504 18.4.2 Full-Performance Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504 18.4.3 Reduced-Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504 18.4.4 LVD -- Low-Voltage Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504 18.4.5 POR -- Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504 18.4.6 LVR -- Low-Voltage Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504 18.4.7 CTRL -- Regulator Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504 18.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505 18.5.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505 18.5.2 Low-Voltage Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505
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18.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505 18.6.1 LVI -- Low-Voltage Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505
Appendix A Electrical Characteristics
A.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507 A.1.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507 A.1.2 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507 A.1.3 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508 A.1.4 Current Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509 A.1.5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509 A.1.6 ESD Protection and Latch-up Immunity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 A.1.7 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 A.1.8 Power Dissipation and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 A.1.9 I/O Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513 A.1.10Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515 A.2 ATD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517 A.2.1 ATD Operating Characteristics In 5V Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517 A.2.2 ATD Operating Characteristics In 3.3V Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517 A.2.3 Factors influencing accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518 A.2.4 ATD accuracy (5V Range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519 A.2.5 ATD accuracy (3.3V Range). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520 A.3 Voltage Regulator Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522 A.4 Chip Power-up and LVI/LVR graphical explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522 A.5 Output Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523 A.5.1 Resistive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523 A.5.2 Capacitive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523 A.6 Reset, Oscillator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524 A.6.1 Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524 A.6.2 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525 A.6.3 Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526 A.7 MSCAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529 A.8 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529 A.8.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530 A.8.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531 A.9 External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533 A.9.1 General Muxed Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533
Appendix B Package Information
B.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537 B.2 112-pin LQFP package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 15
Section Number
Title
Page
B.3 80-pin QFP package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539
Appendix C Printed Circuit Board Proposal
MC3S12RG128 Data Sheet, Rev. 1.05 16 Freescale Semiconductor
Contents
Section Number Chapter 1 Chapter 2 Chapter 3 Chapter 4 Chapter 5 Chapter 6 Chapter 7 Chapter 8 Chapter 9 Chapter 10 Chapter 11 Chapter 12 Chapter 13 Chapter 14 Chapter 15 Chapter 16 Chapter 17 Chapter 18 Title Page
Device Overview (MC3S12RG128V1) . . . . . . . . . . . . . . . . . . . . 19 Port Integration Module (PIM3RG128V1) . . . . . . . . . . . . . . . . . 71 Module Mapping Control (MMCV5) . . . . . . . . . . . . . . . . . . . . . 113 Multiplexed External Bus Interface (MEBIV3) . . . . . . . . . . . . 131 Interrupt (INTV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Background Debug Module (BDMV4). . . . . . . . . . . . . . . . . . . 175 Breakpoint Module (BKPV1) . . . . . . . . . . . . . . . . . . . . . . . . . . 201 Analog-to-Digital Converter (ATD10B8CV3) . . . . . . . . . . . . . 213 Clocks and Reset Generator (CRGV4) . . . . . . . . . . . . . . . . . . 241 Enhanced Capture Timer (ECT16B8CV1). . . . . . . . . . . . . . . . 277 Inter-Integrated Circuit (IICV2) . . . . . . . . . . . . . . . . . . . . . . . . 319 Freescale's Scalable Controller Area Network (MSCANV2) . 343 Oscillator (OSCV2) Block Description . . . . . . . . . . . . . . . . . . 399 Pulse-Width Modulator (PWM8B8CV1). . . . . . . . . . . . . . . . . . 403 Read-Only Memory 64K x 16 (ROM64KX16V1) . . . . . . . . . . . 435 Serial Communications Interface (SCIV2) . . . . . . . . . . . . . . . 443 Serial Peripheral Interface (SPIV3) . . . . . . . . . . . . . . . . . . . . . 477 Dual Output Voltage Regulator (VREG3V3V2). . . . . . . . . . . . 499
Appendix A Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507 Appendix B Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537 Appendix C Printed Circuit Board Proposal . . . . . . . . . . . . . . . . . . . . . . . . 540
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 17
Section Number
Title
Page
MC3S12RG128 Data Sheet, Rev. 1.05 18 Freescale Semiconductor
Chapter 1 Device Overview (MC3S12RG128V1)
1.1 Introduction
The MC3S12RG128 microcontroller unit (MCU) is a 16-bit device composed of standard on-chip peripherals including a 16-bit central processing unit (CPU12), up to 128K bytes of ROM, 8K bytes of RAM, two asynchronous serial communications interfaces (SCI), two serial peripheral interfaces (SPI), IIC-bus, an enhanced capture timer (ECT), two 8-channel 10-bit analog-to-digital converters (ADC), an eight-channel pulse-width modulator (PWM), and up to two CAN 2.0 A, B software compatible modules (MSCAN12). There is no integrated EEPROM on the MC3S12RG128. The MC3S12RG128 has full 16-bit data paths throughout. However, the external bus can operate in an 8-bit narrow mode so single 8-bit wide memory can be interfaced for lower cost systems. The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational requirements.
1.1.1
*
Features
HCS12 Core -- 16-bit HCS12 CPU - Upward compatible with M68HC11 instruction set - Interrupt stacking and programmer's model identical to M68HC11 - 20-bit ALU - Instruction queue - Enhanced indexed addressing -- MEBI (Multiplexed External Bus Interface) -- MMC (Module Mapping Control) -- INT (Interrupt control) -- BKP (Breakpoints) -- BDM (Background Debug Module) CRG (Clock and Reset Generator) -- Choice of low current Colpitts oscillator or standard Pierce oscillator -- PLL -- COP watchdog -- Real time interrupt -- Clock monitor 8-bit and 4-bit ports with interrupt functionality -- Digital filtering
MC3S12RG128 Data Sheet, Rev. 1.05
*
*
Freescale Semiconductor
19
Chapter 1 Device Overview (MC3S12RG128V1)
*
*
*
*
*
*
*
*
*
-- Programmable rising and falling edge trigger Memory Options: -- 128K Byte or 64K Byte ROM -- 8K Byte RAM Two 8-channel Analog-to-Digital Converters -- 10-bit resolution -- External conversion trigger capability Two 1M bit per second, CAN 2.0 A, B software compatible modules -- Five receive and three transmit buffers -- Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit -- Four separate interrupt channels for Rx, Tx, error and wake-up -- Low-pass filter wake-up function -- Loop-back for self test operation Enhanced Capture Timer -- 16-bit main counter with 7-bit prescaler -- 8 programmable input capture or output compare channels -- Four 8-bit or two 16-bit pulse accumulators 8 PWM channels -- Programmable period and duty cycle -- 8-bit 8-channel or 16-bit 4-channel -- Separate control for each pulse width and duty cycle -- Center-aligned or left-aligned outputs -- Programmable clock select logic with a wide range of frequencies -- Fast emergency shutdown input -- Usable as interrupt inputs Serial interfaces -- Two asynchronous Serial Communications Interfaces (SCI) -- Two Synchronous Serial Peripheral Interface (SPI) Inter-IC Bus (IIC) -- Compatible with I2C Bus standard -- Multi-master operation -- Software programmable for one of 256 different serial clock frequencies Internal 2.5V Regulator -- Supports an input voltage range from 2.97V to 5.5V -- Low power mode capability -- Includes low voltage reset (LVR) circuitry -- Includes low voltage interrupt (LVI) circuitry 112-Pin LQFP and 80-Pin QFP package options -- I/O lines with 5V input and drive capability
MC3S12RG128 Data Sheet, Rev. 1.05
20
Freescale Semiconductor
Chapter 1 Device Overview (MC3S12RG128V1)
*
-- 5V A/D converter inputs -- Operation at 66 MHz equivalent to 33 MHz Bus Speed (single-chip modes only) -- Operation at 50 MHz equivalent to 25 MHz Bus Speed (expanded modes) Development support -- Single-wire background debugTM mode (BDM) -- On-chip hardware breakpoints
1.1.2
Modes of Operation
User modes: * Normal and Emulation Operating Modes -- Normal Single-Chip Mode -- Normal Expanded Wide Mode -- Normal Expanded Narrow Mode -- Emulation Expanded Wide Mode -- Emulation Expanded Narrow Mode * Special Operating Modes -- Special Single-Chip Mode with active Background Debug Mode -- Special Test Mode (Freescale use only) -- Special Peripheral Mode (Freescale use only) Low power modes: * Stop Mode * Pseudo Stop Mode * Wait Mode
1.1.3
Block Diagram
Figure 1-1 shows a block diagram of the MC3S12RG128 device.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 21
Chapter 1 Device Overview (MC3S12RG128V1)
128K Byte or 64K Byte ROM 8K Byte RAM
ATD0
VRH VRL VDDA VSSA PAD00 PAD01 PAD02 PAD03 PAD04 PAD05 PAD06 PAD07
ATD1
VRH VRL VDDA VSSA
VRH VRL VDDA VSSA PAD08 PAD09 PAD10 PAD11 PAD12 PAD13 PAD14 PAD15 PK0 PK1 PK2 PK3 PK4 PK5 PK7 PT0 PT1 PT2 PT3 PT4 PT5 PT6 PT7 PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PM0 PM1 PM2 PM3 PM4 PM5 PM6 PM7 PJ0 PJ1 PJ6 PJ7 PP0 PP1 PP2 PP3 PP4 PP5 PP6 PP7 PH0 PH1 PH2 PH3 PH4 PH5 PH6 PH7 XADDR14 XADDR15 XADDR16 XADDR17 XADDR18 XADDR19 ECS/ROMCTL
VDDR VSSR VREGEN VDD1,2 VSS1,2 BKGD XFC VDDPLL VSSPLL EXTAL XTAL RESET PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 TEST
Voltage Regulator
AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 PIX0 PIX1 PIX2 PIX3 PIX4 PIX5 ECS IOC0 IOC1 IOC2 IOC3 IOC4 IOC5 IOC6 IOC7 RXD TXD RXD TXD
AD0
Single-wire Background Debug Module Clock and Reset Generation Module
CPU12
DDRK DDRT DDRS
PPAGE
PLL
Periodic Interrupt COP Watchdog Clock Monitor Breakpoints
XIRQ IRQ System R/W Integration LSTRB Module ECLK (SIM) MODA MODB NOACC/XCLKS
DDRE
PTE
Enhanced Capture Timer
SCI0 SCI1
PTS
PTT
PTK
AD1
Multiplexed Address/Data Bus SPI0 DDRA PTA
DATA15 ADDR15 PA7 DATA14 ADDR14 PA6 DATA13 ADDR13 PA5 DATA12 ADDR12 PA4 DATA11 ADDR11 PA3 DATA10 ADDR10 PA2 DATA9 ADDR9 PA1 DATA8 ADDR8 PA0
MISO MOSI SCK SS RXCAN TXCAN
DDRB PTB
PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
CAN0
CAN4
RXCAN TXCAN
Multiplexed Wide Bus Multiplexed Narrow Bus I/O Driver 5V
VDDX VSSX
IIC
SDA SCL PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 MISO MOSI SCK SS
KWJ0 KWJ1 KWJ6 KWJ7 KWP0 KWP1 KWP2 KWP3 KWP4 KWP5 KWP6 KWP7 KWH0 KWH1 KWH2 KWH3 KWH4 KWH5 KWH6 KWH7
DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0
VDDPLL VSSPLL
VDD1,2 VSS1,2
A/D Converter 5V & Voltage Regulator Reference Voltage Regulator 5V & I/O
VDDA VSSA VDDR VSSR
SPI1
DDRH
Figure 1-1. MC3S12RG128 Block Diagram
MC3S12RG128 Data Sheet, Rev. 1.05 22 Freescale Semiconductor
PTH
PTP
PLL 2.5V
PWM
DDRP
Internal Logic 2.5V
Signals shown in Bold are not available on the 80 Pin Package
Module to Port Routing
DDRM DDRJ
ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0
DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0
PTJ
PTM
Chapter 1 Device Overview (MC3S12RG128V1)
1.1.4
Device Memory Map
Table 1-1 shows the device register memory map of the MC3S12RG128 after reset. Note that after reset the bottom 1K Bytes of RAM ($0000 - $03FF) are hidden by the register space.
Table 1-1. Device Memory Map
Address 0x0000-0x0017 0x0018 0x0019 0x001A-0x001B 0x001C-0x001F 0x0020-0x0027 0x0028-0x002F 0x0030-0x0033 0x0034-0x003F 0x0040-0x007F 0x0080-0x009F 0x00A0-0x00C7 0x00C8-0x00CF 0x00D0-0x00D7 0x00D8-0x00DF 0x00E0-0x00E7 0x00E8-0x00EF 0x00F0-0x00F7 0x00F8-0x00FF 0x0100-0x010F 0x0110-0x011B 0x011C-0x011F 0x0120-0x013F 0x0140-0x017F 0x0180-0x01BF 0x01C0-0x01FF 0x0200-0x023F 0x0240-0x027F 0x0280-0x02BF 0x02C0-0x02FF 0x0300-0x035F 0x0360-0x03FF 0x0000-0x1FFF Module CORE (Ports A, B, E, Modes, Inits, Test) Reserved Voltage Regulator (VREG3V3) Device ID register (PARTID) CORE (MEMSIZ, IRQ, HPRIO) Reserved CORE (Background Debug Module) CORE (PPAGE, Port K) Clock and Reset Generator (PLL, RTI, COP) Enhanced Capture Timer 16-bit 8 channels Analog to Digital Converter 10-bit 8 channels (ATD0) Pulse Width Modulator 8-bit 8 channels (PWM) Serial Communications Interface (SCI0) Serial Communications Interface (SCI1) Serial Peripheral Interface (SPI0) Inter IC Bus Reserved Serial Peripheral Interface (SPI1) Reserved ROM Control/Status Registers Reserved Reserved Analog to Digital Converter 10-bit 8 channels (ATD1) Freescale Scalable CAN (CAN0) Reserved Reserved Reserved Port Integration Module (PIM) Freescale Scalable CAN (CAN4) Reserved Reserved Reserved RAM array Size (Bytes) 24 1 1 2 4 8 8 4 12 64 32 40 8 8 8 8 8 8 8 16 12 4 32 64 64 64 64 64 64 64 96 160 8192
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 23
Chapter 1 Device Overview (MC3S12RG128V1)
Table 1-1. Device Memory Map
Address 0x4000-0x7FFF 0x8000-0xBFFF 0xC000-0xFFFF Fixed ROM array ROM Page Window Fixed ROM array incl. 256 bytes of Vector Space at $FF80 - $FFFF Module Size (Bytes) 16384 16384 16384
NOTE Reserved register space shown in Table 1-1 is not allocated to any module. Writing to these locations has no effect. Read access to these locations returns zero.
MC3S12RG128 Data Sheet, Rev. 1.05 24 Freescale Semiconductor
Chapter 1 Device Overview (MC3S12RG128V1)
1.1.5
Logical Address Map
$0000 $0400
$0000 $03FF
1K Register Space Mappable to any 2K Boundary 8K Bytes RAM Mappable to any 8K Boundary
$2000
$2000
$3FFF $4000 $4000
16K Fixed ROM
$7FFF $8000 $8000 EXT $BFFF $C000 $C000 16K Fixed ROM $FFFF $FF00 $FF00 $FFFF VECTORS NORMAL SINGLE CHIP VECTORS EXPANDED VECTORS SPECIAL SINGLE CHIP $FFFF BDM (If Active) 16K Page Window four * 16K ROM Pages
The figure shows a useful map, which is not the map out of reset. After reset the map is: $0000 - $03FF: Register Space $0000 - $1FFF: 8K RAM
Figure 1-2. MC3S12RG128 Memory Map (also applies to MC3S12RB128)
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 25
Chapter 1 Device Overview (MC3S12RG128V1)
$0000 $0400
$0000 $03FF
1K Register Space Mappable to any 2K Boundary
$2000
$2000
8K Bytes RAM Mappable to any 8K Boundary
$3FFF $4000 $4000
16K Fixed ROM
$7FFF $8000 $8000 EXT $BFFF $C000 $C000 16K Fixed ROM $FFFF $FF00 $FF00 $FFFF VECTORS NORMAL SINGLE CHIP VECTORS EXPANDED VECTORS SPECIAL SINGLE CHIP $FFFF BDM (If Active) 16K Page Window four * 16K ROM Pages
The figure shows a useful map, which is not the map out of reset. After reset the map is: $0000 - $03FF: Register Space $0000 - $1FFF: 8K RAM
Figure 1-3. MC3S12R64 Memory Map
NOTE To ensure compatibility with the MC9S12D64 FLASH devices, the internal RAM should not be remapped to a location outside of the first 16K page ($0000-$3FFF) in the memory map. The internal RAM of the MC9S12D64 device and the MC3S12R64 device differ in size (4K vs. 8K). Therefore re-mapping the internal RAM outside of the first 16K page results in different sizes of visible FLASH or ROM space: a 4K RAM will leave 12K of a 16K page unmasked while the 8K RAM will only leave 8K of a 16K page unmasked.
MC3S12RG128 Data Sheet, Rev. 1.05 26 Freescale Semiconductor
Chapter 1 Device Overview (MC3S12RG128V1)
1.1.6
Device Register Map
The following tables show the detailed register map of the MC3S12RG128 device. 0x0000-0x000F MEBI map 1 of 3 (HCS12 Multiplexed External Bus Interface
Address 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C 0x000D 0x000E 0x000F Name PORTA PORTB DDRA DDRB Reserved Reserved Reserved Reserved PORTE DDRE PEAR MODE PUCR RDRIV EBICTL Reserved Bit 7 R PA7 W R PB7 W R DDRA7 W R DDRB7 W R 0 W R 0 W R 0 W R 0 W R PE7 W R DDRE7 W R NOACCE W R MODC W R PUPKE W R RDPK W R 0 W R 0 W Bit 6 PA6 PB6 DDRA6 DDRB6 0 0 0 0 Bit 5 PA5 PB5 DDRA5 DDRB5 0 0 0 0 Bit 4 PA4 PB4 DDRA4 DDRB4 0 0 0 0 Bit 3 PA3 PB3 DDRA3 DDRB3 0 0 0 0 Bit 2 PA2 PB2 DDRA2 DDRB2 0 0 0 0 Bit 1 PA1 PB1 DDRA1 DDRB1 0 0 0 0 PE1 0 0 Bit 0 PA 0 PB0 DDRA0 DDRB0 0 0 0 0 PE0 0 0
PE6 DDRE6 0
PE5 DDRE5 PIPOE MODA 0 0 0 0
PE4 DDRE4 NECLK 0
PE3 DDRE3 LSTRE IVIS 0 0 0 0
PE2 DDRE2 RDWE 0 0 0 0 0
MODB 0 0 0 0
EMK PUPBE RDPB 0 0
EME PUPAE RDPA ESTR 0
PUPEE RDPE 0 0
0x0010-0x0014 MMC map 1 of 4 (HCS12 Module Mapping Control)
Address 0x0010 0x0011 Name INITRM INITRG R W R W Bit 7 RAM15 0 Bit 6 RAM14 REG14 Bit 5 RAM13 REG13 Bit 4 RAM12 REG12 Bit 3 RAM11 REG11 Bit 2 0 0 Bit 1 0 0 Bit 0 RAMHAL 0
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 27
Chapter 1 Device Overview (MC3S12RG128V1)
0x0010-0x0014 MMC map 1 of 4 (HCS12 Module Mapping Control)
0x0012 0x0013 0x0014 Reserved MISC Reserved R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EXSTR1 0
EXSTR0 0
ROMHM 0
ROMON 0
0x0015-0x0016 INT map 1 of 2 (HCS12 Interrupt)
Address 0x0015 0x0016 Name ITCR ITEST R W R W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 WRINT INT8 Bit 3 ADR3 INT6 Bit 2 ADR2 INT4 Bit 1 ADR1 INT2 Bit 0 ADR0 INT0
INTE
INTC
INTA
0x0017-0x0017 MMC map 2 of 4 (HCS12 Module Mapping Control)
Address 0x0017 Name MTST1 TEST ONLY R W Bit 7 Bit 7 Bit 6 6 Bit 5 5 Bit 4 4 Bit 3 3 Bit 2 2 Bit 1 1 Bit 0 Bit 0
0x0018-0x0018 Reserved
Address 0x0018 Name Reserved R W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
0x0019-0x0019 VREG3V3 (Voltage Regulator)
Address 0x0019 Name VREGCTRL R W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 LVDS Bit 1 LVIE Bit 0 LVIF
0x001A-0x001B Device ID Register (TABLE1-3)
Address 0x001A 0x001B Name PARTIDH PARTIDL R W R W Bit 7 ID15 ID7 Bit 6 ID14 ID6 Bit 5 ID13 ID5 Bit 4 ID12 ID4 Bit 3 ID11 ID3 Bit 2 ID10 ID2 Bit 1 ID9 ID1 Bit 0 ID8 ID0
0x001C-0x001D MMC map 3 of 4 (HCS12 Module Mapping Control, TABLE1-4)
Address 0x001C 0x001D Name MEMSIZ0 MEMSIZ1 Bit 7 R reg_sw0 W R rom_sw1 W Bit 6 0 rom_sw0 Bit 5 eep_sw1 0 Bit 4 eep_sw0 0 Bit 3 0 0 Bit 2 ram_sw2 0 Bit 1 ram_sw1 pag_sw1 Bit 0 ram_sw0 pag_sw0
MC3S12RG128 Data Sheet, Rev. 1.05 28 Freescale Semiconductor
Chapter 1 Device Overview (MC3S12RG128V1)
0x001E-0x001E MEBI map 2 of 3 (HCS12 Multiplexed External Bus Interface)
Address 0x001E Name INTCR R W Bit 7 IRQE Bit 6 IRQEN Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
0x001F-0x001F INT map 2 of 2 (HCS12 Interrupt)
Address 0x001F Name HPRIO R W Bit 7 PSEL7 Bit 6 PSEL6 Bit 5 PSEL5 Bit 4 PSEL4 Bit 3 PSEL3 Bit 2 PSEL2 Bit 1 PSEL1 Bit 0 0
0x0020-0x0027 Reserved
Address 0x0020 0x0027 Name Reserved R W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
0x0028-0x002F BKP (HCS12 Breakpoint)
Address 0x0028 0x0029 0x002A 0x002B 0x002C 0x002D 0x002E 0x002F Name BKPCT0 BKPCT1 BKP0X BKP0H BKP0L BKP1X BKP1H BKP1L Bit 7 R BKEN W R BK0MBH W R 0 W R Bit 15 W R Bit 7 W R 0 W R Bit 15 W R Bit 7 W Bit 6 BKFULL BK0MBL 0 Bit 5 BKBDM BK1MBH BK0V5 13 5 BK1V5 13 5 Bit 4 BKTAG BK1MBL BK0V4 12 4 BK1V4 12 4 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
BK0RWE BK0V3 11 3 BK1V3 11 3
BK0RW BK0V2 10 2 BK1V2 10 2
BK1RWE BK0V1 9 1 BK1V1 9 1
BK1RW BK0V0 Bit 8 Bit 0 BK1V0 Bit 8 Bit 0
14 6 0
14 6
0x0030-0x0031 MMC map 4 of 4 (HCS12 Module Mapping Control)
Address 0x0030 0x0031 Name PPAGE Reserved R W R W Bit 7 0 0 Bit 6 0 0 Bit 5 PIX5 0 Bit 4 PIX4 0 Bit 3 PIX3 0 Bit 2 PIX2 0 Bit 1 PIX1 0 Bit 0 PIX0 0
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 29
Chapter 1 Device Overview (MC3S12RG128V1)
0x0032-0x0033 MEBI map 3 of 3 (HCS12 Multiplexed External Bus Interface)
Address 0x0032 0x0033 Name PORTK DDRK R W R W Bit 7 PK7 DDRK7 Bit 6 PK6 DDRK6 Bit 5 PK5 DDRK5 Bit 4 PK4 DDRK4 Bit 3 PK3 DDRK3 Bit 2 PK2 DDRK2 Bit 1 PK1 DDRK1 Bit 0 PK0 DDRK0
0x0034-0x003F CRG (Clock and Reset Generator)
Address 0x0034 0x0035 0x0036 0x0037 0x0038 0x0039 0x003A 0x003B 0x003C 0x003D 0x003E 0x003F Name SYNR REFDV CTFLG TEST ONLY CRGFLG CRGINT CLKSEL PLLCTL RTICTL COPCTL FORBYP TEST ONLY CTCTL ARMCOP Bit 7 R 0 W R 0 W R 0 W R RTIF W R RTIE W R PLLSEL W R CME W R 0 W R WCOP W R 0 W R 0 W R 0 W Bit 7 Bit 6 0 0 0 Bit 5 SYN5 0 0 0 0 Bit 4 SYN4 0 0 Bit 3 SYN3 REFDV3 0 LOCK 0 Bit 2 SYN2 REFDV2 0 TRACK 0 Bit 1 SYN1 REFDV1 0 Bit 0 SYN0 REFDV0 0 SCM 0
PORF 0
LOCKIF LOCKIE ROAWAI ACQ RTR4 0 0 0 0 4
SCMIF SCMIE RTIWAI PCE RTR1 CR1 0 0 0 1
PSTP PLLON RTR6 RSBCK 0 0 0 6
SYSWAI AUTO RTR5 0 0 0 0 5
PLLWAI 0
CWAI PRE RTR2 CR2 0 0 0 2
COPWAI SCME RTR0 CR0 0 0 0 Bit 0
RTR3 0 0 0 0 3
0x0040-0x007F ECT (Enhanced Capture Timer 16 Bit 8 Channels)
Address 0x0040 0x0041 0x0042 0x0043 0x0044 Name TIOS CFORC OC7M OC7D TCNT (hi) R W R W R W R W R W Bit 7 IOS7 0 FOC7 OC7M7 OC7D7 Bit 15 Bit 6 IOS6 0 FOC6 OC7M6 OC7D6 14 Bit 5 IOS5 0 FOC5 OC7M5 OC7D5 13 Bit 4 IOS4 0 FOC4 OC7M4 OC7D4 12 Bit 3 IOS3 0 FOC3 OC7M3 OC7D3 11 Bit 2 IOS2 0 FOC2 OC7M2 OC7D2 10 Bit 1 IOS1 0 FOC1 OC7M1 OC7D1 9 Bit 0 IOS0 0 FOC0 OC7M0 OC7D0 Bit 8
MC3S12RG128 Data Sheet, Rev. 1.05 30 Freescale Semiconductor
Chapter 1 Device Overview (MC3S12RG128V1)
0x0040-0x007F ECT (Enhanced Capture Timer 16 Bit 8 Channels)
0x0045 0x0046 0x0047 0x0048 0x0049 0x004A 0x004B 0x004C 0x004D 0x004E 0x004F 0x0050 0x0051 0x0052 0x0053 0x0054 0x0055 0x0056 0x0057 0x0058 0x0059 0x005A 0x005B TCNT (lo) TSCR1 TTOV TCTL1 TCTL2 TCTL3 TCTL4 TIE TSCR2 TFLG1 TFLG2 TC0 (hi) TC0 (lo) TC1 (hi) TC1 (lo) TC2 (hi) TC2 (lo) TC3 (hi) TC3 (lo) TC4 (hi) TC4 (lo) TC5 (hi) TC5 (lo) R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 0 2 0 1 0 Bit 0 0
TEN TOV7 OM7 OM3 EDG7B EDG3B C7I TOI C7F TOF Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7
TSWAI TOV6 OL7 OL3 EDG7A EDG3A C6I 0
TSFRZ TOV5 OM6 OM2 EDG6B EDG2B C5I 0
TFFCA TOV4 OL6 OL2 EDG6A EDG2A C4I 0
TOV3 OM5 OM1 EDG5B EDG1B C3I TCRE C3F 0
TOV2 OL5 OL1 EDG5A EDG1A C2I PR2 C2F 0
TOV1 OM4 OM0 EDG4B EDG0B C1I PR1 C1F 0
TOV0 OL4 OL0 EDG4A EDG0A C0I PR0 C0F 0
C6F 0
C5F 0
C4F 0
14 6 14 6 14 6 14 6 14 6 14 6
13 5 13 5 13 5 13 5 13 5 13 5
12 4 12 4 12 4 12 4 12 4 12 4
11 3 11 3 11 3 11 3 11 3 11 3
10 2 10 2 10 2 10 2 10 2 10 2
9 1 9 1 9 1 9 1 9 1 9 1
Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 31
Chapter 1 Device Overview (MC3S12RG128V1)
0x0040-0x007F ECT (Enhanced Capture Timer 16 Bit 8 Channels)
0x005C 0x005D 0x005E 0x005F 0x0060 0x0061 0x0062 0x0063 0x0064 0x0065 0x0066 0x0067 0x0068 0x0069 0x006A 0x006B 0x006C 0x006D 0x006E 0x006F 0x0070 0x0071 0x0072 TC6 (hi) TC6 (lo) TC7 (hi) TC7 (lo) PACTL PAFLG PACN3 (hi) PACN2 (lo) PACN1 (hi) PACN0 (lo) MCCTL MCFLG ICPAR DLYCT ICOVW ICSYS Reserved TIMTST TEST ONLY Reserved Reserved PBCTL PBFLG PA3H R Bit 15 W R Bit 7 W R Bit 15 W R Bit 7 W R 0 W R 0 W R Bit 7 W R Bit 7 W R Bit 7 W R Bit 7 W R MCZI W R MCZF W R 0 W R 0 W R NOVW7 W R SH37 W R W R 0 W R W R W R 0 W R 0 W R Bit 7 W 14 6 14 6 PAEN 0 13 5 13 5 PAMOD 0 12 4 12 4 PEDGE 0 11 3 11 3 CLK1 0 10 2 10 2 CLK0 0 9 1 9 1 PAOVI PAOVF 1 1 1 1 MCPR1 POLF1 Bit 8 Bit 0 Bit 8 Bit 0 PAI PAIF Bit 0 Bit 0 Bit 0 Bit 0 MCPR0 POLF0
6 6 6 6 MODMC 0 0 0
5 5 5 5 RDMCL 0 0 0
4 4 4 4 0 ICLAT 0 0 0
3 3 3 3 0 FLMC POLF3
2 2 2 2 MCEN POLF2
PA3EN 0
PA2EN 0
PA1EN DLY1 NOVW1 BUFEN
PA0EN DLY0 NOVW0 LATQ
NOVW6 SH26
NOVW5 SH15
NOVW4 SH04
NOVW3 TFMOD
NOVW2 PACMX
0
0
0
0
0
TCBYP
0
PBEN 0 6
0 0 5
0 0 4
0 0 3
0 0 2
PBOVI PBOVF 1
0 0 Bit 0
MC3S12RG128 Data Sheet, Rev. 1.05 32 Freescale Semiconductor
Chapter 1 Device Overview (MC3S12RG128V1)
0x0040-0x007F ECT (Enhanced Capture Timer 16 Bit 8 Channels)
0x0073 0x0074 0x0075 0x0076 0x0077 0x0078 0x0079 0x007A 0x007B 0x007C 0x007D 0x007E 0x007F PA2H PA1H PA0H MCCNT (hi) MCCNT (lo) TC0H (hi) TC0H (lo) TC1H (hi) TC1H (lo) TC2H (hi) TC2H (lo) TC3H (hi) TC3H (lo) R W R W R W R W R W R W R W R W R W R W R W R W R W Bit 7 Bit 7 Bit 7 6 6 6 5 5 5 4 4 4 3 3 3 2 2 2 1 1 1 Bit 0 Bit 0 Bit 0
Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7
14 6 14 6 14 6 14 6 14 6
13 5 13 5 13 5 13 5 13 5
12 4 12 4 12 4 12 4 12 4
11 3 11 3 11 3 11 3 11 3
10 2 10 2 10 2 10 2 10 2
9 1 9 1 9 1 9 1 9 1
Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0
0x0080-0x009F ATD0 (Analog to Digital Converter 10 Bit 8 Channel)
Address 0x0080 0x0081 0x0082 0x0083 0x0084 0x0085 0x0086 0x0087 Name ATD0CTL0 ATD0CTL1 ATD0CTL2 ATD0CTL3 ATD0CTL4 ATD0CTL5 ATD0STAT0 Reserved R W R W R W R W R W R W R W R W Bit 7 0 0 Bit 6 0 0 Bit 5 0 0 Bit 4 0 0 Bit 3 0 0 Bit 2 0 0 Bit 1 0 0 Bit 0 0 0 ASCIF
ADPU 0
AFFC S8C SMP1 DSGN 0 0
AWAI S4C SMP0 SCAN ETORF 0
ETRIGLE S2C PRS4 MULT FIFOR 0
ETRIGP S1C PRS3 0 0 0
ETRIG FIFO PRS2 CC CC2 0
ASCIE FRZ1 PRS1 CB CC1 0
FRZ0 PRS0 CA CC0 0
SRES8 DJM SCF 0
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 33
Chapter 1 Device Overview (MC3S12RG128V1)
0x0080-0x009F ATD0 (Analog to Digital Converter 10 Bit 8 Channel)
0x0088 0x0089 0x008A 0x008B 0x008C 0x008D 0x008E 0x008F 0x0090 0x0091 0x0092 0x0093 0x0094 0x0095 0x0096 0x0097 0x0098 0x0099 0x009A 0x009B 0x009C ATD0TEST0 ATD0TEST1 Reserved ATD0STAT1 Reserved ATD0DIEN Reserved PORTAD0 ATD0DR0H ATD0DR0L ATD0DR1H ATD0DR1L ATD0DR2H ATD0DR2L ATD0DR3H ATD0DR3L ATD0DR4H ATD0DR4L ATD0DR5H ATD0DR5L ATD0DR6H R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 0 0 0 CCF7 0 0 0 0 CCF6 0 0 0 0 CCF5 0 0 0 0 CCF4 0 0 0 0 CCF3 0 0 0 0 CCF2 0 0 0 0 CCF1 0 0
SC 0 CCF0 0
Bit 7 0 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15
6 0 6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14
5 0 5 13 0 13 0 13 0 13 0 13 0 13 0 13
4 0 4 12 0 12 0 12 0 12 0 12 0 12 0 12
3 0 3 11 0 11 0 11 0 11 0 11 0 11 0 11
2 0 2 10 0 10 0 10 0 10 0 10 0 10 0 10
1 0 1 9 0 9 0 9 0 9 0 9 0 9 0 9
Bit 0 0 BIT 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8
MC3S12RG128 Data Sheet, Rev. 1.05 34 Freescale Semiconductor
Chapter 1 Device Overview (MC3S12RG128V1)
0x0080-0x009F ATD0 (Analog to Digital Converter 10 Bit 8 Channel)
0x009D 0x009E 0x009F ATD0DR6L ATD0DR7H ATD0DR7L R W R W R W Bit7 Bit15 Bit7 Bit6 14 Bit6 0 13 0 0 12 0 0 11 0 0 10 0 0 9 0 0 Bit8 0
0x00A0-0x00C7 PWM (Pulse Width Modulator 8 Bit 8 Channel)
Address 0x00A0 0x00A1 0x00A2 0x00A3 0x00A4 0x00A5 0x00A6 0x00A7 0x00A8 0x00A9 0x00AA 0x00AB 0x00AC 0x00AD 0x00AE 0x00AF 0x00B0 0x00B1 Name PWME Bit 7 Bit 6 PWME6 PPOL6 PCLK6 PCKB2 CAE6 CON45 0 0 Bit 5 PWME5 PPOL5 PCLK5 PCKB1 CAE5 CON23 0 0 Bit 4 PWME4 PPOL4 PCLK4 PCKB0 CAE4 CON01 0 0 Bit 3 PWME3 PPOL3 PCLK3 0 Bit 2 PWME2 PPOL2 PCLK2 PCKA2 CAE2 PFRZ 0 0 Bit 1 PWME1 PPOL1 PCLK1 PCKA1 CAE1 0 0 0 Bit 0 PWME0 PPOL0 PCLK0 PCKA0 CAE0 0 0 0 R PWME7 W R PWMPOL PPOL7 W R PWMCLK PCLK7 W R 0 PWMPRCLK W R PWMCAE CAE7 W R PWMCTL CON67 W R 0 PWMTST TEST ONLY W 0 PWMPRSC R TEST ONLY W R PWMSCLA Bit 7 W R PWMSCLB Bit 7 W 0 PWMSCNTA R TEST ONLY W 0 PWMSCNTB R TEST ONLY W R Bit 7 PWMCNT0 W 0 R Bit 7 PWMCNT1 W 0 R Bit 7 PWMCNT2 W 0 R Bit 7 PWMCNT3 W 0 R Bit 7 PWMCNT4 W 0 R Bit 7 PWMCNT5 W 0
CAE3 PSWAI 0 0
6 6 0 0 6 0 6 0 6 0 6 0 6 0 6 0
5 5 0 0 5 0 5 0 5 0 5 0 5 0 5 0
4 4 0 0 4 0 4 0 4 0 4 0 4 0 4 0
3 3 0 0 3 0 3 0 3 0 3 0 3 0 3 0
2 2 0 0 2 0 2 0 2 0 2 0 2 0 2 0
1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0
Bit 0 Bit 0 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 35
Chapter 1 Device Overview (MC3S12RG128V1)
0x00A0-0x00C7 PWM (Pulse Width Modulator 8 Bit 8 Channel)
0x00B2 0x00B3 0x00B4 0x00B5 0x00B6 0x00B7 0x00B8 0x00B9 0x00BA 0x00BB 0x00BC 0x00BD 0x00BE 0x00BF 0x00C0 0x00C1 0x00C2 0x00C3 0x00C4 0x00C5 0x00C6 0x00C7 PWMCNT6 PWMCNT7 PWMPER0 PWMPER1 PWMPER2 PWMPER3 PWMPER4 PWMPER5 PWMPER6 PWMPER7 PWMDTY0 PWMDTY1 PWMDTY2 PWMDTY3 PWMDTY4 PWMDTY5 PWMDTY6 PWMDTY7 PWMSDN Reserved Reserved Reserved R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit 7 0 Bit 7 0 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 PWMIF 0 0 0 6 0 6 0 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 PWMIE 0 0 0 5 0 5 0 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 PWMRST RT 0 0 0 4 0 4 0 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 PWMLVL 0 0 0 3 0 3 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 0 0 0 0 2 0 2 0 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 PWM7IN 0 0 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 PWM7INL 0 0 0 Bit 0 0 Bit 0 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 PWM7EN A 0 0 0
MC3S12RG128 Data Sheet, Rev. 1.05 36 Freescale Semiconductor
Chapter 1 Device Overview (MC3S12RG128V1)
0x00C8-0x00CF SCI0 (Asynchronous Serial Interface)
Address 0x00C8 0x00C9 0x00CA 0x00CB 0x00CC 0x00CD 0x00CE 0x00CF Name SCI0BDH SCI0BDL SCI0CR1 SCI0CR2 SCI0SR1 SCI0SR2 SCI0DRH SCI0DRL R W R W R W R W R W R W R W R W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 SBR12 SBR4 M ILIE IDLE 0 0 R4 T4 Bit 3 SBR11 SBR3 WAKE TE OR 0 0 R3 T3 Bit 2 SBR10 SBR2 ILT RE NF Bit 1 SBR9 SBR1 PE RWU FE Bit 0 SBR8 SBR0 PT SBK PF RAF 0 R0 T0
SBR7 LOOPS TIE TDRE 0 R8 R7 T7
SBR6 SCISWAI TCIE TC 0
SBR5 RSRC RIE RDRF 0 0 R5 T5
BRK13 0 R2 T2
TXDIR 0 R1 T1
T8 R6 T6
0x00D0-0x00D7 SCI1 (Asynchronous Serial Interface)
Address 0x00D0 0x00D1 0x00D2 0x00D3 0x00D4 0x00D5 0x00D6 0x00D7 Name SCI1BDH SCI1BDL SCI1CR1 SCI1CR2 SCI1SR1 SCI1SR2 SCI1DRH SCI1DRL R W R W R W R W R W R W R W R W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 SBR12 SBR4 M ILIE IDLE 0 0 R4 T4 Bit 3 SBR11 SBR3 WAKE TE OR 0 0 R3 T3 Bit 2 SBR10 SBR2 ILT RE NF Bit 1 SBR9 SBR1 PE RWU FE Bit 0 SBR8 SBR0 PT SBK PF RAF 0 R0 T0
SBR7 LOOPS TIE TDRE 0 R8 R7 T7
SBR6 SCISWAI TCIE TC 0
SBR5 RSRC RIE RDRF 0 0 R5 T5
BRK13 0 R2 T2
TXDIR 0 R1 T1
T8 R6 T6
0x00D8-0x00DF SPI0 (Serial Peripheral Interface)
Address 0x00D8 0x00D9 0x00DA Name SPI0CR1 SPI0CR2 SPI0BR R W R W R W Bit 7 SPIE 0 0 Bit 6 SPE 0 Bit 5 SPTIE 0 Bit 4 MSTR MODFEN SPPR0 Bit 3 CPOL BIDIROE 0 Bit 2 CPHA 0 Bit 1 SSOE SPISWAI SPR1 Bit 0 LSBFE SPC0 SPR0
SPPR2
SPPR1
SPR2
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 37
Chapter 1 Device Overview (MC3S12RG128V1)
0x00D8-0x00DF SPI0 (Serial Peripheral Interface)
0x00DB 0x00DC 0x00DD 0x00DE 0x00DF SPI0SR Reserved SPI0DR Reserved Reserved R W R W R W R W R W SPIF 0 0 0 SPTEF 0 MODF 0 0 0 0 0 0 0 0 0
Bit7 0 0
6 0 0
5 0 0
4 0 0
3 0 0
2 0 0
1 0 0
Bit0 0 0
0x00E0-0x00E7 IIC (Inter IC Bus)
Address 0x00E0 0x00E1 0x00E2 0x00E3 0x00E4 0x00E5 0x00E6 0x00E7 Name IBAD IBFD IBCR IBSR IBDR Reserved Reserved Reserved R W R W R W R W R W R W R W R W Bit 7 ADR7 IBC7 IBEN TCF Bit 6 ADR6 IBC6 IBIE IAAS Bit 5 ADR5 IBC5 MS/SL IBB Bit 4 ADR4 IBC4 TX/RX IBAL D4 0 0 0 Bit 3 ADR3 IBC3 TXAK 0 Bit 2 ADR2 IBC2 0 RSTA SRW Bit 1 ADR1 IBC1 0 Bit 0 0 IBC0 IBSWAI RXAK
IBIF D1 0 0 0
D7 0 0 0
D6 0 0 0
D5 0 0 0
D3 0 0 0
D2 0 0 0
D0 0 0 0
0x00E8-0x00EF Reserved
Address 0x00E8 0x00EF Name Reserved R W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
0x00F0-0x00F7 SPI1(Serial Peripheral Interface)
Address 0x00F0 0x00F1 0x00F2 0x00F3 Name SPI1CR1 SPI1CR2 SPI1BR SPI1SR R W R W R W R W Bit 7 SPIE 0 0 SPIF Bit 6 SPE 0 Bit 5 SPTIE 0 Bit 4 MSTR MODFEN SPPR0 MODF Bit 3 CPOL BIDIROE 0 0 Bit 2 CPHA 0 Bit 1 SSOE SPISWAI SPR1 0 Bit 0 LSBFE SPC0 SPR0 0
SPPR2 0
SPPR1 SPTEF
SPR2 0
MC3S12RG128 Data Sheet, Rev. 1.05 38 Freescale Semiconductor
Chapter 1 Device Overview (MC3S12RG128V1)
0x00F0-0x00F7 SPI1(Serial Peripheral Interface)
0x00F4 0x00F5 0x00F6 0x00F7 Reserved SPI1DR Reserved Reserved R W R W R W R W 0 0 0 0 0 0 0 0
Bit7 0 0
6 0 0
5 0 0
4 0 0
3 0 0
2 0 0
1 0 0
Bit0 0 0
0x00F8-0x00FF Reserved
Address 0x00F8 0x00FF Name Reserved R W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
0x0100-0x010F ROM Control/Status Registers
Address 0x0100 0x0101 0x0102 0x0103 0x0104 0x0105 0x0106 0x0107 0x0108 0x0109 0x010A 0x010B 0x010C Name Reserved ROPT Reserved RCNFG Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RDSC0 Bit 7 R 0 W R KEYEN1 W R 0 W R 0 W R 0 W R 0 W R 0 W R 0 W R 0 W R 0 W R 0 W R 0 W R W Bit 6 0 KEYEN0 0 0 0 0 0 0 0 0 0 0 Bit 5 0 NV5 0 Bit 4 0 NV4 0 0 0 0 0 0 0 0 0 0 DSC0[7:0] Bit 3 0 NV3 0 0 0 0 0 0 0 0 0 0 Bit 2 0 NV2 0 0 0 0 0 0 0 0 0 0 Bit 1 0 SEC1 0 0 0 0 0 0 0 0 0 0 Bit 0 0 SEC0 0 0 0 0 0 0 0 0 0 0
KEYACC 0 0 0 0 0 0 0 0
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 39
Chapter 1 Device Overview (MC3S12RG128V1)
0x0100-0x010F ROM Control/Status Registers
0x010D 0x010E 0x010F RDSC1 RDSC2 Reserved R W R W R W DSC1[7:0] DSC2[7:0] 0 0 0 0 0 0 0 0
0x0110-0x011B Reserved
Address 0x0110 0x011B Name Reserved R W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
0x011C-0x011F Reserved for RAM Control Registers
Address 0x011C0x011F Name Reserved R W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
0x0120-0x013F ATD1 (Analog to Digital Converter 10 Bit 8 Channel)
Address 0x0120 0x0121 0x0122 0x0123 0x0124 0x0125 0x0126 0x0127 0x0128 0x0129 0x012A 0x012B 0x012C Name ATD1CTL0 ATD1CTL1 ATD1CTL2 ATD1CTL3 ATD1CTL4 ATD1CTL5 ATD1STAT0 Reserved ATD1TEST0 ATD1TEST1 Reserved ATD1STAT1 Reserved R W R W R W R W R W R W R W R W R W R W R W R W R W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 SBR12 SBR4 M ILIE IDLE 0 0 R4 T4 SBR12 SBR4 M ILIE IDLE Bit 3 SBR11 SBR3 WAKE TE OR 0 0 R3 T3 SBR11 SBR3 WAKE TE OR Bit 2 SBR10 SBR2 ILT RE NF Bit 1 SBR9 SBR1 PE RWU FE Bit 0 SBR8 SBR0 PT SBK PF RAF 0 R0 T0 SBR8 SBR0 PT SBK PF
SBR7 LOOPS TIE TDRE 0 R8 R7 T7 0
SBR6 SCISWAI TCIE TC 0
SBR5 RSRC RIE RDRF 0 0 R5 T5 0
BRK13 0 R2 T2 SBR10 SBR2 ILT RE NF
TXDIR 0 R1 T1 SBR9 SBR1 PE RWU FE
T8 R6 T6 0
SBR7 LOOPS TIE TDRE
SBR6 SCISWAI TCIE TC
SBR5 RSRC RIE RDRF
MC3S12RG128 Data Sheet, Rev. 1.05 40 Freescale Semiconductor
Chapter 1 Device Overview (MC3S12RG128V1)
0x0120-0x013F ATD1 (Analog to Digital Converter 10 Bit 8 Channel)
0x012D 0x012E 0x012F 0x0130 0x0131 0x0132 0x0133 0x0134 0x0135 0x0136 0x0137 0x0138 0x0139 0x013A 0x013B 0x013C 0x013D 0x013E 0x013F ATD1DIEN Reserved PORTAD1 ATD1DR0H ATD1DR0L ATD1DR1H ATD1DR1L ATD1DR2H ATD1DR2L ATD1DR3H ATD1DR3L ATD1DR4H ATD1DR4L ATD1DR5H ATD1DR5L ATD1DR6H ATD1DR6L ATD1DR7H ATD1DR7L R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 0 R8 R7 T7 0 0 0 0 R5 T5 0 0 0 R4 T4 SBR12 SBR4 M ILIE IDLE 0 0 R4 T4 SBR12 SBR4 M ILIE IDLE 0 0 R4 T4 0 0 R3 T3 SBR11 SBR3 WAKE TE OR 0 0 R3 T3 SBR11 SBR3 WAKE TE OR 0 0 R3 T3 BRK13 0 R2 T2 SBR10 SBR2 ILT RE NF TXDIR 0 R1 T1 SBR9 SBR1 PE RWU FE RAF 0 R0 T0 SBR8 SBR0 PT SBK PF RAF 0 R0 T0 SBR8 SBR0 PT SBK PF RAF 0 R0 T0
T8 R6 T6 0
SBR7 LOOPS TIE TDRE 0 R8 R7 T7 0
SBR6 SCISWAI TCIE TC 0
SBR5 RSRC RIE RDRF 0 0 R5 T5 0
BRK13 0 R2 T2 SBR10 SBR2 ILT RE NF
TXDIR 0 R1 T1 SBR9 SBR1 PE RWU FE
T8 R6 T6 0
SBR7 LOOPS TIE TDRE 0 R8 R7 T7
SBR6 SCISWAI TCIE TC 0
SBR5 RSRC RIE RDRF 0 0 R5 T5
BRK13 0 R2 T2
TXDIR 0 R1 T1
T8 R6 T6
0x0140-0x017F CAN0 (Freescale Scalable CAN - MSCAN)
Address 0x0140 0x0141 Name CAN0CTL0 CAN0CTL1 Bit 7 R RXFRM W R CANE W Bit 6 RXACT Bit 5 CSWAI LOOPB Bit 4 SYNCH Bit 3 TIME 0 Bit 2 WUPE WUPM Bit 1 SLPRQ SLPAK Bit 0 INITRQ INITAK
CLKSRC
LISTEN
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 41
Chapter 1 Device Overview (MC3S12RG128V1)
0x0140-0x017F CAN0 (Freescale Scalable CAN - MSCAN)
0x0142 0x0143 0x0144 0x0145 0x0146 0x0147 0x0148 0x0149 0x014A 0x014B 0x014C 0x014D 0x014E 0x014F CAN0BTR0 CAN0BTR1 CAN0RFLG CAN0RIER CAN0TFLG CAN0TIER CAN0TARQ CAN0TAAK CAN0TBSEL CAN0IDAC Reserved Reserved CAN0RXERR CAN0TXERR R SJW1 W R SAMP W R WUPIF W R WUPIE W R 0 W R 0 W R 0 W R 0 W R 0 W R 0 W R 0 W R 0 W R RXERR7 W R TXERR7 W R AC7 W R AM7 W R AC7 W R AM7 W R W R W SJW0 TSEG22 CSCIF CSCIE 0 0 0 0 0 0 0 0 RXERR6 TXERR6 BRP5 TSEG21 RSTAT1 BRP4 TSEG20 RSTAT0 BRP3 TSEG13 TSTAT1 BRP2 TSEG12 TSTAT0 BRP1 TSEG11 OVRIF OVRIE TXE1 TXEIE1 ABTRQ1 ABTAK1 BRP0 TSEG10 RXF RXFIE TXE0 TXEIE0 ABTRQ0 ABTAK0
RSTATE1 0 0 0 0 0
RSTATE0 0 0 0 0 0
TSTATE1 0 0 0 0 0 0 0 0 RXERR3 TXERR3
TSTATE0 TXE2 TXEIE2 ABTRQ2 ABTAK2
TX2 IDHIT2 0 0 RXERR2 TXERR2
TX1 IDHIT1 0 0 RXERR1 TXERR1
TX0 IDHIT0 0 0 RXERR0 TXERR0
IDAM1 0 0 RXERR5 TXERR5
IDAM0 0 0 RXERR4 TXERR4
0x0150 - CAN0IDAR0 0x0153 CAN0IDAR3 0x0154 - CAN0IDMR0 0x0157 CAN0IDMR3 0x0158 - CAN0IDAR4 0x015B CAN0IDAR7 0x015C- CAN0IDMR4 0x015F CAN0IDMR7 0x0160 0x016F 0x0170 0x017F CAN0RXFG
AC6 AM6 AC6 AM6
AC5 AM5 AC5 AM5
AC4 AM4 AC4 AM4
AC3 AM3 AC3 AM3
AC2 AM2 AC2 AM2
AC1 AM1 AC1 AM1
AC0 AM0 AC0 AM0
FOREGROUND RECEIVE BUFFER (See Detailed MSCAN Foreground Receive and Transmit Buffer Layout) FOREGROUND TRANSMIT BUFFER (See Detailed MSCAN Foreground Receive and Transmit Buffer Layout)
CAN0TXFG
MC3S12RG128 Data Sheet, Rev. 1.05 42 Freescale Semiconductor
Chapter 1 Device Overview (MC3S12RG128V1)
Detailed MSCAN Foreground Receive and Transmit Buffer Layout
Address 0xXXX0 Name R R W R R W R R W R R W R CANxRDSR0- W CANxRDSR7 CANRxDLR Reserved R W R W R W R W R W R W R W R W R W R W R W R W R W R W Extended ID Standard ID CANxRIDR0 Extended ID Standard ID CANxRIDR1 Extended ID Standard ID CANxRIDR2 Extended ID Standard ID CANxRIDR3 Bit 7 ID28 ID10 ID20 ID2 ID14 Bit 6 ID27 ID9 ID19 ID1 ID13 Bit 5 ID26 ID8 ID18 ID0 ID12 Bit 4 ID25 ID7 SRR=1 RTR ID11 Bit 3 ID24 ID6 IDE=1 IDE=0 ID10 Bit 2 ID23 ID5 ID17 Bit 1 ID22 ID4 ID16 Bit 0 ID21 ID3 ID15
0xXXX1
ID9
ID8
ID7
0xXXX2
ID6
ID5
ID4
ID3
ID2
ID1
ID0
RTR
0xXXX3 0xXXX4 - 0xXXXB 0xXXXC 0xXXXD
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DLC3
DLC2
DLC1
DLC0
0xXXXE CANxRTSRH 0xXXXF CANxRTSRL Extended ID CANxTIDR0 Standard ID Extended ID CANxTIDR1 Standard ID Extended ID CANxTIDR2 Standard ID Extended ID CANxTIDR3 Standard ID
TSR15 TSR7
TSR14 TSR6
TSR13 TSR5
TSR12 TSR4
TSR11 TSR3
TSR10 TSR2
TSR9 TSR1
TSR8 TSR0
ID28 ID10 ID20 ID2 ID14
ID27 ID9 ID19 ID1 ID13
ID26 ID8 ID18 ID0 ID12
ID25 ID7 SRR=1 RTR ID11
ID24 ID6 IDE=1 IDE=0 ID10
ID23 ID5 ID17
ID22 ID4 ID16
ID21 ID3 ID15
0xXX10
0xXX0x XX10
ID9
ID8
ID7
0xXX12
ID6
ID5
ID4
ID3
ID2
ID1
ID0
RTR
0xXX13
0xXX14 CANxTDSR0- - CANxTDSR7 0xXX1B 0xXX1C CANxTDLR
DB7
DB6
DB5
DB4
DB3 DLC3
DB2 DLC2
DB1 DLC1
DB0 DLC0
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 43
Chapter 1 Device Overview (MC3S12RG128V1)
Detailed MSCAN Foreground Receive and Transmit Buffer Layout
0xXX1D 0xXX1E 0xXX1F R W R CANxTTSRH W R CANxTTSRL W CANxTTBPR PRIO7 TSR15 TSR7 PRIO6 TSR14 TSR6 PRIO5 TSR13 TSR5 PRIO4 TSR12 TSR4 PRIO3 TSR11 TSR3 PRIO2 TSR10 TSR2 PRIO1 TSR9 TSR1 PRIO0 TSR8 TSR0
0x0180-0x023F Reserved
Address 0x0180 0x023F Name Reserved R W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
0x0240-0x027F PIM (Port Integration Module)
Address 0x0240 0x0241 0x0242 0x0243 0x0244 0x0245 0x0246 0x0247 0x0248 0x0249 0x024A 0x024B 0x024C 0x024D 0x024E 0x024F Name PTT PTIT DDRT RDRT PERT PPST Reserved Reserved PTS PTIS DDRS RDRS PERS PPSS WOMS Reserved Bit 7 R PTT7 W R PTIT7 W R DDRT7 W R RDRT7 W R PERT7 W R PPST7 W R 0 W R 0 W R PTS7 W R PTIS7 W R DDRS7 W R RDRS7 W R PERS7 W R PPSS7 W R WOMS7 W R 0 W Bit 6 PTT6 PTIT6 Bit 5 PTT5 PTIT5 Bit 4 PTT4 PTIT4 Bit 3 PTT3 PTIT3 Bit 2 PTT2 PTIT2 Bit 1 PTT1 PTIT1 Bit 0 PTT0 PTIT0
DDRT7 RDRT6 PERT6 PPST6 0 0
DDRT5 RDRT5 PERT5 PPST5 0 0
DDRT4 RDRT4 PERT4 PPST4 0 0
DDRT3 RDRT3 PERT3 PPST3 0 0
DDRT2 RDRT2 PERT2 PPST2 0 0
DDRT1 RDRT1 PERT1 PPST1 0 0
DDRT0 RDRT0 PERT0 PPST0 0 0
PTS6 PTIS6
PTS5 PTIS5
PTS4 PTIS4
PTS3 PTIS3
PTS2 PTIS2
PTS1 PTIS1
PTS0 PTIS0
DDRS7 RDRS6 PERS6 PPSS6 WOMS6 0
DDRS5 RDRS5 PERS5 PPSS5 WOMS5 0
DDRS4 RDRS4 PERS4 PPSS4 WOMS4 0
DDRS3 RDRS3 PERS3 PPSS3 WOMS3 0
DDRS2 RDRS2 PERS2 PPSS2 WOMS2 0
DDRS1 RDRS1 PERS1 PPSS1 WOMS1 0
DDRS0 RDRS0 PERS0 PPSS0 WOMS0 0
MC3S12RG128 Data Sheet, Rev. 1.05 44 Freescale Semiconductor
Chapter 1 Device Overview (MC3S12RG128V1)
0x0240-0x027F PIM (Port Integration Module)
0x0250 0x0251 0x0252 0x0253 0x0254 0x0255 0x0256 0x0257 0x0258 0x0259 0x025A 0x025B 0x025C 0x025D 0x025E 0x025F 0x0260 0x0261 0x0262 0x0263 0x0264 0x0265 0x0266 PTM PTIM DDRM RDRM PERM PPSM WOMM MODRR PTP PTIP DDRP RDRP PERP PPSP PIEP PIFP PTH PTIH DDRH RDRH PERH PPSH PIEH R PTM7 W R PTIM7 W R DDRM7 W R RDRM7 W R PERM7 W R PPSM7 W R WOMM7 W R 0 W R PTP7 W R PTIP7 W R DDRP7 W R RDRP7 W R PERP7 W R PPSP7 W R PIEP7 W R PIFP7 W R PTH7 W R PTIH7 W R DDRH7 W R RDRH7 W R PERH7 W R PPSH7 W R PIEH7 W PTM6 PTIM6 PTM5 PTIM5 PTM4 PTIM4 PTM3 PTIM3 PTM2 PTIM2 PTM1 PTIM1 PTM0 PTIM0
DDRM7 RDRM6 PERM6 PPSM6 WOMM6 0
DDRM5 RDRM5 PERM5 PPSM5 WOMM5 MODRR5 PTP5 PTIP5
DDRM4 RDRM4 PERM4 PPSM4 WOMM4 MODRR4 PTP4 PTIP4
DDRM3 RDRM3 PERM3 PPSM3 WOMM3 MODRR3 PTP3 PTIP3
DDRM2 RDRM2 PERM2 PPSM2 WOMM2 MODRR2 PTP2 PTIP2
DDRM1 RDRM1 PERM1 PPSM1 WOMM1 MODRR1 PTP1 PTIP1
DDRM0 RDRM0 PERM0 PPSM0 WOMM0 MODRR0 PTP0 PTIP0
PTP6 PTIP6
DDRP7 RDRP6 PERP6 PPSP6 PIEP6 PIFP6 PTH6 PTIH6
DDRP5 RDRP5 PERP5 PPSP5 PIEP5 PIFP5 PTH5 PTIH5
DDRP4 RDRP4 PERP4 PPSP4 PIEP4 PIFP4 PTH4 PTIH4
DDRP3 RDRP3 PERP3 PPSP3 PIEP3 PIFP3 PTH3 PTIH3
DDRP2 RDRP2 PERP2 PPSP2 PIEP2 PIFP2 PTH2 PTIH2
DDRP1 RDRP1 PERP1 PPSP1 PIEP1 PIFP1 PTH1 PTIH1
DDRP0 RDRP0 PERP0 PPSS0 PIEP0 PIFP0 PTH0 PTIH0
DDRH7 RDRH6 PERH6 PPSH6 PIEH6
DDRH5 RDRH5 PERH5 PPSH5 PIEH5
DDRH4 RDRH4 PERH4 PPSH4 PIEH4
DDRH3 RDRH3 PERH3 PPSH3 PIEH3
DDRH2 RDRH2 PERH2 PPSH2 PIEH2
DDRH1 RDRH1 PERH1 PPSH1 PIEH1
DDRH0 RDRH0 PERH0 PPSH0 PIEH0
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 45
Chapter 1 Device Overview (MC3S12RG128V1)
0x0240-0x027F PIM (Port Integration Module)
0x0267 0x0268 0x0269 0x026A 0x026B 0x026C 0x026D 0x026E 0x026F 0x0270 0x027F PIFH PTJ PTIJ DDRJ RDRJ PERJ PPSJ PIEJ PIFJ Reserved R W R W R W R W R W R W R W R W R W R W PIFH7 PTJ7 PTIJ7 PIFH6 PTJ6 PTIJ6 PIFH5 0 0 0 0 0 0 0 0 0 PIFH4 0 0 0 0 0 0 0 0 0 PIFH3 0 0 0 0 0 0 0 0 0 PIFH2 0 0 0 0 0 0 0 0 0 PIFH1 PTJ1 PTIJ1 PIFH0 PTJ0 PTIJ0
DDRJ7 RDRJ7 PERJ7 PPSJ7 PIEJ7 PIFJ7 0
DDRJ7 RDRJ6 PERJ6 PPSJ6 PIEJ6 PIFJ6 0
DDRJ1 RDRJ1 PERJ1 PPSJ1 PIEJ1 PIFJ1 0
DDRJ0 RDRJ0 PERJ0 PPSJ0 PIEJ0 PIFJ0 0
0x0280-0x02BF CAN4 (Freescale Scalable CAN - MSCAN)
Address 0x0280 0x0281 0x0282 0x0283 0x0284 0x0285 0x0286 0x0287 0x0288 0x0289 0x028A Name CAN4CTL0 Bit 7 Bit 6 RXACT Bit 5 CSWAI LOOPB BRP5 TSEG21 RSTAT1 Bit 4 SYNCH Bit 3 TIME 0 Bit 2 WUPE WUPM BRP2 TSEG12 TSTAT0 Bit 1 SLPRQ SLPAK Bit 0 INITRQ INITAK R RXFRM W R CAN4CTL1 CANE W R CAN4BTR0 SJW1 W R CAN4BTR1 SAMP W R CAN4RFLG WUPIF W R CAN4RIER WUPIE W R 0 CAN4TFLG W R 0 CAN4TIER W R 0 CAN4TARQ W R 0 CAN4TAAK W R 0 CAN4TBSEL W
CLKSRC SJW0 TSEG22 CSCIF CSCIE 0 0 0 0 0
LISTEN BRP4 TSEG20 RSTAT0
BRP3 TSEG13 TSTAT1
BRP1 TSEG11 OVRIF OVRIE TXE1 TXEIE1 ABTRQ1 ABTAK1
BRP0 TSEG10 RXF RXFIE TXE0 TXEIE0 ABTRQ0 ABTAK0
RSTATE1 0 0 0 0 0
RSTATE0 0 0 0 0 0
TSTATE1 0 0 0 0 0
TSTATE0 TXE2 TXEIE2 ABTRQ2 ABTAK2
TX2
TX1
TX0
MC3S12RG128 Data Sheet, Rev. 1.05 46 Freescale Semiconductor
Chapter 1 Device Overview (MC3S12RG128V1)
0x0280-0x02BF CAN4 (Freescale Scalable CAN - MSCAN)
0x028B 0x028C 0x028D 0x028E 0x028F CAN4IDAC Reserved Reserved CAN4RXERR CAN4TXERR R 0 W R 0 W R 0 W R RXERR7 W R TXERR7 W R AC7 W R AM7 W R AC7 W R AM7 W R W R W 0 0 0 RXERR6 TXERR6 IDAM1 0 0 RXERR5 TXERR5 IDAM0 0 0 RXERR4 TXERR4 0 0 0 RXERR3 TXERR3 IDHIT2 0 0 RXERR2 TXERR2 IDHIT1 0 0 RXERR1 TXERR1 IDHIT0 0 0 RXERR0 TXERR0
0x0290 - CAN4IDAR0 0x0293 CAN4IDAR3 0x0294 - CAN4IDMR0 0x0297 CAN4IDMR3 0x0298 - CAN4IDAR4 0x029B CAN4IDAR7 0x029C- CAN4IDMR4 0x029F CAN4IDMR7 0x02A0 0x02AF 0x02B0 0x02BF CAN4RXFG
AC6 AM6 AC6 AM6
AC5 AM5 AC5 AM5
AC4 AM4 AC4 AM4
AC3 AM3 AC3 AM3
AC2 AM2 AC2 AM2
AC1 AM1 AC1 AM1
AC0 AM0 AC0 AM0
FOREGROUND RECEIVE BUFFER (See Detailed MSCAN Foreground Receive and Transmit Buffer Layout) FOREGROUND TRANSMIT BUFFER (See Detailed MSCAN Foreground Receive and Transmit Buffer Layout)
CAN4TXFG
0x02C0-0x03FF Reserved
Address 0x02C00x03FF Name Reserved R W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
1.1.7
Part ID Assignments
The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses 0x001A and 0x001B after reset). The read-only value is a unique part ID for each revision of the chip. Table 1-2 shows the assigned part ID number and Mask Set number.
Table 1-2. Assigned Part ID Numbers
Device MC3S12RG128
1
Mask Set Number 2M38B
Part ID1 0x0682
The coding is as follows: Bit 15-12: Major family identifier Bit 11-8: Minor family identifier Bit 7-4: Major mask set revision number including FAB transfers Bit 3-0: Minor -- non full -- mask set revision
The device memory sizes are located in two 8-bit registers MEMSIZ0 and MEMSIZ1 (addresses $001C and $001D after reset). Table 1-3 shows the read-only values of these registers. Refer to HCS12 Module Mapping Control (MMC) Block Guide for further details.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 47
Chapter 1 Device Overview (MC3S12RG128V1)
Table 1-3. Memory size registers
Register name MEMSIZ0 MEMSIZ1 Constant value 0x03 0x80
1.2
Signal Description
This section describes signals that connect off chip. It includes a pinout diagram, a table of signal properties, and detailed discussion of signals. It is built from the signal description sections of the Block Guides of the individual IP Blocks contained in the system.
1.2.1
Device Pinout
The MC3S12RG128 and its derivatives are available in a 112-pin low profile quad flat pack (LQFP) and in a 80-pin quad flat pack (QFP). Most pins perform two or more functions, as described in the Signal Descriptions. Figure 1-4 and Figure 1-5 show the pin assignments for different packages. For pins not available in 80 pin QFP please refer to Table 1-4 in section 1.2.2 Signal Properties Summary.
MC3S12RG128 Data Sheet, Rev. 1.05 48 Freescale Semiconductor
Chapter 1 Device Overview (MC3S12RG128V1)
Signals shown in Bold are not available on the 80 pin package
Figure 1-4. Pin assignments in 112 LQFP for MC3S12RG128
Freescale Semiconductor
ADDR5/DATA5/PB5 ADDR6/DATA6/PB6 ADDR7/DATA7/PB7 KWH7/PH7 KWH6/PH6 KWH5/PH5 KWH4/PH4 XCLKS/NOACC/PE7 MODB/IPIPE1/PE6 MODA/IPIPE0/PE5 ECLK/PE4 VSSR VDDR RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST SS1/KWH3/PH3 SCK1/KWH2/PH2 MOSI1/KWH1/PH1 MISO1/KWH0/PH0 LSTRB/TAGLO/PE3 R/W/PE2 IRQ/PE1 XIRQ/PE0
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56
SS1/PWM3/KWP3/PP3 SCK1/PWM2/KWP2/PP2 MOSI1/PWM1/KWP1/PP1 MISO1/PWM0/KWP0/PP0 XADDR17/PK3 XADDR16/PK2 XADDR15/PK1 XADDR14/PK0 IOC0/PT0 IOC1/PT1 IOC2/PT2 IOC3/PT3 VDD1 VSS1 IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 XADDR19/PK5 XADDR18/PK4 KWJ1/PJ1 KWJ0/PJ0 MODC/TAGHI/BKGD ADDR0/DATA0/PB0 ADDR1/DATA1/PB1 ADDR2/DATA2/PB2 ADDR3/DATA3/PB3 ADDR4/DATA4/PB4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85
PP4/KWP4/PWM4 PP5/KWP5/PWM5 PP6/KWP6/PWM6 PP7/KWP7/PWM7 PK7/ECS/ROMCTL VDDX VSSX PM0/RXCAN0 PM1/TXCAN0 PM2/RXCAN0/MISO0 PM3/TXCAN0/SS0 PM4/RXCAN0/RXCAN4/MOSI0 PM5/TXCAN0/TXCAN4/SCK0 PJ6/KWJ6/RXCAN4/SDA/RXCAN0 PJ7/KWJ7/TXCAN4/SCL/TXCAN0 VREGEN PS7/SS0 PS6/SCK0 PS5/MOSI0 PS4/MISO0 PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0 PM6/RXCAN4 PM7/TXCAN4 VSSA VRL
MC3S12RG128 112LQFP
84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57
VRH VDDA PAD15/AN15/ETRIG1 PAD07/AN07/ETRIG0 PAD14/AN14 PAD06/AN06 PAD13/AN13 PAD05/AN05 PAD12/AN12 PAD04/AN04 PAD11/AN11 PAD03/AN03 PAD10/AN10 PAD02/AN02 PAD09/AN09 PAD01/AN01 PAD08/AN08 PAD00/AN00 VSS2 VDD2 PA7/ADDR15/DATA15 PA6/ADDR14/DATA14 PA5/ADDR13/DATA13 PA4/ADDR12/DATA12 PA3/ADDR11/DATA11 PA2/ADDR10/DATA10 PA1/ADDR9/DATA9 PA0/ADDR8/DATA8
MC3S12RG128 Data Sheet, Rev. 1.05 49
Chapter 1 Device Overview (MC3S12RG128V1)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
PP4/KWP4/PWM4 PP5/KWP5/PWM5 PP7/KWP7/PWM7 VDDX VSSX PM0/RXCAN0 PM1/TXCAN0 PM2/RXCAN0/MISO0 PM3/TXCAN0/SS0 PM4/RXCAN0/RXCAN4/MOSI0 PM5/TXCAN0/TXCAN4/SCK0 PJ6/KWJ6/RXCAN4/SDA/RXCAN0 PJ7/KWJ7/TXCAN4/SCL/TXCAN0 VREGEN PS3/TXD1 PS2//RXD1 PS1/TXD0 PS0/RXD0 VSSA VRL SS1/PWM3/KWP3/PP3 SCK1/PWM2/KWP2/PP2 MOSI1/PWM1/KWP1/PP1 MISO1/PWM0/KWP0/PP0 IOC0/PT0 IOC1/PT1 IOC2/PT2 IOC3/PT3 VDD1 VSS1 IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 MODC/TAGHI/BKGD ADDR0/DATA0/PB0 ADDR1/DATA1/PB1 ADDR2/DATA2/PB2 ADDR3/DATA3/PB3 ADDR4/DATA4/PB4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
MC3S12RG128 80 QFP
VRH VDDA PAD07/AN07/ETRIG0 PAD06/AN06 PAD05/AN05 PAD04/AN04 PAD03/AN03 PAD02/AN02 PAD01/AN01 PAD00/AN00 VSS2 VDD2 PA7/ADDR15/DATA15 PA6/ADDR14/DATA14 PA5/ADDR13/DATA13 PA4/ADDR12/DATA12 PA3/ADDR11/DATA11 PA2/ADDR10/DATA10 PA1/ADDR9/DATA9 PA0/ADDR8/DATA8
Figure 1-5. Pin assignments in 80 QFP for MC3S12RG128
1.2.2
Signal Properties Summary
Table 1-4 summarizes the pin functionality. Pin names printed in bold are not available in the 80 QFP package.
50
ADDR5/DATA5/PB5 ADDR6/DATA6/PB6 ADDR7/DATA7/PB7 XCLKS/NOACC/PE7 MODB/IPIPE1/PE6 MODA/IPIPE0/PE5 ECLK/PE4 VSSR VDDR RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST LSTRB/TAGLO/PE3 R/W/PE2 IRQ/PE1 XIRQ/PE0
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor
Chapter 1 Device Overview (MC3S12RG128V1)
Table 1-4. Signal Properties Summary (Sheet 1 of 3)
Pin Pin Pin Pin Pin Power Name Name Name Name Name Supply Function 1 Function 2 Function 3 Function 4 Function 5 EXTAL XTAL RESET TEST VREGEN XFC BKGD PAD[15] -- -- -- -- -- -- TAGHI AN1[7] -- -- -- -- -- -- MODC ETRIG1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VDDPLL VDDPLL VDDR VDDR VDDX VDDPLL VDDR VDDA Internal Pull Resistor Description CTRL NA NA None None NA NA Always Up None Reset State NA NA None None NA NA Up None External Reset Test Input Voltage Regulator Enable Input PLL Loop Filter Background Debug, Tag High, Mode Input Port AD Input, Analog Inputs, External Trigger Input (ATD1) Port AD Input, Analog Inputs (ATD1) Port AD Input, Analog Inputs, External Trigger Input (ATD0) Port AD Input, Analog Inputs (ATD0) Oscillator Pins
PAD[14:8] PAD[7]
AN1[6:0] AN0[7]
-- ETRIG0
-- --
-- --
VDDA VDDA
None None
None None
PAD[6:0] PA[7:0]
AN0[6:0] ADDR[15:8] / DATA[15:8] ADDR[7:0]/ DATA[7:0] NOACC
-- --
-- --
-- --
VDDA VDDR
None PUCR/ PUPAE PUCR/ PUPBE PUCR/ PUPEE
None
Disabled Port A I/O, Multiplexed Address/Data Disabled Port B I/O, Multiplexed Address/Data Mode Port E I/O, Access, Clock depen- Select dant1
PB[7:0] PE7
-- XCLKS
-- --
-- --
VDDR VDDR
PE6 PE5 PE4 PE3 PE2 PE1 PE0
IPIPE1 IPIPE0 ECLK LSTRB R/W IRQ XIRQ
MODB MODA -- TAGLO -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
VDDR VDDR VDDR VDDR VDDR VDDR VDDR
While RESET pin low: Port E I/O, Pipe Status, Down Mode Input Port E I/O, Pipe Status, Mode Input PUCR/ PUPEE PUCR/ PUPEE PUCR/ PUPEE PUCR/ PUPEE PUCR/ PUPEE Up Mode Port E I/O, Bus Clock Output dependant1 Port E I/O, Byte Strobe, Tag Low Port E I/O, R/W in expanded modes Port E Input, Maskable Interrupt Port E Input, Non Maskable Interrupt
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 51
Chapter 1 Device Overview (MC3S12RG128V1)
Table 1-4. Signal Properties Summary (Sheet 2 of 3)
Pin Pin Pin Pin Pin Power Name Name Name Name Name Supply Function 1 Function 2 Function 3 Function 4 Function 5 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 PJ7 PJ6 PJ[1:0] PK7 PK[5:0] PM7 KWH7 KWH6 KWH5 KWH4 KWH3 KWH2 KWH1 KWH0 KWJ7 KWJ6 KWJ[1:0] ECS XADDR[19: 14] TXCAN4 -- -- -- -- SS1 SCK1 MOSI1 MISO1 TXCAN4 RXCAN4 -- ROMCTL -- -- -- -- -- -- -- -- -- -- SCL SDA -- -- -- -- -- -- -- -- -- -- -- -- TXCAN0 RXCAN0 -- -- -- -- VDDR VDDR VDDR VDDR VDDR VDDR VDDR VDDR VDDX VDDX VDDX VDDX VDDX VDDX Internal Pull Resistor Description CTRL PERH/ PPSH PERH/ PPSH PERH/ PPSH PERH/ PPSH PERH/ PPSH PERH/ PPSH PERH/ PPSH PERH/ PPSH PERJ/ PPSJ PERJ/ PPSJ PERJ/ PPSJ PUCR/ PUPKE PUCR/ PUPKE PERM/ PPSM PERM/ PPSM PERM/ PPSM PERM/ PPSM PERM/ PPSM PERM/ PPSM PERM/ PPSM Reset State Disable Port H I/O, Interrupt d Disable Port H I/O, Interrupt d Disable Port H I/O, Interrupt d Disable Port H I/O, Interrupt d Disable Port H I/O, Interrupt, SS of d SPI1 Disable Port H I/O, Interrupt, SCK d of SPI1 Disable Port H I/O, Interrupt, MOSI d of SPI1 Disable Port H I/O, Interrupt, MISO d of SPI1 Up Up Up Up Up Port J I/O, Interrupt, TX of CAN4, SCL of IIC Port J I/O, Interrupt, RX of CAN4, SDA of IIC Port J I/O, Interrupts Port K I/O, Emulation Chip Select, ROM Control Port K I/O, Extended Addresses
Disable Port M I/O, BF slot d mismatch pulse, TX of CAN4 Disable Port M I/O, BF illegal d pulse/message format error pulse, RX of CAN4 Disabled Port M I/O, TX of CAN0, CAN4, SCK of SPI0 Disabled Port M I/O, RX of CAN0, CAN4, MOSI of SPI0 Disabled Port M I/O, CAN0, SS of SPI0 Disabled Port M I/O, CAN0, MISO of SPI0 Disabled Port M I/O, TX of CAN0
PM6
RXCAN4
--
--
--
VDDX
PM5 PM4 PM3 PM2 PM1
TXCAN0 RXCAN0 TXCAN1 RXCAN1 TXCAN0
TXCAN4 RXCAN4 TXCAN0 RXCAN0 --
SCK0 MOSI0 SS0 MISO0 --
-- -- -- -- --
VDDX VDDX VDDX VDDX VDDX
MC3S12RG128 Data Sheet, Rev. 1.05 52 Freescale Semiconductor
Chapter 1 Device Overview (MC3S12RG128V1)
Table 1-4. Signal Properties Summary (Sheet 3 of 3)
Pin Pin Pin Pin Pin Power Name Name Name Name Name Supply Function 1 Function 2 Function 3 Function 4 Function 5 PM0 PP7 PP6 PP5 PP4 PP3 RXCAN0 KWP7 KWP6 KWP5 KWP4 KWP3 -- PWM7 PWM6 PWM5 PWM4 PWM3 -- -- -- -- -- SS1 -- -- -- -- -- -- VDDX VDDX VDDX VDDX VDDX VDDX Internal Pull Resistor Description CTRL PERM/ PPSM PERP/ PPSP PERP/ PPSP PERP/ PPSP PERP/ PPSP PERP/ PPSP PERP/ PPSP PERP/ PPSP PERP/ PPSP PERS/ PPSS PERS/ PPSS PERS/ PPSS PERS/ PPSS PERS/ PPSS PERS/ PPSS PERS/ PPSS PERS/ PPSS PERT/ PPST Reset State Disabled Port M I/O, RX of CAN0 Disabled Port P I/O, Interrupt, Channel 7 of PWM Disable Port P I/O, Interrupt, d Channel 6 of PWM Disabled Port P I/O, Interrupt, Channel 5 of PWM Disabled Port P I/O, Interrupt, Channel 4 of PWM Disabled Port P I/O, Interrupt, Channel 3 of PWM, SS of SPI1 Disabled Port P I/O, Interrupt, Channel 2 of PWM, SCK of SPI1 Disabled Port P I/O, Interrupt, Channel 1 of PWM, MOSI of SPI1 Disabled Port P I/O, Interrupt, Channel 0 of PWM, MISO of SPI1 Up Up Up Up Up Up Up Up Port S I/O, SS of SPI0 Port S I/O, SCK of SPI0 Port S I/O, MOSI of SPI0 Port S I/O, MISO of SPI0 Port S I/O, TXD of SCI1 Port S I/O, RXD of SCI1 Port S I/O, TXD of SCI0 Port S I/O, RXD of SCI0
PP2
KWP2
PWM2
SCK1
--
VDDX
PP1
KWP1
PWM1
MOSI1
--
VDDX
PP0
KWP0
PWM0
MISO1
--
VDDX
PS7 PS6 PS5 PS4 PS3 PS2 PS1 PS0 PT[7:0]
1
SS0 SCK0 MOSI0 MISO0 TXD1 RXD1 TXD0 RXD0 IOC[7:0]
-- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- --
VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX
Disabled Port T I/O, Timer channels
Refer to PEAR register description in HCS12 Multiplexed External Bus Interface (MEBI) Block Guide.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 53
Chapter 1 Device Overview (MC3S12RG128V1)
1.2.3
1.2.3.1
Detailed Signal Descriptions
EXTAL, XTAL -- Oscillator Pins
EXTAL and XTAL are the crystal driver and external clock pins. On reset all the device clocks are derived from the EXTAL input frequency. XTAL is the crystal output.
1.2.3.2
RESET -- External Reset Pin
An active low bidirectional control signal, it acts as an input to initialize the MCU to a known start-up state, and an output when an internal MCU function causes a reset.
1.2.3.3
TEST -- Test Pin
NOTE The TEST pin must be tied to VSS in all applications.
This input only pin is reserved for test.
1.2.3.4
XFC -- PLL Loop Filter Pin
PLL loop filter. Please ask your Freescale representative for the interactive application note to compute PLL loop filter elements. Any current leakage on this pin must be avoided.
XFC R MCU CS VDDPLL VDDPLL
CP
Figure 1-6. PLL Loop Filter Connections
1.2.3.5
BKGD / TAGHI / MODC -- Background Debug, Tag High, and Mode Pin
The BKGD/TAGHI/MODC pin is used as a pseudo-open-drain pin for the background debug communication. In MCU expanded modes of operation when instruction tagging is on, an input low on this pin during the falling edge of E-clock tags the high half of the instruction word being read into the instruction queue. It is used as an MCU operating mode select pin during reset. The state of this pin is latched to the MODC bit at the rising edge of RESET. This pin has a permanently enabled pull-up device.
MC3S12RG128 Data Sheet, Rev. 1.05 54 Freescale Semiconductor
Chapter 1 Device Overview (MC3S12RG128V1)
1.2.3.6
PAD[15] / AN1[7] / ETRIG1 -- Port AD Input Pin [15]
PAD15 is a general purpose input pin and analog input of the analog to digital converter ATD1. It can act as an external trigger input for the ATD1.
1.2.3.7
PAD[14:8] / AN1[6:0] -- Port AD Input Pins [14:8]
PAD14 - PAD8 are general purpose input pins and analog inputs of the analog to digital converter ATD1.
1.2.3.8
PAD[7] / AN0[7] / ETRIG0 -- Port AD Input Pin [7]
PAD7 is a general purpose input pin and analog input of the analog to digital converter ATD0. It can act as an external trigger input for the ATD0.
1.2.3.9
PAD[6:0] / AN0[6:0] -- Port AD Input Pins [6:0]
PAD6 - PAD8 are general purpose input pins and analog inputs of the analog to digital converter ATD0.
1.2.3.10
PA[7:0] / ADDR[15:8] / DATA[15:8] -- Port A I/O Pins
PA7-PA0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are used for the multiplexed external address and data bus.
1.2.3.11
PB[7:0] / ADDR[7:0] / DATA[7:0] -- Port B I/O Pins
PB7-PB0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are used for the multiplexed external address and data bus.
1.2.3.12
PE7 / NOACC / XCLKS -- Port E I/O Pin 7
PE7 is a general purpose input or output pin. During MCU expanded modes of operation, the NOACC signal, when enabled, is used to indicate that the current bus cycle is an unused or "free" cycle. This signal will assert when the CPU is not using the bus. The XCLKS is an input signal which controls whether a crystal in combination with the internal Colpitts (low power) oscillator is used or whether Pierce oscillator/external clock circuitry is used. The state of this pin is latched at the rising edge of RESET. If the input is a logic low the EXTAL pin is configured for an external clock drive. If input is a logic high an oscillator circuit is configured on EXTAL and XTAL. Since this pin is an input with a pull-up device during reset, if the pin is left floating, the default configuration is an oscillator circuit on EXTAL and XTAL.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 55
Chapter 1 Device Overview (MC3S12RG128V1)
EXTAL CDC * MCU XTAL C2 VSSPLL * Due to the nature of a translated ground Colpitts oscillator a DC voltage bias is applied to the crystal Please contact the crystal manufacturer for crystal DC bias conditions and recommended capacitor value CDC. Figure 1-7. Colpitts Oscillator Connections (PE7=1) C1 Crystal or ceramic resonator
EXTAL
C1
MCU RS* RB
Crystal or ceramic resonator C2
XTAL
VSSPLL
* Rs can be zero (shorted) when used with higher frequency crystals. Refer to manufacturer's data. Figure 1-8. Pierce Oscillator Connections (PE7=0)
EXTAL
MCU
CMOS-COMPATIBLE EXTERNAL OSCILLATOR (VDDPLL-Level)
XTAL
not connected
Figure 1-9. External Clock Connections (PE7=0)
1.2.3.13
PE6 / MODB / IPIPE1 -- Port E I/O Pin 6
PE6 is a general purpose input or output pin. It is used as an MCU operating mode select pin during reset. The state of this pin is latched to the MODB bit at the rising edge of RESET. This pin is shared with the
MC3S12RG128 Data Sheet, Rev. 1.05 56 Freescale Semiconductor
Chapter 1 Device Overview (MC3S12RG128V1)
instruction queue tracking signal IPIPE1. This pin is an input with a pull-down device which is only active when RESET is low.
1.2.3.14
PE5 / MODA / IPIPE0 -- Port E I/O Pin 5
PE5 is a general purpose input or output pin. It is used as an MCU operating mode select pin during reset. The state of this pin is latched to the MODA bit at the rising edge of RESET. This pin is shared with the instruction queue tracking signal IPIPE0. This pin is an input with a pull-down device which is only active when RESET is low.
1.2.3.15
PE4 / ECLK -- Port E I/O Pin 4
PE4 is a general purpose input or output pin. It can be configured to drive the internal bus clock ECLK. ECLK can be used as a timing reference.
1.2.3.16
PE3 / LSTRB / TAGLO -- Port E I/O Pin 3
PE3 is a general purpose input or output pin. In MCU expanded modes of operation, LSTRB can be used for the low-byte strobe function to indicate the type of bus access and when instruction tagging is on, TAGLO is used to tag the low half of the instruction word being read into the instruction queue.
1.2.3.17
PE2 / R/W -- Port E I/O Pin 2
PE2 is a general purpose input or output pin. In MCU expanded modes of operations, this pin drives the read/write output signal for the external bus. It indicates the direction of data on the external bus.
1.2.3.18
PE1 / IRQ -- Port E Input Pin 1
PE1 is a general purpose input pin and the maskable interrupt request input that provides a means of applying asynchronous interrupt requests. This will wake up the MCU from STOP or WAIT mode.
1.2.3.19
PE0 / XIRQ -- Port E Input Pin 0
PE0 is a general purpose input pin and the non-maskable interrupt request input that provides a means of applying asynchronous interrupt requests. This will wake up the MCU from STOP or WAIT mode.
1.2.3.20
PH7 / KWH7 -- Port H I/O Pin 7
PH7 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode.
1.2.3.21
PH6 / KWH6 -- Port H I/O Pin 6
PH6 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 57
Chapter 1 Device Overview (MC3S12RG128V1)
1.2.3.22
PH5 / KWH5 -- Port H I/O Pin 5
PH5 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode.
1.2.3.23
PH4 / KWH4 -- Port H I/O Pin 2
PH4 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode.
1.2.3.24
PH3 / KWH3 / SS1 -- Port H I/O Pin 3
PH3 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as slave select pin SS of the Serial Peripheral Interface 1 (SPI1).
1.2.3.25
PH2 / KWH2 / SCK1 -- Port H I/O Pin 2
PH2 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as serial clock pin SCK of the Serial Peripheral Interface 1 (SPI1).
1.2.3.26
PH1 / KWH1 / MOSI1 -- Port H I/O Pin 1
PH1 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as master output (during master mode) or slave input pin (during slave mode) MOSI of the Serial Peripheral Interface 1 (SPI1).
1.2.3.27
PH0 / KWH0 / MISO1 -- Port H I/O Pin 0
PH0 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as master input (during master mode) or slave output (during slave mode) pin MISO of the Serial Peripheral Interface 1 (SPI1).
1.2.3.28
PJ7 / KWJ7 / TXCAN4 / SCL / TXCAN0 -- PORT J I/O Pin 7
PJ7 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as the transmit pin TXCAN for the Freescale Scalable Controller Area Network controller 0 or 4 (CAN0, CAN4) or the serial clock pin SCL of the IIC module.
1.2.3.29
PJ6 / KWJ6 / RXCAN4 / SDA / RXCAN0 -- PORT J I/O Pin 6
PJ6 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as the receive pin RXCAN for the Freescale Scalable Controller Area Network controller 0 or 4 (CAN0, CAN4) or the serial data pin SDA of the IIC module.
MC3S12RG128 Data Sheet, Rev. 1.05 58 Freescale Semiconductor
Chapter 1 Device Overview (MC3S12RG128V1)
1.2.3.30
PJ[1:0] / KWJ[1:0] -- Port J I/O Pins [1:0]
PJ1 and PJ0 are general purpose input or output pins. They can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode.
1.2.3.31
PK7 / ECS / ROMCTL -- Port K I/O Pin 7
PK7 is a general purpose input or output pin. During MCU expanded modes of operation, this pin is used as the emulation chip select output (ECS). While configurating MCU expanded modes, this pin is used to enable the ROM memory in the memory map (ROMCTL). At the rising edge of RESET, the state of this pin is latched to the ROMON bit. For a complete list of modes refer to 1.4 Chip Configuration Summary.
1.2.3.32
PK[5:0] / XADDR[19:14] -- Port K I/O Pins [5:0]
PK5-PK0 are general purpose input or output pins. In MCU expanded modes of operation, these pins provide the expanded address XADDR[19:14] for the external bus.
1.2.3.33
PM7 / TXCAN4 -- Port M I/O Pin 7
PM7 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN of the Freescale Scalable Controller Area Network controllers 4 (CAN4).
1.2.3.34
PM6 / RXCAN4 -- Port M I/O Pin 6
PM6 is a general purpose input or output pin. It can be configured as the receive pin RXCAN of the Freescale Scalable Controller Area Network controllers 4 (CAN4).
1.2.3.35
PM5 / TXCAN0 / TXCAN4 / SCK0 -- Port M I/O Pin 5
PM5 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN of the Freescale Scalable Controller Area Network controllers 0 or 4 (CAN0 or CAN4). It can be configured as the serial clock pin SCK of the Serial Peripheral Interface 0 (SPI0).
1.2.3.36
PM4 / RXCAN0 / RXCAN4/ MOSI0 -- Port M I/O Pin 4
PM4 is a general purpose input or output pin. It can be configured as the receive pin RXCAN of the Freescale Scalable Controller Area Network controllers 0 or 4 (CAN0 or CAN4). It can be configured as the master output (during master mode) or slave input pin (during slave mode) MOSI for the Serial Peripheral Interface 0 (SPI0).
1.2.3.37
PM3 / TXCAN0 / SS0 -- Port M I/O Pin 3
PM3 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN of the Freescale Scalable Controller Area Network controller 0 (CAN0). It can be configured as the slave select pin SS of the Serial Peripheral Interface 0 (SPI0).
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 59
Chapter 1 Device Overview (MC3S12RG128V1)
1.2.3.38
PM2 / RXCAN0 / MISO0 -- Port M I/O Pin 2
PM2 is a general purpose input or output pin. It can be configured as the receive pin RXCAN of the Freescale Scalable Controller Area Network controller 0 (CAN0). It can be configured as the master input (during master mode) or slave output pin (during slave mode) MISO for the Serial Peripheral Interface 0 (SPI0).
1.2.3.39
PM1 / TXCAN0 -- Port M I/O Pin 1
PM1 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN of the Freescale Scalable Controller Area Network controller 0 (CAN0).
1.2.3.40
PM0 / RXCAN0 -- Port M I/O Pin 0
PM0 is a general purpose input or output pin. It can be configured as the receive pin RXCAN of the Freescale Scalable Controller Area Network controller 0 (CAN0).
1.2.3.41
PP7 / KWP7 / PWM7 -- Port P I/O Pin 7
PP7 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 7 output.
1.2.3.42
PP6 / KWP6 / PWM6 -- Port P I/O Pin 6
PP6 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 6 output.
1.2.3.43
PP5 / KWP5 / PWM5 -- Port P I/O Pin 5
PP5 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 5 output.
1.2.3.44
PP4 / KWP4 / PWM4 -- Port P I/O Pin 4
PP4 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 4 output.
1.2.3.45
PP3 / KWP3 / PWM3 / SS1 -- Port P I/O Pin 3
PP3 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 3 output. It can be configured as slave select pin SS of the Serial Peripheral Interface 1 (SPI1).
1.2.3.46
PP2 / KWP2 / PWM2 / SCK1 -- Port P I/O Pin 2
PP2 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 2 output. It can be configured as serial clock pin SCK of the Serial Peripheral Interface 1 (SPI1).
MC3S12RG128 Data Sheet, Rev. 1.05 60 Freescale Semiconductor
Chapter 1 Device Overview (MC3S12RG128V1)
1.2.3.47
PP1 / KWP1 / PWM1 / MOSI1 -- Port P I/O Pin 1
PP1 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 1 output. It can be configured as master output (during master mode) or slave input pin (during slave mode) MOSI of the Serial Peripheral Interface 1 (SPI1).
1.2.3.48
PP0 / KWP0 / PWM0 / MISO1 -- Port P I/O Pin 0
PP0 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 0 output. It can be configured as master input (during master mode) or slave output (during slave mode) pin MISO of the Serial Peripheral Interface 1 (SPI1).
1.2.3.49
PS7 / SS0 -- Port S I/O Pin 7
PS7 is a general purpose input or output pin. It can be configured as the slave select pin SS of the Serial Peripheral Interface 0 (SPI0).
1.2.3.50
PS6 / SCK0 -- Port S I/O Pin 6
PS6 is a general purpose input or output pin. It can be configured as the serial clock pin SCK of the Serial Peripheral Interface 0 (SPI0).
1.2.3.51
PS5 / MOSI0 -- Port S I/O Pin 5
PS5 is a general purpose input or output pin. It can be configured as master output (during master mode) or slave input pin (during slave mode) MOSI of the Serial Peripheral Interface 0 (SPI0).
1.2.3.52
PS4 / MISO0 -- Port S I/O Pin 4
PS4 is a general purpose input or output pin. It can be configured as master input (during master mode) or slave output pin (during slave mode) MOSI of the Serial Peripheral Interface 0 (SPI0).
1.2.3.53
PS3 / TXD1 -- Port S I/O Pin 3
PS3 is a general purpose input or output pin. It can be configured as the transmit pin TXD of Serial Communication Interface 1 (SCI1).
1.2.3.54
PS2 / RXD1 -- Port S I/O Pin 2
PS2 is a general purpose input or output pin. It can be configured as the receive pin RXD of Serial Communication Interface 1 (SCI1).
1.2.3.55
PS1 / TXD0 -- Port S I/O Pin 1
PS1 is a general purpose input or output pin. It can be configured as the transmit pin TXD of Serial Communication Interface 0 (SCI0).
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 61
Chapter 1 Device Overview (MC3S12RG128V1)
1.2.3.56
PS0 / RXD0 -- Port S I/O Pin 0
PS0 is a general purpose input or output pin. It can be configured as the receive pin RXD of Serial Communication Interface 0 (SCI0).
1.2.3.57
PT[7:0] / IOC[7:0] -- Port T I/O Pins [7:0]
PT7-PT0 are general purpose input or output pins. They can be configured as input capture or output compare pins IOC7-IOC0 of the Enhanced Capture Timer (ECT).
1.2.4
Power Supply Pins
Table 1-5. MC3S12RG128 Power and Ground Connection Summary
Pin Number
MC3S12RG128 power and ground pins are described below.
Mnemonic 112-pin QFP VDD1,2 VSS1,2 VDDR VSSR VDDX VSSX VDDA VSSA VRL VRH VDDPLL VSSPLL VREGEN 13, 65 14, 66 41 40 107 106 83 86 85 84 43 45 97
Nominal Voltage 2.5V 0V 5.0V 0V 5.0V 0V 5.0V 0V 0V 5.0V 2.5V 0V 5V
Description Internal power and ground generated by internal regulator External power and ground, supply to pin drivers and internal voltage regulator. External power and ground, supply to pin drivers. Operating voltage and ground for the analog-to-digital converters and the reference for the internal voltage regulator, allows the supply voltage to the A/D to be bypassed independently. Reference voltages for the analog-to-digital converter. Provides operating voltage and ground for the Phased-Locked Loop. This allows the supply voltage to the PLL to be bypassed independently. Internal power and ground generated by internal regulator. Internal Voltage Regulator enable/disable
NOTE All VSS pins must be connected together in the application.
1.2.4.1
VDDX,VSSX -- Power & Ground Pins for I/O Drivers
External power and ground for I/O drivers. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. Bypass requirements depend on how heavily the MCU pins are loaded.
MC3S12RG128 Data Sheet, Rev. 1.05 62 Freescale Semiconductor
Chapter 1 Device Overview (MC3S12RG128V1)
1.2.4.2
VDDR, VSSR -- Power & Ground Pins for I/O Drivers & for Internal Voltage Regulator
External power and ground for I/O drivers and input to the internal voltage regulator. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. Bypass requirements depend on how heavily the MCU pins are loaded.
1.2.4.3
VDD1, VDD2, VSS1, VSS2 -- Internal Logic Power Supply Pins
Power is supplied to the MCU by the internal voltage regulator (if enabled) through VDD1/VDD2 and VSS1/VSS2. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. This 2.5V supply is derived from the internal voltage regulator. There is no static load on those pins allowed. The internal voltage regulator is turned off, if VREGEN is tied to ground. NOTE No load allowed except for bypass capacitors.
1.2.4.4
VDDA, VSSA -- Power Supply Pins for ATD and VREG
VDDA, VSSA are the power supply and ground input pins for the voltage regulator and the analog to digital converter. It also provides the reference for the internal voltage regulator. This allows the supply voltage to the ATD and the reference voltage to be bypassed independently.
1.2.4.5
VRH, VRL -- ATD Reference Voltage Input Pins
VRH and VRL are the reference voltage input pins for the analog to digital converter.
1.2.4.6
VDDPLL, VSSPLL -- Power Supply Pins for PLL
Provides operating voltage and ground for the Oscillator and the Phased-Locked Loop. This allows the supply voltage to the Oscillator and PLL to be bypassed independently.This 2.5V voltage is generated by the internal voltage regulator. NOTE No load allowed except for bypass capacitors and/or XFC filter components (please refer A.6.3.1 XFC Component Selection for details).
1.2.4.7
VREGEN -- On Chip Voltage Regulator Enable
Enables the internal 5V to 2.5V voltage regulator. If this pin is tied low, VDD1,2 and VDDPLL must be supplied externally.
1.3
System Clock Description
The Clock and Reset Generator provides the internal clock signals for the core and all peripheral modules. Figure 1-10 shows the clock connections from the CRG to all modules.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 63
Chapter 1 Device Overview (MC3S12RG128V1)
Consult the CRG Block User Guide for details on clock generation.
HCS12 CORE
BDM MEBI CPU MMC
core clock
INT BKP
ROM RAM ECT ATD0, ATD1 EXTAL PWM SCI0, SCI1 CRG bus clock oscillator clock XTAL IIC PIM SPI0, SPI1 CAN0, CAN4
Figure 1-10. Clock Connections
1.4
Chip Configuration Summary
Eight possible modes determine the operating configuration of the MC3S12RG128. Each mode has an associated default memory map and external bus configuration controlled by a further pin. Three low power modes exist for the device. The operating mode out of reset is determined by the states of the MODC, MODB, and MODA pins during reset (Table 1-6). The MODC, MODB, and MODA bits in the MODE register show the current operating mode and provide limited mode switching during operation. The states of the MODC, MODB, and MODA pins are latched into these bits on the rising edge of the reset signal. The ROMCTL signal allows the setting of the ROMON bit in the MISC register thus controlling whether the internal ROM is visible in the memory map. ROMON = 1 mean the ROM is visible in the memory map. The state of the ROMCTL pin is latched into the ROMON bit in the MISC register on the rising edge of the reset signal.
MC3S12RG128 Data Sheet, Rev. 1.05 64 Freescale Semiconductor
Chapter 1 Device Overview (MC3S12RG128V1)
Table 1-6. Mode Selection
BKGD = MODC 0 PE6 = MODB 0 PE5 = MODA 0 PK7 = ROMCTL1 X ROMON Bit 1 Mode Description Special Single Chip, BDM allowed and ACTIVE. BDM is allowed in all other modes but a serial command is required to make BDM active. Emulation Expanded Narrow, BDM allowed Special Test (Expanded Wide), BDM allowed Emulation Expanded Wide, BDM allowed Normal Single Chip, BDM allowed Normal Expanded Narrow, BDM allowed Special Peripheral; BDM allowed but bus operations would cause bus conflicts (must not be used) Normal Expanded Wide, BDM allowed
0 0 0 1 1 1 1
1
0 1 1 0 0 1 1
1 0 1 0 1 0 1
0 1 X 0 1 X 0 1 X 0 1
1 0 0 1 0 1 0 1 1 0 1
This pin is not available in the 80 pin package. It is pulled to `1' by an internal pull-up resistor.
For further explanation on the modes refer to the HCS12 Multiplexed External Bus Interface Block Guide.
Table 1-7. Clock Selection Based on PE7 PE7 = XCLKS
1 0
Description
Colpitts Oscillator selected Pierce Oscillator/external clock selected
Table 1-8. Voltage Regulator VREGEN VREGEN
1 0
Description
Internal Voltage Regulator enabled Internal Voltage Regulator disabled, VDD1,2 and VDDPLL must be supplied externally with 2.5V
1.4.1
Security
The device will make available a security feature preventing the unauthorized read and write of the memory contents. This feature allows: * Protection of the contents of ROM, * Operation in single-chip mode, No BDM possible The user must be reminded that part of the security must lie with the user's code. An extreme example would be user's code that dumps the contents of the internal program. This code would defeat the purpose of security. At the same time the user may also wish to put a back door in the user's program.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 65
Chapter 1 Device Overview (MC3S12RG128V1)
1.4.1.1
Securing the Microcontroller
The status of security of the part is determined by the security bits located in the ROM module. These non-volatile bits will keep the part secured through resetting the part and through powering down the part. The security byte resides in a portion of the ROM array. Check the ROM Block User Guide for more details on the security configuration.
1.4.1.2
1.4.1.2.1
Operation of the Secured Microcontroller
Normal Single Chip Mode
This will be the most common usage of the secured part. Everything will appear the same as if the part was not secured with the exception of BDM operation. The BDM operation will be blocked. 1.4.1.2.2 Executing from External Memory
Disabling the internal ROM will unsecure the microcontroller and will also unblock the BDM. As a consequence, executing from external space with a secured microcontroller is not possible. Please note that in the 80 pin package the ROMCTL pin is not accessable externally but is pulled to `1' internally by a pull-up resistor.
1.4.1.3
Unsecuring the Microcontroller
In order to unsecure the microcontroller, the internal ROM must be disabled. This can be done by selecting expanded mode or by starting in special single chip mode. Unsecuring is also possible via the Backdoor Key Access. Refer to ROM Block Guide for details. If a secure part is reset to special single chip mode, BDM firmware will disable the ROM by clearing the ROMON bit (Bit0 in the MISC register). The BDM software commands are unblocked and the part can be used in unsecure mode. In this state (secured ROM disabled, part unsecured) setting the ROMON bit again has no effect on the memory map, i.e. ROM remains disabled until next reset.
1.5
1.5.1
1.5.1.1
Modes of Operation
User Modes
Normal Expanded Wide Mode
Ports A, B and K are configured as a 23-bit address bus during the address phase, port A and B are configured as 16-bit data bus during the data-phase, and port E provides bus control and status signals. This mode allows 16-bit external memory and peripheral devices to be interfaced to the system.
MC3S12RG128 Data Sheet, Rev. 1.05 66 Freescale Semiconductor
Chapter 1 Device Overview (MC3S12RG128V1)
1.5.1.2
Normal Expanded Narrow Mode
Ports A, B and K are configured as a 23-bit address bus during the address phase, port B is configured as a 8-bit data bus during the data phase, and port E provides bus control and status signals. This mode allows 8-bit external memory and peripheral devices to be interfaced to the system.
1.5.1.3
Normal Single-Chip Mode
There is no external bus in this mode. The processor program is executed from internal memory. Ports A, B, K, and most pins of port E are available as general-purpose I/O.
1.5.1.4
Special Single-Chip Mode
This mode is used for debugging single-chip operation, boot-strapping, or security related operations. The background debug module BDM is active in this mode. The CPU executes a monitor program located in an on-chip ROM. BDM firmware is waiting for additional serial commands through the BKGD pin. There is no external bus after reset in this mode.
1.5.1.5
Emulation of Expanded Wide Mode
Developers use this mode for emulation systems in which the users target application is normal expanded wide mode. Code is executed from external memory or from internal memory depending on the state of ROMON bit. In this mode the internal operation is visible on external bus interface.
1.5.1.6
Emulation of Expanded Narrow Mode
Developers use this mode for emulation systems in which the users target application is normal expanded narrow mode. Code is executed from external memory or from internal memory depending on the state of ROMON bit. In this mode the internal operation is visible on external bus interface.
1.5.1.7
Special Test Mode
Freescale internal use only.
1.5.1.8
Special Peripheral Mode
Freescale internal use only.
1.5.2
Low Power Modes
The microcontroller features three main low power modes. Consult the respective Block User Guide for information on the module behavior in Stop, Pseudo Stop, and Wait Mode. An important source of information about the clock system is the Clock and Reset Generator User Guide (CRG).
1.5.2.1
Stop
Executing the CPU STOP instruction stops all clocks and the oscillator thus putting the chip in fully static mode. Wake up from this mode can be done via reset or external interrupts.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 67
Chapter 1 Device Overview (MC3S12RG128V1)
1.5.2.2
Pseudo Stop
This mode is entered by executing the CPU STOP instruction. In this mode the oscillator is still running and the Real Time Interrupt (RTI) or Watchdog (COP) sub module can stay active. Other peripherals are turned off. This mode consumes more current than the full STOP mode, but the wake up time from this mode is significantly shorter.
1.5.2.3
Wait
This mode is entered by executing the CPU WAI instruction. In this mode the CPU will not execute instructions. The internal CPU signals (address and databus) will be fully static. All peripherals stay active. To further reduce the power consumption the peripherals can turn off their local clocks individually.
1.5.2.4
Run
Although this is not a low power mode, unused peripheral modules should not be enabled in order to save power.
1.6
Resets and Interrupts
Consult the Exception Processing section of the S12 CPU Reference Manual for information on resets and interrupts.
1.6.1
Vectors
Table 1-9. Interrupt Vector Locations
Table 1-9 lists interrupt sources and vectors in default order of priority.
CCR Mask None None None None None X-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit HPRIO Value to Elevate - - - - - - 0xF2 0xF0 0xEE 0xEC 0xEA 0xE8 0xE6 0xE4 0xE2 0xE0 0xDE
Vector Address 0xFFFE, 0xFFFF 0xFFFC, 0xFFFD 0xFFFA, 0xFFFB 0xFFF8, 0xFFF9 0xFFF6, 0xFFF7 0xFFF4, 0xFFF5 0xFFF2, 0xFFF3 0xFFF0, 0xFFF1 0xFFEE, 0xFFEF 0xFFEC, 0xFFED 0xFFEA, 0xFFEB 0xFFE8, 0xFFE9 0xFFE6, 0xFFE7 0xFFE4, 0xFFE5 0xFFE2, 0xFFE3 0xFFE0, 0xFFE1 0xFFDE, 0xFFDF
Interrupt Source Reset Clock Monitor fail reset COP failure reset Unimplemented instruction trap SWI XIRQ IRQ Real Time Interrupt Enhanced Capture Timer channel 0 Enhanced Capture Timer channel 1 Enhanced Capture Timer channel 2 Enhanced Capture Timer channel 3 Enhanced Capture Timer channel 4 Enhanced Capture Timer channel 5 Enhanced Capture Timer channel 6 Enhanced Capture Timer channel 7 Enhanced Capture Timer overflow
Local Enable None COPCTL (CME, FCME) COP rate select None None None INTCR (IRQEN) CRGINT (RTIE) TIE (C0I) TIE (C1I) TIE (C2I) TIE (C3I) TIE (C4I) TIE (C5I) TIE (C6I) TIE (C7I) TSCR2 (TOF)
MC3S12RG128 Data Sheet, Rev. 1.05 68 Freescale Semiconductor
Chapter 1 Device Overview (MC3S12RG128V1)
0xFFDC, 0xFFDD 0xFFDA, 0xFFDB 0xFFD8, 0xFFD9 0xFFD6, 0xFFD7 0xFFD4, 0xFFD5 0xFFD2, 0xFFD3 0xFFD0, 0xFFD1 0xFFCE, 0xFFCF 0xFFCC, 0xFFCD 0xFFCA, 0xFFCB 0xFFC8, 0xFFC9 0xFFC6, 0xFFC7 0xFFC4, 0xFFC5 0xFFC2, 0xFFC3 0xFFC0, 0xFFC1 0xFFBE, 0xFFBF 0xFFBC, 0xFFBD 0xFFBA, 0xFFBB 0xFFB8, 0xFFB9 0xFFB6, 0xFFB7 0xFFB4, 0xFFB5 0xFFB2, 0xFFB3 0xFFB0, 0xFFB1 0xFFAE, 0xFFAF 0xFFAC, 0xFFAD 0xFFAA, 0xFFAB 0xFFA8, 0xFFA9 0xFFA6, 0xFFA7 0xFFA4, 0xFFA5 0xFFA2, 0xFFA3 0xFFA0, 0xFFA1 0xFF98, 0xFF9F 0xFF96, 0xFF97 0xFF94, 0xFF95 0xFF92, 0xFF93 0xFF90, 0xFF91 0xFF8E, 0xFF8F 0xFF8C, 0xFF8D 0xFF8A, 0xFF8B 0xFF80 to 0xFF89
Pulse accumulator A overflow Pulse accumulator input edge SPI0 SCI0 SCI1 ATD0 ATD1 Port J Port H Modulus Down Counter underflow Pulse Accumulator B Overflow CRG PLL lock CRG Self Clock Mode IIC Bus SPI1
I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit Reserved I-Bit I-Bit Reserved Reserved Reserved
PACTL (PAOVI) PACTL (PAI) SPICR1 (SPIE, SPTIE) SCICR2 (TIE, TCIE, RIE, ILIE) SCICR2 (TIE, TCIE, RIE, ILIE) ATDCTL2 (ASCIE) ATDCTL2 (ASCIE) PIEJ (PIEJ7, PIEJ6, PIEJ1, PIEJ0) PIEH (PIEH7-0) MCCTL (MCZI) PBCTL (PBOVI) PLLCR (LOCKIE) PLLCR (SCMIE) IBCR (IBIE) SPICR1 (SPIE, SPTIE)
0xDC 0xDA 0xD8 0xD6 0xD4 0xD2 0xD0 0xCE 0xCC 0xCA 0xC8 0xC6 0xC4 0xC0 0xBE
CAN0 wake-up CAN0 errors CAN0 receive CAN0 transmit
I-Bit I-Bit I-Bit I-Bit Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
CANRIER (WUPIE) CANRIER (CSCIE, OVRIE) CANRIER (RXFIE) CANTIER (TXEIE[2:0])
0xB6 0xB4 0xB2 0xB0
CAN4 wake-up CAN4 errors CAN4 receive CAN4 transmit Port P Interrupt PWM Emergency Shutdown VREG Low Voltage Interrupt
I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit Reserved
CANRIER (WUPIE) CANRIER (CSCIE, OVRIE) CANRIER (RXFIE) CANTIER (TXEIE[2:0]) PIEP (PIEP7-0) PWMSDN (PWMIE) VREGCTRL (LVIE)
0x96 0x94 0x92 0x90 0x8E 0x8C 0x8A
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 69
Chapter 1 Device Overview (MC3S12RG128V1)
1.6.2
Effects of Reset
When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to the respective module Block User Guides for register reset states.
1.6.2.1
I/O pins
Refer to the HCS12 Multiplexed External Bus Interface (MEBI) Block Guide for mode dependent pin configuration of port A, B, E and K out of reset. Refer to the PIM Block User Guide for reset configurations of all peripheral module ports. NOTE For devices assembled in 80-pin QFP packages all non-bonded out pins should be configured as outputs after reset in order to avoid current drawn from floating inputs. Refer to Table 1-4 for affected pins.
1.6.2.2
Memory
Refer to Figure 1-2 for locations of the memories depending on the operating mode after reset. The content of the RAM array is not automatically initialized out of reset.
MC3S12RG128 Data Sheet, Rev. 1.05 70 Freescale Semiconductor
Chapter 2 Port Integration Module (PIM3RG128V1) Block Description
2.1 Introduction
The Port Integration Module establishes the interface between the peripheral modules and the I/O pins for all ports. NOTE Port A, B, E, and K are related to the core logic and multiplexed bus interface. Refer to the HCS12 Core User Guide for details. This section covers: * Port T connected to the timer module * The serial port S associated with 2 SCI and 1 SPI modules * Port M associated with 2 CAN and 1 SPI modules * Port P connected to the PWM and 1 SPI modules, which also can be used as an external interrupt source * The standard I/O ports H and J associated with the first and fifth CAN module and the IIC interface. These ports can also be used as external interrupt sources. Each I/O pin can be configured by several registers in order to select data direction and drive strength, to enable and select pull-up or pull-down resistors. On certain pins also interrupts can be enabled which result in status flags. The I/O's of two CAN and all two SPI modules can be routed from their default location to determined pins. The implementation of the Port Integration Module is device dependent.
2.1.1
Features
A standard port pin has the following minimum features: * Input/output selection * 5-V output drive with two selectable drive strengths * 5-V digital and analog input * Input with selectable pull-up or pull-down device
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 71
Chapter 2 Port Integration Module (PIM3RG128V1) Block Description
Optional features: * Open drain for wired-OR connections * Interrupt inputs with glitch filtering
2.1.2
Block Diagram
Figure 2-1 is a block diagram of the PIM3RG128.
PORT INTEGRATION MODULE PH0 PH1 PH2 PH3 PH4 PH5 PH6 PH7 PJ0 PJ1 PORT J SPI1 rout.
IOC0 IOC1 IOC2 IOC3 IOC4 IOC5 IOC6 IOC7 SPI1 rout. INTERRUPT LOGIC
PT0 PT1 PT2 PT3 PT4 PT5 PT6 PT7 PP0 PP1 PP2 PP3 PP4 PP5 PP6 PP7 PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7
Interrupt Logic
PORT H
CAN0 rout.
PJ6 PJ7
SDA IIC SCL RXCAN TXCAN CAN4
PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7
PM0 PM1 PM2 PM3 PM4 PM5 PM6 PM7
CAN4 rout. SPI0 rout. CAN0 routing
PORT M
PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7
ADDR0/DATA0 ADDR1/DATA1 ADDR2/DATA2 ADDR3/DATA3 ADDR4/DATA4 ADDR5/DATA5 ADDR6/DATA6 ADDR7/DATA7 ADDR8/DATA8 ADDR9/DATA9 ADDR10/DATA10 ADDR11/DATA11 ADDR12/DATA12 ADDR13/DATA13 ADDR14/DATA14 ADDR15/DATA15
BKGD/MODC/TAGHI XIRQ IRQ R/W LSTRB/TAGLO ECLK IPIPE0/MODA IPIPE1/MODB NOACC/XCLKS CORE XADDR14 XADDR15 XADDR16 XADDR17 XADRR18 XADDR19 ECS/ROMONE
SPI0 rout.
PORT S
RXCAN TXCAN CAN0
RXD SCI0 TXD RXD SCI1 TXD MISO MOSI SCK SPI0 SS
PORT P
PWM
MISO MOSI SCK SPI1 SS
PORT T
TIMER
PORT B
PORT E
Interrupt Logic
BKGD PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 PK0 PK1 PK2 PK3 PK4 PK5 PK7
PORT A
Figure 2-1. PIM3RG128 Block Diagram
MC3S12RG128 Data Sheet, Rev. 1.05 72 Freescale Semiconductor
PORT K
Chapter 2 Port Integration Module (PIM3RG128V1) Block Description
2.2
External Signal Description
This section lists and describes the signals that do connect off-chip.
2.2.1
Signal Properties
Table 2-1shows all the pins and their functions that are controlled by the PIM3RG128. If there is more than one function associated with a pin, the priority is indicated by the position in the table from top (highest priority) to down (lowest priority).
Table 2-1. Pin Functions and Priorities (Sheet 1 of 4)
Port Port T Pin Name PT[7:0] Pin Function and Priority IOC[7:0] GPIO Port S PS7 SS0 GPIO PS6 SCK0 GPIO PS5 MOSI0 GPIO PS4 MISO0 GPIO PS3 TXD1 GPIO PS2 RXD1 GPIO PS1 TXD0 GPIO PS0 RXD0 GPIO Description Enhanced Capture Timer Channels 7 to 0 General-purpose I/O Serial Peripheral Interface 0 slave select output in master mode, input in slave mode or master mode. General-purpose I/O Serial Peripheral Interface 0 serial clock pin General-purpose I/O Serial Peripheral Interface 0 master out/slave in pin General-purpose I/O Serial Peripheral Interface 0 master in/slave out pin General-purpose I/O Serial Communication Interface 1 transmit pin General-purpose I/O Serial Communication Interface 1 receive pin General-purpose I/O Serial Communication Interface 0 transmit pin General-purpose I/O Serial Communication Interface 0 receive pin General-purpose I/O GPIO Pin Function after Reset GPIO
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 73
Chapter 2 Port Integration Module (PIM3RG128V1) Block Description
Table 2-1. Pin Functions and Priorities (Sheet 2 of 4)
Port Port M Pin Name PM7 Pin Function and Priority TXCAN4 GPIO PM6 RXCAN4 GPIO PM5 TXCAN0 TXCAN4 SCK0 GPIO PM4 RXCAN0 RXCAN4 MOSI0 GPIO PM3 TXCAN0 SS01 GPIO PM2 RXCAN0 MSCAN4 transmit pin General-purpose I/O MSCAN4 receive pin General-purpose I/O MSCAN0 transmit pin MSCAN4 transmit pin Serial Peripheral Interface 0 serial clock pin General-purpose I/O MSCAN0 receive pin MSCAN4 receive pin Serial Peripheral Interface 0 master out/slave in pin General-purpose I/O MSCAN0 transmit pin Serial Peripheral Interface 0 slave select output in master mode, input for slave mode or master mode. General-purpose I/O MSCAN0 receive pin Description Pin Function after Reset GPIO
MISO0

GPIO PM1 TXCAN0 GPIO PM0 RXCAN0 GPIO General-purpose I/O MSCAN0 transmit pin General-purpose I/O MSCAN0 receive pin General-purpose I/O
MC3S12RG128 Data Sheet, Rev. 1.05 74 Freescale Semiconductor
Chapter 2 Port Integration Module (PIM3RG128V1) Block Description
Table 2-1. Pin Functions and Priorities (Sheet 3 of 4)
Port Port P Pin Name PP7 Pin Function and Priority PWM7 GPIO/KWP7 PP6 PWM6 GPIO/KWP6 PP5 PWM5 GPIO/KWP5 PP4 PWM4 GPIO/KWP4 PP3 PWM3 SS1 GPIO/KWP3 PP2 PWM2 SCK1 GPIO/KWP2 PP1 PWM1 MOSI1 GPIO/KWP1 PP0 PWM0 MISO1 GPIO/KWP0 Port H PH7 PH6 PH5 PH4 PH3 GPIO/KWH7 GPIO/KWH6 GPIO/KWH5 GPIO/KWH4 SS1 GPIO/KWH3 PH2 SCK1 GPIO/KWH2 PH1 MOSI1 GPIO/KWH1 PH0 MISO1 GPIO/KWH0 Description Pulse Width Modulator channel 7 General-purpose I/O with interrupt Pulse Width Modulator channel 6 General-purpose I/O with interrupt Pulse Width Modulator channel 5 General-purpose I/O with interrupt Pulse Width Modulator channel 4 General-purpose I/O with interrupt Pulse Width Modulator channel 3 Serial Peripheral Interface 1 slave select output in master mode, input for slave mode or master mode. General-purpose I/O with interrupt Pulse Width Modulator channel 2 Serial Peripheral Interface 1 serial clock pin General-purpose I/O with interrupt Pulse Width Modulator channel 1 Serial Peripheral Interface 1 master out/slave in pin General-purpose I/O with interrupt Pulse Width Modulator channel 0 Serial Peripheral Interface 1 master in/slave out pin General-purpose I/O with interrupt General-purpose I/O with interrupt General-purpose I/O with interrupt General-purpose I/O with interrupt General-purpose I/O with interrupt Serial Peripheral Interface 1 slave select output in master mode, input for slave mode or master mode. General-purpose I/O with interrupt Serial Peripheral Interface 1 serial clock pin General-purpose I/O with interrupt Serial Peripheral Interface 1 master out/slave in pin General-purpose I/O with interrupt Serial Peripheral Interface 1 master in/slave out pin General-purpose I/O with interrupt GPIO Pin Function after Reset GPIO
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 75
Chapter 2 Port Integration Module (PIM3RG128V1) Block Description
Table 2-1. Pin Functions and Priorities (Sheet 4 of 4)
Port Port J Pin Name PJ7 Pin Function and Priority TXCAN4 SCL TXCAN0 GPIO/KWJ7 PJ6 RXCAN4 SDA RXCAN0 GPIO/KWJ6 PJ[1:0]
1
Description MSCAN4 transmit pin Inter Integrated Circuit serial clock line MSCAN0 transmit pin General-purpose I/O with interrupt MSCAN4 receive pin Inter Integrated Circuit serial data line MSCAN0 receive pin General-purpose I/O with interrupt General-purpose I/O with interrupt
Pin Function after Reset GPIO
GPIO/KWJ[1:0]
If CAN0 is routed to PM[3:2] the SPI0 can still be used in bidirectional master mode. Refer to SPI Block Guide for details.
2.3
Memory Map and Registers
This section provides a detailed description of all registers.
2.3.1
Address 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008
Module Memory Map
Name PTT PTIT DDRT RDRT PERT PPST Reserved Reserved PTS R W R W R W R W R W R W R W R W R W Bit 7 PTT7 PTIT7 6 PTT6 PTIT6 5 PTT5 PTIT5 4 PTT4 PTIT4 3 PTT3 PTIT3 2 PTT2 PTIT2 1 PTT1 PTIT1 Bit 0 PTT0 PTIT0
Figure 2-2 shows the register map of the Port Integration Module.
DDRT7 RDRT7 PERT7 PPST7
DDRT6 RDRT6 PERT6 PPST6
DDRT5 RDRT5 PERT5 PPST5
DDRT4 RDRT4 PERT4 PPST4
DDRT3 RDRT3 PERT3 PPST3
DDRT2 RDRT2 PERT2 PPST2
DDRT1 RDRT1 PERT1 PPST1
DDRT0 RDRT0 PERT0 PPST0
PTS7
PTS6
PTS5
PTS4
PTS3
PTS2
PTS1
PTS0
= Unimplemented or Reserved
Figure 2-2. PIM Register Summary (Sheet 1 of 3)
MC3S12RG128 Data Sheet, Rev. 1.05 76 Freescale Semiconductor
Chapter 2 Port Integration Module (PIM3RG128V1) Block Description
Address 0x0009 0x000A 0x000B 0x000C 0x000D 0x000E 0x000F 0x0010 0x0011 0x0012 0x0013 0x0014 0x0015 0x0016 0x0017 0x0018 0x0019 0x001A 0x001B 0x001C 0x001D 0x001E
Name PTIS DDRS RDRS PERS PPSS WOMS Reserved PTM PTIM DDRM RDRM PERM PPSM WOMM MODRR PTP PTIP DDRP RDRP PERP PPSP PIEP R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W
Bit 7 PTIS7
6 PTIS6
5 PTIS5
4 PTIS4
3 PTIS3
2 PTIS2
1 PTIS1
Bit 0 PTIS0
DDRS7 RDRS7 PERS7 PPSS7 WOMS7
DDRS6 RDRS6 PERS6 PPSS6 WOMS6
DDRS5 RDRS5 PERS5 PPSS5 WOMS5
DDRS4 RDRS4 PERS4 PPSS4 WOMS4
DDRS3 RDRS3 PERS3 PPSS3 WOMS3
DDRS2 RDRS2 PERS2 PPSS2 WOMS2
DDRS1 RDRS1 PERS1 PPSS1 WOMS1
DDRS0 RDRS0 PERS0 PPSS0 WOMS0
PTM7 PTIM7
PTM6 PTIM6
PTM5 PTIM5
PTM4 PTIM4
PTM3 PTIM3
PTM2 PTIM2
PTM1 PTIM1
PTM0 PTIM0
DDRM7 RDRM7 PERM7 PPSM7 WOMM7 0
DDRM6 RDRM6 PERM6 PPSM6 WOMM6 0
DDRM5 RDRM5 PERM5 PPSM5 WOMM5
DDRM4 RDRM4 PERM4 PPSM4 WOMM4
DDRM3 RDRM3 PERM3 PPSM3 WOMM3
DDRM2 RDRM2 PERM2 PPSM2 WOMM2
DDRM1 RDRM1 PERM1 PPSM1 WOMM1 MODRR1 PTP1 PTIP1
DDRM0 RDRM0 PERM0 PPSM0 WOMM0 MODRR0 PTP0 PTIP0
MODRR5 MODRR4 MODRR3 MODRR2 PTP5 PTIP5 PTP4 PTIP4 PTP3 PTIP3 PTP2 PTIP2
PTP7 PTIP7
PTP6 PTIP6
DDRP7 RDRP7 PERP7 PPSP7 PIEP7
DDRP6 RDRP6 PERP6 PPSP6 PIEP6
DDRP5 RDRP5 PERP5 PPSP5 PIEP5
DDRP4 RDRP4 PERP4 PPSP4 PIEP4
DDRP3 RDRP3 PERP3 PPSP3 PIEP3
DDRP2 RDRP2 PERP2 PPSP2 PIEP2
DDRP1 RDRP1 PERP1 PPSP1 PIEP1
DDRP0 RDRP0 PERP0 PPSP0 PIEP0
= Unimplemented or Reserved
Figure 2-2. PIM Register Summary (Sheet 2 of 3)
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 77
Chapter 2 Port Integration Module (PIM3RG128V1) Block Description
Address 0x001F 0x0020 0x0021 0x0022 0x0023 0x0024 0x0025 0x0026 0x0027 0x0028 0x0029 0x002A 0x002B 0x002C 0x002D 0x002E 0x002F 0x0030- 0x003F
Name PIFP PTH PTIH DDRH RDRH PERH PPSH PIEH PIFH PTJ PTIJ DDRJ RDRJ PERJ PPSJ PIEJ PIFJ Reserved R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W
Bit 7 PIFP7 PTH7 PTIH7
6 PIFP6 PTH6 PTIH6
5 PIFP5 PTH5 PTIH5
4 PIFP4 PTH4 PTIH4
3 PIFP3 PTH3 PTIH3
2 PIFP2 PTH2 PTIH2
1 PIFP1 PTH1 PTIH1
Bit 0 PIFP0 PTH0 PTIH0
DDRH7 RDRH7 PERH7 PPSH7 PIEH7 PIFH7 PTJ7 PTIJ7
DDRH6 RDRH6 PERH6 PPSH6 PIEH6 PIFH6 PTJ6 PTIJ6
DDRH5 RDRH5 PERH5 PPSH5 PIEH5 PIFH5 0 0 0 0 0 0 0 0
DDRH4 RDRH4 PERH4 PPSH4 PIEH4 PIFH4 0 0 0 0 0 0 0 0
DDRH3 RDRH3 PERH3 PPSH3 PIEH3 PIFH3 0 0 0 0 0 0 0 0
DDRH2 RDRH2 PERH2 PPSH2 PIEH2 PIFH2 0 0 0 0 0 0 0 0
DDRH1 RDRH1 PERH1 PPSH1 PIEH1 PIFH1 PTJ1 PTIJ1
DDRH0 RDRH0 PERH0 PPSH0 PIEH0 PIFH0 PTJ0 PTIJ0
DDRJ7 RDRJ7 PERJ7 PPSJ7 PIEJ7 PIFJ7
DDRJ6 RDRJ6 PERJ6 PPSJ6 PIEJ6 PIFJ6
DDRJ1 RDRJ1 PERJ1 PPSJ1 PIEJ1 PIFJ1
DDRJ0 RDRJ0 PERJ0 PPSJ0 PIEJ0 PIFJ0
= Unimplemented or Reserved
Figure 2-2. PIM Register Summary (Sheet 3 of 3)
NOTE Register Address = Base Address + Address Offset, where the Base Address is defined at the MCU level and the Address Offset is defined at the module level.
MC3S12RG128 Data Sheet, Rev. 1.05 78 Freescale Semiconductor
Chapter 2 Port Integration Module (PIM3RG128V1) Block Description
2.3.2
Register Descriptions
Table 2-2 summarizes the effect on the various configuration bits, data direction (DDR), output level (I/O), reduced drive (RDR), pull enable (PE), pull select (PS) and interrupt enable (IE) for the ports. The configuration bit PS is used for two purposes: 1. Configure the sensitive interrupt edge (rising or falling), if interrupt is enabled. 2. Select either a pull-up or pull-down device if PE is active.
Table 2-2. Pin Configuration Summary
DDR 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
1
IO X X X X X X X 0 1 0 1 0 1 0 1
RDR X X X X X X X 0 0 1 1 0 0 1 1
PE 0 1 1 0 0 1 1 X X X X X X X X
PS X 0 1 0 1 0 1 X X X X 0 1 0 1
IE1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
Function Input Input Input Input Input Input Input Output, full drive to 0 Output, full drive to 1 Output, reduced drive to 0 Output, reduced drive to 1 Output, full drive to 0 Output, full drive to 1 Output, reduced drive to 0 Output, reduced drive to 1
Pull Device Disabled Pull Up Pull Down Disabled Disabled Pull Up Pull Down Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled
Interrupt Disabled Disabled Disabled Falling edge Rising edge Falling edge Rising edge Disabled Disabled Disabled Disabled Falling edge Rising edge Falling edge Rising edge
Applicable only on port P, H and J.
NOTE All bits of all registers in this module are completely synchronous to internal clocks during a register read.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 79
Chapter 2 Port Integration Module (PIM3RG128V1) Block Description
2.3.2.1
2.3.2.1.1
Port T Registers
Port T I/O Register (PTT)
Module Base + 0x_0000
7 6 5 4 3 2 1 0
R PTT7 W ECT: Reset IOC7 0 IOC6 0 IOC5 0 IOC4 0 IOC3 0 IOC2 0 IOC1 0 IOC0 0 PTT6 PTT5 PTT4 PTT3 PTT2 PTT1 PTT0
Figure 2-3. Port T I/O Register (PTT)
Read: Anytime. Write: Anytime. If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port register, otherwise the value at the pins is read. 2.3.2.1.2 Port T Input Register (PTIT)
Module Base + 0x_0001
7 6 5 4 3 2 1 0
R W Reset
PTIT7
PTIT6
PTIT5
PTIT4
PTIT3
PTIT2
PTIT1
PTIT0
--
--
--
--
--
--
--
--
= Unimplemented or Reserved
Figure 2-4. Port T Input Register (PTIT)
Read: Anytime. Write: Never, writes to this register have no effect. This register always reads back the status of the associated pins. This can also be used to detect overload or short circuit conditions on output pins.
MC3S12RG128 Data Sheet, Rev. 1.05 80 Freescale Semiconductor
Chapter 2 Port Integration Module (PIM3RG128V1) Block Description
2.3.2.1.3
Port T Data Direction Register (DDRT)
Module Base + 0x_0002
7 6 5 4 3 2 1 0
R DDRT7 W Reset 0 0 0 0 0 0 0 0 DDRT6 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0
Figure 2-5. Port T Data Direction Register (DDRT)
Read: Anytime. Write: Anytime. This register configures each port T pin as either input or output. * The ECT forces the I/O state to be an output for each timer port associated with an enabled output compare. In these cases the data direction bits will not change. * The DDRT bits revert to controlling the I/O direction of a pin when the associated timer output compare is disabled. * The timer input capture always monitors the state of the pin.
Table 2-3. DDRT Field Descriptions
Field 7-0 DDRT[7:0] Description Data Direction Port T Bits 0 Associated pin is configured as input. 1 Associated pin is configured as output. Note: Due to internal synchronization circuits, it can take up to two bus cycles until the correct value is read on PTT or PTIT registers, when changing the DDRT register.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 81
Chapter 2 Port Integration Module (PIM3RG128V1) Block Description
2.3.2.1.4
Port T Reduced Drive Register (RDRT)
Module Base + 0x_0003
7 6 5 4 3 2 1 0
R RDRT7 W Reset 0 0 0 0 0 0 0 0 RDRT6 RDRT5 RDRT4 RDRT3 RDRT2 RDRT1 RDRT0
Figure 2-6. Port T Reduced Drive Register (RDRT)
Read: Anytime. Write: Anytime. This register configures the drive strength of each port T output pin as either full or reduced. If the port is used as input this bit is ignored.
Table 2-4. RDRT Field Descriptions
Field 7-0 RDRT[7:0] Description Reduced Drive Port T Bits 0 Full drive strength at output. 1 Associated pin drives at about 1/3 of the full drive strength.
2.3.2.1.5
Port T Pull Device Enable Register (PERT)
Module Base + 0x_0004
7 6 5 4 3 2 1 0
R PERT7 W Reset 0 0 0 0 0 0 0 0 PERT6 PERT5 PERT4 PERT3 PERT2 PERT1 PERT0
Figure 2-7. Port T Pull Device Enable Register (PERT)
Read: Anytime. Write: Anytime. This register configures whether a pull-up or a pull-down device is activated, if the port is used as input. This bit has no effect if the port is used as output. Out of reset no pull device is enabled.
Table 2-5. PERT Field Descriptions
Field 7-0 PERT[7:0] Description Pull Device Enable Port T Bits 0 Pull-up or pull-down device is disabled. 1 Either a pull-up or pull-down device is enabled.
MC3S12RG128 Data Sheet, Rev. 1.05 82 Freescale Semiconductor
Chapter 2 Port Integration Module (PIM3RG128V1) Block Description
2.3.2.1.6
Port T Polarity Select Register (PPST)
Module Base + 0x_0005
7 6 5 4 3 2 1 0
R PPST7 W Reset 0 0 0 0 0 0 0 0 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0
Figure 2-8. Port T Polarity Select Register (PPST)
Read: Anytime. Write: Anytime. This register selects whether a pull-down or a pull-up device is connected to the pin.
Table 2-6. PPST Field Descriptions
Field 7-0 PPST[7:0] Description Pull Select Port T Bits 0 A pull-up device is connected to the associated port T pin, if enabled by the associated bit in register PERT and if the port is used as input. 1 A pull-down device is connected to the associated port T pin, if enabled by the associated bit in register PERT and if the port is used as input.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 83
Chapter 2 Port Integration Module (PIM3RG128V1) Block Description
2.3.2.2
2.3.2.2.1
Port S Registers
Port S I/O Register (PTS)
Module Base + 0x_0008
7 6 5 4 3 2 1 0
R PTS7 W SS0 Reset 0 SCK0 0 MOSI0 0 MISO0 0 TXD1 0 RXD1 0 TXD0 0 RXD0 0 PTS6 PTS5 PTS4 PTS3 PTS2 PTS1 PTS0
Figure 2-9. Port S I/O Register (PTS)
Read: Anytime. Write: Anytime. If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port register, otherwise the value at the pins is read. * The SPI pins (PS[7:4]) configuration is determined by several status bits in the SPI module. Refer to SPI Block Guide for details. * The SCI ports associated with transmit pins 3 and 1 are configured as outputs if the transmitter is enabled. * The SCI ports associated with receive pins 2 and 0 are configured as inputs if the receiver is enabled. Refer to SCI Block Guide for details. 2.3.2.2.2 Port S Input Register (PTIS)
Module Base + 0x_0009
7 6 5 4 3 2 1 0
R W Reset
PTIS7
PTIS6
PTIS5
PTIS4
PTIS3
PTIS2
PTIS1
PTIS0
--
--
--
--
--
--
--
--
= Unimplemented or Reserved
Figure 2-10. Port S Input Register (PTIS)
Read: Anytime. Write: Never, writes to this register have no effect. This register always reads back the status of the associated pins. This also can be used to detect overload or short circuit conditions on output pins.
MC3S12RG128 Data Sheet, Rev. 1.05 84 Freescale Semiconductor
Chapter 2 Port Integration Module (PIM3RG128V1) Block Description
2.3.2.2.3
Port S Data Direction Register (DDRS)
Module Base + 0x_000A
7 6 5 4 3 2 1 0
R DDRS7 W Reset 0 0 0 0 0 0 0 0 DDRS6 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRS0
Figure 2-11. Port S Data Direction Register (DDRS)
Read: Anytime. Write: Anytime. This register configures each port S pin as either input or output. * If SPI is enabled, the SPI determines the pin direction. Refer to SPI Block Guide for details. * If the associated SCI transmit or receive channel is enabled this register has no effect on the pins. The pin is forced to be an output if a SCI transmit channel is enabled, it is forced to be an input if the SCI receive channel is enabled. * The DDRS bits revert to controlling the I/O direction of a pin when the associated channel is disabled.
Table 2-7. DDRS Field Descriptions
Field 7-0 DDRS[7:0] Description Data Direction Port S Bits 0 Associated pin is configured as input. 1 Associated pin is configured as output. Note: Due to internal synchronization circuits, it can take up to two bus cycles until the correct value is read on PTS or PTIS registers, when changing the DDRS register.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 85
Chapter 2 Port Integration Module (PIM3RG128V1) Block Description
2.3.2.2.4
Port S Reduced Drive Register (RDRS)
Module Base + 0x_000B
7 6 5 4 3 2 1 0
R RDRS7 W Reset 0 0 0 0 0 0 0 0 RDRS6 RDRS5 RDRS4 RDRS3 RDRS2 RDRS1 RDRS0
Figure 2-12. Port S Reduced Drive Register (RDRS)
Read: Anytime. Write: Anytime. This register configures the drive strength of each port S output pin as either full or reduced. If the port is used as input this bit is ignored.
Table 2-8. RDRS Field Descriptions
Field 7-0 RDRS[7:0] Description Reduced Drive Port S Bits 0 Full drive strength at output. 1 Associated pin drives at about 1/3 of the full drive strength.
2.3.2.2.5
Port S Pull Device Enable Register (PERS)
Module Base + 0x_000C
7 6 5 4 3 2 1 0
R PERS7 W Reset 1 1 1 1 1 1 1 1 PERS6 PERS5 PERS4 PERS3 PERS2 PERS1 PERS0
Figure 2-13. Port S Pull Device Enable Register (PERS)
Read: Anytime. Write: Anytime. This register configures whether a pull-up or a pull-down device is activated, if the port is used as input or as output in wired-OR (open drain) mode. This bit has no effect if the port is used as push-pull output. Out of reset a pull-up device is enabled.
Table 2-9. PERS Field Descriptions
Field 7-0 PERS[7:0] Description Pull Device Enable Port S Bits 0 Pull-up or pull-down device is disabled. 1 Either a pull-up or pull-down device is enabled.
MC3S12RG128 Data Sheet, Rev. 1.05 86 Freescale Semiconductor
Chapter 2 Port Integration Module (PIM3RG128V1) Block Description
2.3.2.2.6
Port S Polarity Select Register (PPSS)
Module Base + 0x_000D
7 6 5 4 3 2 1 0
R PPSS7 W Reset 0 0 0 0 0 0 0 0 PPSS6 PPSS5 PPSS4 PPSS3 PPSS2 PPSS1 PPSS0
Figure 2-14. Port S Polarity Select Register (PPSS)
Read: Anytime. Write: Anytime. This register selects whether a pull-down or a pull-up device is connected to the pin.
Table 2-10. PPSS Field Descriptions
Field 7-0 PPSS[7:0] Description Pull Select Port S Bits 0 A pull-up device is connected to the associated port S pin, if enabled by the associated bit in register PERS and if the port is used as input or as wired-OR output. 1 A pull-down device is connected to the associated port S pin, if enabled by the associated bit in register PERS and if the port is used as input.
2.3.2.2.7
Port S Wire-OR Mode Register (WOMS)
Module Base + 0x_000E
7 6 5 4 3 2 1 0
R WOMS7 W Reset 0 0 0 0 0 0 0 0 WOMS6 WOMS5 WOMS4 WOMS3 WOMS2 WOMS1 WOMS0
Figure 2-15. Port S Wired-OR Mode Register (WOMS)
Read: Anytime. Write: Anytime. This register configures the output pins as wired-OR. If enabled the output is driven active low only (open-drain). A logic level of "1" is not driven. It applies also to the SPI and SCI outputs and allows a multipoint connection of several serial modules. This bit has no influence on pins used as inputs.
Table 2-11. WOMS Field Descriptions
Field 7-0 Wired-OR Mode Port S Bits WOMS[7:0] 0 Output buffers operate as push-pull outputs. 1 Output buffers operate as open-drain outputs. Description
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 87
Chapter 2 Port Integration Module (PIM3RG128V1) Block Description
2.3.2.3
2.3.2.3.1
Port M Registers
Port M I/O Register (PTM)
Module Base + 0x_0010
7 6 5 4 3 2 1 0
R PTM7 W CAN CAN0 CAN4 SPI0 Reset 0 0 TXCAN4 RXCAN4 TXCAN0 TXCAN4 SCK0 0 RXCAN0 RXCAN4 MOSI0 0 SS0 0 MISO0 0 0 0 TXCAN0 RXCAN0 TXCAN0 RXCAN0 PTM6 PTM5 PTM4 PTM3 PTM2 PTM1 PTM0
Figure 2-16. Port M I/O Register (PTM)
Read: Anytime. Write: Anytime. If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port register, otherwise the value at the pins is read.
Table 2-12. PTM Field Descriptions
Field 7-6 PM[7:6} 5-4 PM[5:4] Description PM[7:6] * The CAN4 function (TXCAN4 and RXCAN4) takes precedence over the general purpose I/O function if the CAN4 module is enabled. Refer to MSCAN Block Guide for details. PM[5:4] * The CAN0 function (TXCAN0 and RXCAN0) takes precedence over the CAN4, the SPI0 and the general purpose I/O function if the CAN0 module is enabled. * The CAN4 function (TXCAN4 and RXCAN4) takes precedence over the SPI and general purpose I/O function if the CAN4 module is enabled. Refer to MSCAN Block Guide for details. * The SPI0 function (SCK0 and MOSI0) takes precedence of the general purpose I/O function if the SPI0 is enabled. Refer to SPI Block Guide for details. PM[3:2] * The CAN0 function (TXCAN0 and RXCAN0) takes precedence over the SPI0 and the general purpose I/O function if the CAN0 module is enabled. Refer to MSCAN Block Guide for details. * The SPI0 function (SS0 and MISO0) takes precedence of the general purpose I/O function if the SPI0 is enabled and not in bidirectional mode. Refer to SPI Block Guide for details. PM[1:0] * The CAN0 function (TXCAN0 and RXCAN0) takes precedence over the general purpose I/O function if the CAN0 module is enabled. Refer to MSCAN Block Guide for details.
3-2 PM[3:2]
1-0 PM[1:0]
MC3S12RG128 Data Sheet, Rev. 1.05 88 Freescale Semiconductor
Chapter 2 Port Integration Module (PIM3RG128V1) Block Description
2.3.2.3.2
Port M Input Register (PTIM)
Module Base + 0x_0011
7 6 5 4 3 2 1 0
R W Reset
PTIM7
PTIM6
PTIM5
PTIM4
PTIM3
PTIM2
PTIM1
PTIM0
--
--
--
--
--
--
--
--
= Unimplemented or Reserved
Figure 2-17. Port M Input Register (PTIM)
Read: Anytime. Write: Never, writes to this register have no effect. This register always reads back the status of the associated pins. This can also be used to detect overload or short circuit conditions on output pins.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 89
Chapter 2 Port Integration Module (PIM3RG128V1) Block Description
2.3.2.3.3
Port M Data Direction Register (DDRM)
Module Base + 0x_0012
7 6 5 4 3 2 1 0
R DDRM7 W Reset 0 0 0 0 0 0 0 0 DDRM6 DDRM5 DDRM4 DDRM3 DDRM2 DDRM1 DDRM0
Figure 2-18. Port M Data Direction Register (DDRM)
Read: Anytime. Write: Anytime. This register configures each port M pin as either input or output. * The CAN forces the I/O state to be an output for each port line associated with an enabled output (TXCAN0). It also forces the I/O state to be an input for each port line associated with an enabled input (RXCAN0). In those cases the data direction bits will not change. * The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled.
Table 2-13. DDRM Field Descriptions
Field 7-0 DDRM[7:0] Description Data Direction Port M Bits 0 Associated pin is configured as input. 1 Associated pin is configured as output. Note: Due to internal synchronization circuits, it can take up to two bus cycles until the correct value is read on PTM or PTIM registers, when changing the DDRM register.
MC3S12RG128 Data Sheet, Rev. 1.05 90 Freescale Semiconductor
Chapter 2 Port Integration Module (PIM3RG128V1) Block Description
2.3.2.3.4
Port M Reduced Drive Register (RDRM)
Module Base + 0x_0013
7 6 5 4 3 2 1 0
R RDRM7 W Reset 0 0 0 0 0 0 0 0 RDRM6 RDRM5 RDRM4 RDRM3 RDRM2 RDRM1 RDRM0
Figure 2-19. Port M Reduced Drive Register (RDRM)
Read: Anytime. Write: Anytime. This register configures the drive strength of each port M output pin as either full or reduced. If the port is used as input this bit is ignored.
Table 2-14. RDRM Field Descriptions
Field 7-0 RDRM[7:0] Description Reduced Drive Port M Bits 0 Full drive strength at output. 1 Associated pin drives at about 1/3 of the full drive strength.
2.3.2.3.5
Port M Pull Device Enable Register (PERM)
Module Base + 0x_0014
7 6 5 4 3 2 1 0
R PERM7 W Reset 0 0 0 0 0 0 0 0 PERM6 PERM5 PERM4 PERM3 PERM2 PERM1 PERM0
Figure 2-20. Port M Pull Device Enable Register (PERM)
Read: Anytime. Write: Anytime. This register configures whether a pull-up or a pull-down device is activated, if the port is used as input or wired-OR output. This bit has no effect if the port is used as push-pull output. Out of reset no pull device is enabled.
Table 2-15. PERM Field Descriptions
Field 7-0 PERM[7:0] Description Pull Device Enable Port M Bits 0 Pull-up or pull-down device is disabled. 1 Either a pull-up or pull-down device is enabled.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 91
Chapter 2 Port Integration Module (PIM3RG128V1) Block Description
2.3.2.3.6
Port M Polarity Select Register (PPSM)
Module Base + 0x_0015
7 6 5 4 3 2 1 0
R PPSM7 W Reset 0 0 0 0 0 0 0 0 PPSM6 PPSM5 PPSM4 PPSM3 PPSM2 PPSM1 PPSM0
Figure 2-21. Port M Polarity Select Register (PPSM)
Read: Anytime. Write: Anytime. This register selects whether a pull-down or a pull-up device is connected to the pin. If CAN is active a pull-up device can be activated on the RXCAN0 input, but not a pull-down.
Table 2-16. PPSM Field Descriptions
Field 7-0 PPSM[7:0] Description Pull Select Port M Bits 0 A pull-up device is connected to the associated port M pin, if enabled by the associated bit in register PERM and if the port is used as general purpose or RXCAN input. 1 A pull-down device is connected to the associated port M pin, if enabled by the associated bit in register PERM and if the port is used as a general purpose but not as RXCAN.
2.3.2.3.7
Port M Wire-OR Mode Register (WOMM)
Module Base + 0x_0016
7 6 5 4 3 2 1 0
R WOMM7 W Reset 0 0 0 0 0 0 0 0 WOMM6 WOMM5 WOMM4 WOMM3 WOMM2 WOMM1 WOMM0
Figure 2-22. Port M Wired-OR Mode Register (WOMM)
Read: Anytime. Write: Anytime. This register configures the output pins as wired-OR. If enabled the output is driven active low only (open-drain). A logic level of "1" is not driven. It applies also to the CAN and outputs and allows a multipoint connection of several serial modules. This bit has no influence on pins used as inputs.
Table 2-17. WOMM Field Descriptions
Field 7-0 Wired-OR Mode Port M Bits WOMM[7:0] 0 Output buffers operate as push-pull outputs. 1 Output buffers operate as open-drain outputs. Description
MC3S12RG128 Data Sheet, Rev. 1.05 92 Freescale Semiconductor
Chapter 2 Port Integration Module (PIM3RG128V1) Block Description
2.3.2.4
Module Routing Register (MODRR)
Module Base + 0x_0017
7 6 5 4 3 2 1 0
R W Reset
0
0 MODRR5 MODRR4 0 MODRR3 0 MODRR2 0 MODRR1 0 MODRR0 0
0
0
0
= Unimplemented or Reserved
Figure 2-23. Module Routing Register (MODRR)
Read: Anytime. Write: Anytime. This register configures the re-routing of CAN0, CAN4, SPI0, SPI1, and SPI2 on defined port pins.
Table 2-18. MODRR Field Descriptions
Field 5 MODRR5 4 MODRR4 SPI1 Routing Bit -- See Table 2-19. CAN0 Routing Bit -- See Table 2-22. Description
3-2 CAN4 Routing Bit -- See Table 2-21. MODRR[3:2] 1-0 SPI0 Routing Bit -- See Table 2-20. MODRR[1:0]
Table 2-19. SPI1 Routing
MODRR[5] 0 1 MISO1 PP0 PH0 MOSI1 PP1 PH1 SCK1 PP2 PH2 SS1 PP3 PH3
Table 2-20. SPI0 Routing
MODRR[4] 0 1 MISO0 PS4 PM2 MOSI0 PS5 PM4 SCK0 PS6 PM5 SS0 PS7 PM3
Table 2-21. CAN4 Routing
MODRR[3] 0 0 1 MODRR[2] 0 1 0 RXCAN4 PJ6 PM4 PM6 TXCAN4 PJ7 PM5 PM7
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 93
Chapter 2 Port Integration Module (PIM3RG128V1) Block Description
Table 2-21. CAN4 Routing
MODRR[3] 1 MODRR[2] 1 RXCAN4 TXCAN4
Reserved
Table 2-22. CAN0 Routing
MODRR[1] 0 0 1 1 MODRR[0] 0 1 0 1 RXCAN0 PM0 PM2 PM4 PJ6 TXCAN0 PM1 PM3 PM5 PJ7
2.3.2.5
2.3.2.5.1
Port P Registers
Port P I/O Register (PTP)
Module Base + 0x_0018
7 6 5 4 3 2 1 0
R PTP7 W PWM SPI Reset PWM7 SCK2 0 PWM6 SS2 0 PWM5 MOSI2 0 PWM4 MISO2 0 PWM3 SS1 0 PWM2 SCK1 0 PWM1 MOSI1 0 PWM0 MISO1 0 PTP6 PTP5 PTP4 PTP3 PTP2 PTP1 PTP0
Figure 2-24. Port P I/O Register (PTP)
Read: Anytime. Write: Anytime. If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port register, otherwise the value at the pins is read. * The PWM function takes precedence over the general purpose I/O function if the associated PWM channel is enabled. While channels 6-0 are output only if the respective channel is enabled, channel 7 can be PWM output or input if the shutdown feature is enabled. Refer to PWM Block Guide for details. * The SPI function takes precedence over the general purpose I/O function associated with if enabled. Refer to SPI Block Guide for details. * If both PWM and SPI are enabled the PWM functionality takes precedence.
MC3S12RG128 Data Sheet, Rev. 1.05 94 Freescale Semiconductor
Chapter 2 Port Integration Module (PIM3RG128V1) Block Description
2.3.2.5.2
Port P Input Register (PTIP)
Module Base + 0x_0019
7 6 5 4 3 2 1 0
R W Reset
PTIP7
PTIP6
PTIP5
PTIP4
PTIP3
PTIP2
PTIP1
PTIP0
--
--
--
--
--
--
--
--
= Unimplemented or Reserved
Figure 2-25. Port P Input Register (PTIP)
Read: Anytime. Write: Never, writes to this register have no effect. This register always reads back the status of the associated pins. This can be also used to detect overload or short circuit conditions on output pins. 2.3.2.5.3 Port P Data Direction Register (DDRP)
Module Base + 0x_001A
7 6 5 4 3 2 1 0
R DDRP7 W Reset 0 0 0 0 0 0 0 0 DDRP6 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0
Figure 2-26. Port P Data Direction Register (DDRP)
Read: Anytime. Write: Anytime. This register configures each port P pin as either input or output. * If the associated PWM channel or SPI module is enabled this register has no effect on the pins. * The PWM forces the I/O state to be an output for each port line associated with an enabled PWM7-0 channel. Channel 7 can force the pin to input if the shutdown feature is enabled. * If a SPI module is enabled, the SPI determines the pin direction. Refer to SPI Block Guide for details. * The DDRM bits revert to controlling the I/O direction of a pin when the associated PWM channel is disabled.
Table 2-23. DDRP Field Descriptions
Field 7-0 DDRP[7:0] Description Data Direction Port P Bits 0 Associated pin is configured as input. 1 Associated pin is configured as output. Note: Due to internal synchronization circuits, it can take up to 2 bus cycles until the correct value is read on PTP or PTIP registers, when changing the DDRP register.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 95
Chapter 2 Port Integration Module (PIM3RG128V1) Block Description
2.3.2.5.4
Port P Reduced Drive Register (RDRP)
Module Base + 0x_001B
7 6 5 4 3 2 1 0
R RDRP7 W Reset 0 0 0 0 0 0 0 0 RDRP6 RDRP5 RDRP4 RDRP3 RDRP2 RDRP1 RDRP0
Figure 2-27. Port P Reduced Drive Register (RDRP)
Read: Anytime. Write: Anytime. This register configures the drive strength of each port P output pin as either full or reduced. If the port is used as input this bit is ignored.
Table 2-24. RDRP Field Descriptions
Field 7-0 RDRP[7:0] Description Reduced Drive Port P Bits 0 Full drive strength at output. 1 Associated pin drives at about 1/3 of the full drive strength.
2.3.2.5.5
Port P Pull Device Enable Register (PERP)
Module Base + 0x_001C
7 6 5 4 3 2 1 0
R PERP7 W Reset 0 0 0 0 0 0 0 0 PERP6 PERP5 PERP4 PERP3 PERP2 PERP1 PERP0
Figure 2-28. Port P Pull Device Enable Register (PERP)
Read: Anytime. Write: Anytime. This register configures whether a pull-up or a pull-down device is activated, if the port is used as input. This bit has no effect if the port is used as output. Out of reset no pull device is enabled.
Table 2-25. PERP Field Descriptions
Field 7-0 PERP[7:0] Description Pull Device Enable Port P Bits 0 Pull-up or pull-down device is disabled. 1 Either a pull-up or pull-down device is enabled.
MC3S12RG128 Data Sheet, Rev. 1.05 96 Freescale Semiconductor
Chapter 2 Port Integration Module (PIM3RG128V1) Block Description
2.3.2.5.6
Port P Polarity Select Register (PPSP)
Module Base + 0x_001D
7 6 5 4 3 2 1 0
R PPSP7 W Reset 0 0 0 0 0 0 0 0 PPSP6 PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSP0
Figure 2-29. Port P Polarity Select Register (PPSP)
Read: Anytime. Write: Anytime. This register serves a dual purpose by selecting the polarity of the active interrupt edge as well as selecting a pull-up or pull-down device if enabled.
Table 2-26. PPSP Field Descriptions
Field 7-0 PPSP[7:0] Description Polarity Select Port P Bits 0 Falling edge on the associated port P pin sets the associated flag bit in the PIFP register. A pull-up device is connected to the associated port P pin, if enabled by the associated bit in register PERP and if the port is used as input. 1 Rising edge on the associated port P pin sets the associated flag bit in the PIFP register. A pull-down device is connected to the associated port P pin, if enabled by the associated bit in register PERP and if the port is used as input.
2.3.2.5.7
Port P Interrupt Enable Register (PIEP)
Module Base + 0x_001E
7 6 5 4 3 2 1 0
R PIEP7 W Reset 0 0 0 0 0 0 0 0 PIEP6 PIEP5 PIEP4 PIEP3 PIEP2 PIEP1 PIEP0
Figure 2-30. Port P Interrupt Enable Register (PIEP)
Read: Anytime. Write: Anytime. This register disables or enables on a per pin basis the edge sensitive external interrupt associated with port P.
Table 2-27. PIEP Field Descriptions
Field 7-0 PIEP[7:0] Interrupt Enable Port P Bits 0 Interrupt is disabled (interrupt flag masked). 1 Interrupt is enabled. Description
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 97
Chapter 2 Port Integration Module (PIM3RG128V1) Block Description
2.3.2.5.8
Port P Interrupt Flag Register (PIFP)
Module Base + 0x_001F
7 6 5 4 3 2 1 0
R PIFP7 W Reset 0 0 0 0 0 0 0 0 PIFP6 PIFP5 PIFP4 PIFP3 PIFP2 PIFP1 PIFP0
Figure 2-31. Port P Interrupt Flag Register (PIFP)
Read: Anytime. Write: Anytime. Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based on the state of the PPSP register. To clear this flag, write "1" to the corresponding bit in the PIFP register. Writing a "0" has no effect.
Table 2-28. Field PIFP Descriptions
Field 7-0 PIFP[7:0] Description Interrupt Flags Port P Bits 0 No active edge pending. Writing a "0" has no effect. 1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set). Writing a "1" clears the associated flag.
2.3.2.6
2.3.2.6.1
Port H Registers
Port H I/O Register (PTH)
Module Base + 0x_0020
7 6 5 4 3 2 1 0
R PTH7 W SPI Reset SS2 0 SCK2 0 MOSI2 0 MISO2 0 SS1 0 SCK1 0 MOSI1 0 MISO1 0 PTH6 PTH5 PTH4 PTH3 PTH2 PTH1 PTH0
Figure 2-32. Port H I/O Register (PTH)
Read: Anytime. Write: Anytime. If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port register, otherwise the value at the pins is read. The SPI function takes precedence over the general purpose I/O function associated with if enabled. Refer to SPI Block Guide for details.
MC3S12RG128 Data Sheet, Rev. 1.05 98 Freescale Semiconductor
Chapter 2 Port Integration Module (PIM3RG128V1) Block Description
2.3.2.6.2
Port H Input Register (PTIH)
Module Base + 0x_0021
7 6 5 4 3 2 1 0
R W Reset
PTIH7
PTIH6
PTIH5
PTIH4
PTIH3
PTIH2
PTIH1
PTIH0
--
--
--
--
--
--
--
--
= Unimplemented or Reserved
Figure 2-33. Port H Input Register (PTIH)
Read: Anytime. Write: Never, writes to this register have no effect. This register always reads back the status of the associated pins. This can also be used to detect overload or short circuit conditions on output pins. 2.3.2.6.3 Port H Data Direction Register (DDRH)
Module Base + 0x_0022
7 6 5 4 3 2 1 0
R DDRH7 W Reset 0 0 0 0 0 0 0 0 DDRH6 DDRH5 DDRH4 DDRH3 DDRH2 DDRH1 DDRH0
Figure 2-34. Port H Data Direction Register (DDRH)
Read: Anytime. Write: Anytime. This register configures each port H pin as either input or output.
Table 2-29. DDRH Field Descriptions
Field 7-0 DDRH[7:0] Description Data Direction Port H Bits 0 Associated pin is configured as input. 1 Associated pin is configured as output. Note: Due to internal synchronization circuits, it can take up to two bus cycles until the correct value is read on PTH or PTIH registers, when changing the DDRH register.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 99
Chapter 2 Port Integration Module (PIM3RG128V1) Block Description
2.3.2.6.4
Port H Reduced Drive Register (RDRH)
Module Base + 0x_0023
7 6 5 4 3 2 1 0
R RDRH7 W Reset 0 0 0 0 0 0 0 0 RDRH6 RDRH5 RDRH4 RDRH3 RDRH2 RDRH1 RDRH0
Figure 2-35. Port H Reduced Drive Register (RDRH)
Read: Anytime. Write: Anytime. This register configures the drive strength of each port H output pin as either full or reduced. If the port is used as input this bit is ignored.
Table 2-30. RDRH Field Descriptions
Field 7-0 RDRH[7:0] Description Reduced Drive Port H Bits 0 Full drive strength at output. 1 Associated pin drives at about 1/3 of the full drive strength.
2.3.2.6.5
Port H Pull Device Enable Register (PERH)
Module Base + 0x_0024
7 6 5 4 3 2 1 0
R PERH7 W Reset 0 0 0 0 0 0 0 0 PERH6 PERH5 PERH4 PERH3 PERH2 PERH1 PERH0
Figure 2-36. Port H Pull Device Enable Register (PERH)
Read: Anytime. Write: Anytime. This register configures whether a pull-up or a pull-down device is activated, if the port is used as input. This bit has no effect if the port is used as output. Out of reset no pull device is enabled.
Table 2-31. PERH Field Descriptions
Field 7-0 PERH[7:0] Description Pull Device Enable Port H Bits 0 Pull-up or pull-down device is disabled. 1 Either a pull-up or pull-down device is enabled.
MC3S12RG128 Data Sheet, Rev. 1.05 100 Freescale Semiconductor
Chapter 2 Port Integration Module (PIM3RG128V1) Block Description
2.3.2.6.6
Port H Polarity Select Register (PPSH)
Module Base + 0x_0025
7 6 5 4 3 2 1 0
R PPSH7 W Reset 0 0 0 0 0 0 0 0 PPSH6 PPSH5 PPSH4 PPSH3 PPSH2 PPSH1 PPSH0
Figure 2-37. Port H Polarity Select Register (PPSH)
Read: Anytime. Write: Anytime. This register serves a dual purpose by selecting the polarity of the active interrupt edge as well as selecting a pull-up or pull-down device if enabled.
Table 2-32. PPSH Field Descriptions
Field 7-0 PPSH[7:0] Description Polarity Select Port H Bits 0 Falling edge on the associated port H pin sets the associated flag bit in the PIFH register. A pull-up device is connected to the associated port H pin, if enabled by the associated bit in register PERH and if the port is used as input. 1 Rising edge on the associated port H pin sets the associated flag bit in the PIFH register. A pull-down device is connected to the associated port H pin, if enabled by the associated bit in register PERH and if the port is used as input.
2.3.2.6.7
Port H Interrupt Enable Register (PIEH)
Module Base + 0x_0026
7 6 5 4 3 2 1 0
R PIEH7 W Reset 0 0 0 0 0 0 0 0 PIEH6 PIEH5 PIEH4 PIEH3 PIEH2 PIEH1 PIEH0
Figure 2-38. Port H Interrupt Enable Register (PIEH)
Read: Anytime. Write: Anytime. This register disables or enables on a per pin basis the edge sensitive external interrupt associated with port H.
Table 2-33. PIEH Field Descriptions
Field 7-0 PIEH[7:0] Interrupt Enable Port H Bits 0 Interrupt is disabled (interrupt flag masked). 1 Interrupt is enabled. Description
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 101
Chapter 2 Port Integration Module (PIM3RG128V1) Block Description
2.3.2.6.8
Port H Interrupt Flag Register (PIFH)
Module Base + 0x_0027
7 6 5 4 3 2 1 0
R PIFH7 W Reset 0 0 0 0 0 0 0 0 PIFH6 PIFH5 PIFH4 PIFH3 PIFH2 PIFH1 PIFH0
Figure 2-39. Port H Interrupt Flag Register (PIFH)
Read: Anytime. Write: Anytime. Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based on the state of the PPSH register. To clear this flag, write "1" to the corresponding bit in the PIFH register. Writing a "0" has no effect.
Table 2-34. PIFH Field Descriptions
Field 7-0 PIFH[7:0] Description Interrupt Flags Port H Bits 0 No active edge pending. Writing a "0" has no effect. 1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set). Writing a "1" clears the associated flag.
MC3S12RG128 Data Sheet, Rev. 1.05 102 Freescale Semiconductor
Chapter 2 Port Integration Module (PIM3RG128V1) Block Description
2.3.2.7
2.3.2.7.1
Port J Registers
Port J I/O Register (PTJ)
Module Base + 0x_0028
7 6 5 4 3 2 1 0
R PTJ7 W CAN4 IIC CAN0 Reset TXCAN4 SCL TXCAN0 0 RXCAN4 SDA RXCAN0 0 PTJ6
0
0
0
0 PTJ1 PTJ0
--
--
--
--
0
0
= Unimplemented or Reserved
Figure 2-40. Port J I/O Register (PTJ)
Read: Anytime. Write: Anytime. If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port register, otherwise the value at the pins is read.
Table 2-35. PTJ Field Descriptions
Field 7-6 PJ[7:6] Description PJ7-PJ6 * The CAN4 function (TXCAN4 and RXCAN4) takes precedence over the IIC, the CAN0 and the general purpose I/O function if the CAN4 module is enabled. * The IIC function (SCL and SDA) takes precedence over CAN0 and the general purpose I/O function if the IIC is enabled. If the IIC module takes precedence the SDA and SCL outputs are configured as open drain outputs. Refer to IIC Block Guide for details. * The CAN0 function (TXCAN0 and RXCAN0) takes precedence over the general purpose I/O function if the CAN0 module is enabled.Refer to MSCAN Block Guide for details.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 103
Chapter 2 Port Integration Module (PIM3RG128V1) Block Description
2.3.2.7.2
Port J Input Register (PTIJ)
Module Base + 0x_0029
7 6 5 4 3 2 1 0
R W Reset
PTIJ7
PTIJ6
0
0
0
0
PTIJ1
PTIJ0
--
--
--
--
--
--
--
--
= Unimplemented or Reserved
Figure 2-41. Port J Input Register (PTIJ)
Read: Anytime. Write: Never, writes to this register have no effect. This register always reads back the status of the associated pins. This can be used to detect overload or short circuit conditions on output pins. 2.3.2.7.3 Port J Data Direction Register (DDRJ)
Module Base + 0x_002A
7 6 5 4 3 2 1 0
R DDRJ7 W Reset 0 0 DDRJ6
0
0
0
0 DDRJ1 DDRJ0 0
--
--
--
--
0
= Unimplemented or Reserved
Figure 2-42. Port J Data Direction Register (DDRJ))
Read: Anytime. Write: Anytime. This register configures each port J pin as either input or output. The CAN forces the I/O state to be an output on PJ7 (TXCAN4) and an input on pin PJ6 (RXCAN4). The IIC takes control of the I/O if enabled. In these cases the data direction bits will not change. The DDRJ bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled.
Table 2-36. DDRJ Field Descriptions
Field 7, 6, 1, 0 DDRJ[7:6] DDRJ[1:0} Description Data Direction Port J Bits 0 Associated pin is configured as input. 1 Associated pin is configured as output. Note: Due to internal synchronization circuits, it can take up to two bus cycles until the correct value is read on PTJ or PTIJ registers, when changing the DDRJ register.
MC3S12RG128 Data Sheet, Rev. 1.05 104 Freescale Semiconductor
Chapter 2 Port Integration Module (PIM3RG128V1) Block Description
2.3.2.7.4
Port J Reduced Drive Register (RDRJ)
Module Base + 0x_002B
7 6 5 4 3 2 1 0
R RDRJ7 W Reset 0 0 RDRJ6
0
0
0
0 RDRJ1 RDRJ0 0
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-43. Port J Reduced Drive Register (RDRJ)
Read: Anytime. Write: Anytime. This register configures the drive strength of each port J output pin as either full or reduced. If the port is used as input this bit is ignored.
Table 2-37. RDRJ Field Descriptions
Field 7, 6, 1, 0 RDRJ[7:6] RDRJ[1:0] Description Reduced Drive Port J Bits 0 Full drive strength at output. 1 Associated pin drives at about 1/3 of the full drive strength.
2.3.2.7.5
Port J Pull Device Enable Register (PERJ)
Module Base + 0x_002C
7 6 5 4 3 2 1 0
R PERJ7 W Reset 1 1 PERJ6
0
0
0
0 PERJ1 PERJ0 1
--
--
--
--
1
= Unimplemented or Reserved
Figure 2-44. Port J Pull Device Enable Register (PERJ)
Read: Anytime. Write: Anytime. This register configures whether a pull-up or a pull-down device is activated, if the port is used as input or as wired-OR output. This bit has no effect if the port is used as push-pull output. Out of reset a pull-up device is enabled.
Table 2-38. PERJ Field Descriptions
Field 7, 6, 1, 0 PERJ[7:6] PERJ[1:0] Description Pull Device Enable Port J Bits 0 Pull-up or pull-down device is disabled. 1 Either a pull-up or pull-down device is enabled.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 105
Chapter 2 Port Integration Module (PIM3RG128V1) Block Description
2.3.2.7.6
Port J Polarity Select Register (PPSJ)
Module Base + 0x_002D
7 6 5 4 3 2 1 0
R PPSJ7 W Reset 0 0 PPSJ6
0
0
0
0 PPSJ1 PPSJ0 0
--
--
--
--
0
= Unimplemented or Reserved
Figure 2-45. Port J Polarity Select Register (PPSJ)
Read: Anytime. Write: Anytime. This register serves a dual purpose by selecting the polarity of the active interrupt edge as well as selecting a pull-up or pull-down device if enabled.
Table 2-39. PPSJ Field Descriptions
Field 7, 6, 1, 0 PPSJ[7:6] PPSJ]1:0] Description Polarity Select Port J Bits 0 Falling edge on the associated port J pin sets the associated flag bit in the PIFJ register. A pull-up device is connected to the associated port J pin, if enabled by the associated bit in register PERJ and if the port is used as general purpose input or as IIC port. 1 Rising edge on the associated port J pin sets the associated flag bit in the PIFJ register. A pull-down device is connected to the associated port J pin, if enabled by the associated bit in register PERJ and if the port is used as input.
MC3S12RG128 Data Sheet, Rev. 1.05 106 Freescale Semiconductor
Chapter 2 Port Integration Module (PIM3RG128V1) Block Description
2.3.2.7.7
Port J Interrupt Enable Register (PIEJ)
Module Base + 0x_002E
7 6 5 4 3 2 1 0
R W Reset
PIEJ7 0
PIEJ6 0
0
0
0
0
PIEJ1 0
PIEJ0 0
--
--
--
--
= Unimplemented or Reserved
Figure 2-46. Port J Interrupt Enable Register (PIEJ)
Read: Anytime. Write: Anytime. This register disables or enables on a per pin basis the edge sensitive external interrupt associated with port J.
Table 2-40. PIEJ Field Descriptions
Field 7, 6, 1, 0 PIEJ[7:6] PIEJ]1:0] Interrupt Enable Port J Bits 0 Interrupt is disabled (interrupt flag masked). 1 Interrupt is enabled. Description
2.3.2.7.8
Port J Interrupt Flag Register (PIFJ)
Module Base + 0x_002F
7 6 5 4 3 2 1 0
R PIFJ7 W Reset 0 0 PIFJ6
0
0
0
0 PIFJ1 PIFJ0 0
--
--
--
--
0
= Unimplemented or Reserved
Figure 2-47. Port J Interrupt Flag Register (PIFJ)
Read: Anytime. Write: Anytime. Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based on the state of the PPSJ register. To clear this flag, write "1" to the corresponding bit in the PIFJ register. Writing a "0" has no effect.
Table 2-41. PIFJ Field Descriptions
Field 7, 6, 1, 0 PIFJ[7:6] PIFJ[1:0] Description Interrupt Flags Port J Bits 0 No active edge pending. Writing a "0" has no effect. 1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set). Writing a "1" clears the associated flag. MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 107
Chapter 2 Port Integration Module (PIM3RG128V1) Block Description
2.4
Functional Description
Each pin can act as general purpose I/O. In addition the pin can act as an output from a peripheral module or an input to a peripheral module. A set of configuration registers is common to all ports. All registers can be written at any time; however a specific configuration might not become active. Example: Selecting a pull-up resistor. This resistor does not become active while the port is used as a push-pull output.
2.4.1
I/O Register
This register holds the value driven out to the pin if the port is used as a general purpose I/O. Writing to this register has only an effect on the pin if the port is used as general purpose output. When reading this address, the value of the pins is returned if the data direction register bits are set to 0. If the data direction register bits are set to 1, the contents of the I/O register is returned. This is independent of any other configuration (Figure 2-48).
2.4.2
Input Register
This is a read-only register and always returns the value of the pin (Figure 2-48).
2.4.3
Data Direction Register
This register defines whether the pin is used as an input or an output. If a peripheral module controls the pin the contents of the data direction register is ignored (Figure 2-48).
PTI 0 1 PAD
PT
0 1
DDR
0 1 DATA OUT
MODULE
OUTPUT ENABLE MODULE ENABLE
Figure 2-48. Illustration of I/O Pin Functionality
MC3S12RG128 Data Sheet, Rev. 1.05 108 Freescale Semiconductor
Chapter 2 Port Integration Module (PIM3RG128V1) Block Description
2.4.4
Reduced Drive Register
If the port is used as an output the register allows the configuration of the drive strength.
2.4.5
Pull Device Enable Register
This register turns on a pull-up or pull-down device. It becomes active only if the pin is used as an input or as a wired-OR output.
2.4.6
Polarity Select Register
This register selects either a pull-up or pull-down device if enabled. It becomes active only if the pin is used as an input. A pull-up device can be activated if the pin is used as a wired-OR output.
2.4.7
Port T
This port is associated with the ECT module. Port T pins PT[7:0] can be used for either general-purpose I/O, or with the channels of the Enhanced Capture Timer. During reset, port T pins are configured as high-impedance inputs.
2.4.8
Port S
This port is associated with SCI0, SCI1, and SPI0. Port S pins PS[7:0] can be used either for general-purpose I/O, or with the SCI and SPI subsystems. During reset, port S pins are configured as inputs with pull-up. The SPI0 pins can be re-routed. Refer to Figure 2-23.
2.4.9
Port M
This port is associated with the CAN4, CAN0, and SPI0. Port M pins PM[7:0] can be used for either general purpose I/O, or with the CAN and SPI subsystems. During reset, port M pins are configured as high-impedance inputs. The CAN0, CAN4, and SPI0 pins can be re-routed. Refer to Figure 2-23.
2.4.9.1
Module Routing Register
NOTE The purpose of the Module Routing Register is to provide maximum flexibility for future derivatives of the MC3S12RG128 with a lower number of MSCAN and SPI modules.
This register allows to re-route the CAN0, CAN4, SPI0, and SPI1 pins to predefined pins.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 109
Chapter 2 Port Integration Module (PIM3RG128V1) Block Description
Table 2-42. Implemented Modules on Derivatives
Number of Modules 2 1 MSCAN Modules CAN0 X X CAN4 X -- SPI Modules SPI0 X X SPI1 X --
2.4.10
Port P
This port is associated with the PWM and SPI1. Port P pins PP[7:0] can be used for either general purpose I/O, or with the PWM and SPI subsystems. The pins are shared between the PWM channels and the SPI1 module. If the PWM is enabled the pins become PWM output channels with the exception of pin 7 which can be PWM input or output. If SPI1 is enabled and PWM is disabled, the respective pin configuration is determined by several status bits in the SPI1 module. During reset, port P pins are configured as high-impedance inputs. The SPI1 pins can be re-routed. Refer to Figure 2-23. Port P offers eight I/O pins with edge triggered interrupt capability in wired-OR fashion. The interrupt enable as well as the sensitivity to rising or falling edges can be individually configured on per pin basis. All eight bits/pins share the same interrupt vector. Interrupts can be used with the pins configured as inputs or outputs. An interrupt is generated when a bit in the port interrupt flag register and its corresponding port interrupt enable bit are both set. This external interrupt feature is capable to wake up the CPU when it is in Stop or Wait mode. A digital filter on each pin prevents pulses (Figure 2-50) shorter than a specified time from generating an interrupt. The minimum time varies over process conditions, temperature and voltage (Figure 2-49 and Table 2-43).
GLITCH, FILTERED OUT, NO INTERRUPT FLAG SET
VALID PULSE, INTERRUPT FLAG SET
UNCERTAIN
tpign tpval
Figure 2-49. Interrupt Glitch Filter on Port P, H, and J (PPS = 0)
MC3S12RG128 Data Sheet, Rev. 1.05 110 Freescale Semiconductor
Chapter 2 Port Integration Module (PIM3RG128V1) Block Description
Table 2-43. Pulse Detection Criteria
Mode Pulse STOP Unit Ignored Uncertain Valid
1
STOP1
tpulse 3 3 < tpulse < 4 tpulse 4
Bus clocks Bus clocks Bus clocks
tpulse tpign tpign < tpulse < tpval tpulse tpval
These values include the spread of the oscillator frequency over temperature, voltage and process.
tpulse
Figure 2-50. Pulse Illustration
A valid edge on an input is detected if four consecutive samples of a passive level are followed by four consecutive samples of an active level directly or indirectly. The filters are continuously clocked by the bus clock in Run and Wait mode. In Stop mode the clock is generated by a single RC oscillator in the Port Integration Module. To maximize current saving the RC oscillator runs only if the following condition is true on any pin: Sample count <= 4 and port interrupt enabled (PIE = 1) and port interrupt flag not set (PIF = 0).
2.4.11
Port H
This port is associated with the SPI1. Port H pins PH[7:0] can be used for either general purpose I/O, or with the SPI subsystems. During reset, port H pins are configured as high-impedance inputs. Port H pins can be used with the routed SPI1 module. Refer to Figure 2-23. Port H offers eight I/O ports with the same interrupt features as port P.
2.4.12
Port J
This port is associated with the CAN4, CAN0, and the IIC. Port J pins PJ[7:6] and PJ[1:0] can be used for either general purpose I/O, or with the CAN and IIC subsystems. During reset, port J pins are configured as inputs with pull-up. If IIC takes precedence the pins become IIC open-drain output pins. The CAN4 pins can be re-routed. Refer to Figure 2-23. Port J pins can be used with the routed CAN0 modules. Refer to Figure 2-23. Port J offers four I/O ports with the same interrupt features as port P.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 111
Chapter 2 Port Integration Module (PIM3RG128V1) Block Description
2.4.13
Port A, B, E, K, and BKGD Pin
All port and pin logic is located in the core module. Refer to MEBI in HCS12 Core User Guide for details.
2.4.14
External Pin Descriptions
All ports start up as general-purpose inputs on reset.
2.4.15
2.4.15.1
Low-Power Options
Run Mode
No low-power options exist for this module in run mode.
2.4.15.2
Wait Mode
No low-power options exist for this module in wait mode.
2.4.15.3
Stop Mode
All clocks are stopped. There are asynchronous paths to generate interrupts from STOP on port P, H, and J.
MC3S12RG128 Data Sheet, Rev. 1.05 112 Freescale Semiconductor
Chapter 3 Module Mapping Control (MMCV5) Block Description
3.1 Introduction
This section describes the functionality of the module mapping control (MMC) sub-block of the S12 core platform. The block diagram of the MMC is shown in Figure 3-1.
MMC SECURE BDM_UNSECURE STOP, WAIT SECURITY MMC_SECURE
ADDRESS DECODE READ & WRITE ENABLES CLOCKS, RESET MODE INFORMATION INTERNAL MEMORY EXPANSION REGISTERS PORT K INTERFACE MEMORY SPACE SELECT(S) PERIPHERAL SELECT EBI ALTERNATE ADDRESS BUS EBI ALTERNATE WRITE DATA BUS EBI ALTERNATE READ DATA BUS ALTERNATE ADDRESS BUS (BDM) CPU ADDRESS BUS CPU READ DATA BUS CPU WRITE DATA BUS CPU CONTROL BUS CONTROL ALTERNATE WRITE DATA BUS (BDM) ALTERNATE READ DATA BUS (BDM) CORE SELECT (S)
Figure 3-1. MMC Block Diagram
The MMC is the sub-module which controls memory map assignment and selection of internal resources and external space. Internal buses between the core and memories and between the core and peripherals is controlled in this module. The memory expansion is generated in this module.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 113
Chapter 3 Module Mapping Control (MMCV5) Block Description
3.1.1
* * * * * * * * * * *
Features
Registers for mapping of address space for on-chip RAM, EEPROM, and FLASH (or ROM) memory blocks and associated registers Memory mapping control and selection based upon address decode and system operating mode Core address bus control Core data bus control and multiplexing Core security state decoding Emulation chip select signal generation (ECS) External chip select signal generation (XCS) Internal memory expansion External stretch and ROM mapping control functions via the MISC register Reserved registers for test purposes Configurable system memory options defined at integration of core into the system-on-a-chip (SoC).
3.1.2
Modes of Operation
Some of the registers operate differently depending on the mode of operation (i.e., normal expanded wide, special single chip, etc.). This is best understood from the register descriptions.
3.2
External Signal Description
All interfacing with the MMC sub-block is done within the core, it has no external signals.
3.3
Memory Map and Register Definition
A summary of the registers associated with the MMC sub-block is shown in Figure 3-2. Detailed descriptions of the registers and bits are given in the subsections that follow.
MC3S12RG128 Data Sheet, Rev. 1.05 114 Freescale Semiconductor
Chapter 3 Module Mapping Control (MMCV5) Block Description
3.3.1
Name 0x0010 INITRM 0x0011 INITRG
Register Descriptions
Bit 7 R W R W R W R W R W R W R REG_SW0 W R ROM_SW1 ROM_SW0 W R W R W = Unimplemented 0 0 0 0 0 0 0 0 PAG_SW1 PAG_SW0 0 EEP_SW1 EEP_SW0 0 RAM_SW2 RAM_SW1 RAM_SW0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 0 0 0 0 EXSTR1 3 EXSTR0 2 ROMHM 1 ROMON Bit 0 0 RAM15 0 6 RAM14 5 RAM13 4 RAM12 3 RAM11 2 0 1 0 Bit 0 RAMHAL 0
REG14 0
REG13 0
REG12 0
REG11 0
0
0
0x0012 Reserved 0x0013 MISC 0x0014 MTSTO
0
0
0
0x0017 MTST1
0x001C MEMSIZ0 0x001D MEMSIZ1
0x0030 PPAGE 0x0031 Reserved
PIX5 0
PIX4 0
PIX3 0
PIX2 0
PIX1 0
PIX0 0
Figure 3-2. MMC Register Summary
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 115
Chapter 3 Module Mapping Control (MMCV5) Block Description
3.3.1.1
Initialization of Internal RAM Position Register (INITRM)
Module Base + 0x0010 Starting address location affected by INITRG register setting.
7 6 5 4 3 2 1 0
R RAM15 W Reset 0 0 0 0 1 RAM14 RAM13 RAM12 RAM11
0
0 RAMHAL
0
0
1
= Unimplemented or Reserved
Figure 3-3. Initialization of Internal RAM Position Register (INITRM)
Read: Anytime Write: Once in normal and emulation modes, anytime in special modes NOTE Writes to this register take one cycle to go into effect. This register initializes the position of the internal RAM within the on-chip system memory map.
Table 3-1. INITRM Field Descriptions
Field Description
7:3 Internal RAM Map Position -- These bits determine the upper five bits of the base address for the system's RAM[15:11] internal RAM array. 0 RAMHAL RAM High-Align -- RAMHAL specifies the alignment of the internal RAM array. 0 Aligns the RAM to the lowest address (0x0000) of the mappable space 1 Aligns the RAM to the higher address (0xFFFF) of the mappable space
MC3S12RG128 Data Sheet, Rev. 1.05 116 Freescale Semiconductor
Chapter 3 Module Mapping Control (MMCV5) Block Description
3.3.1.2
Initialization of Internal Registers Position Register (INITRG)
Module Base + 0x0011 Starting address location affected by INITRG register setting.
7 6 5 4 3 2 1 0
R W Reset
0 REG14 0 0 REG13 0 REG12 0 REG11 0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 3-4. Initialization of Internal Registers Position Register (INITRG)
Read: Anytime Write: Once in normal and emulation modes and anytime in special modes This register initializes the position of the internal registers within the on-chip system memory map. The registers occupy either a 1K byte or 2K byte space and can be mapped to any 2K byte space within the first 32K bytes of the system's address space.
Table 3-2. INITRG Field Descriptions
Field Description
6:3 Internal Register Map Position -- These four bits in combination with the leading zero supplied by bit 7 of REG[14:11] INITRG determine the upper five bits of the base address for the system's internal registers (i.e., the minimum base address is 0x0000 and the maximum is 0x7FFF).
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 117
Chapter 3 Module Mapping Control (MMCV5) Block Description
3.3.1.3
Miscellaneous System Control Register (MISC)
Module Base + 0x0013 Starting address location affected by INITRG register setting.
7 6 5 4 3 2 1 0
R W Reset: Expanded or Emulation Reset: Peripheral or Single Chip Reset: Special Test
0
0
0
0 EXSTR1 EXSTR0 ROMHM ROMON --1 1 0
0 0 0
0 0 0
0 0 0
0 0 0
1 1 1
1 1 1
0 0 0
1. The reset state of this bit is determined at the chip integration level. = Unimplemented or Reserved
Figure 3-5. Miscellaneous System Control Register (MISC)
Read: Anytime Write: As stated in each bit description NOTE Writes to this register take one cycle to go into effect. This register initializes miscellaneous control functions.
Table 3-3. MISC Field Descriptions
Field Description
3:2 External Access Stretch Bits 1 and 0 EXSTR[1:0] Write: once in normal and emulation modes and anytime in special modes This two-bit field determines the amount of clock stretch on accesses to the external address space as shown in Table 3-4. In single chip and peripheral modes these bits have no meaning or effect. 1 ROMHM FLASH EEPROM or ROM Only in Second Half of Memory Map Write: once in normal and emulation modes and anytime in special modes 0 The fixed page(s) of FLASH EEPROM or ROM in the lower half of the memory map can be accessed. 1 Disables direct access to the FLASH EEPROM or ROM in the lower half of the memory map. These physical locations of the FLASH EEPROM or ROM remain accessible through the program page window. ROMON -- Enable FLASH EEPROM or ROM Write: once in normal and emulation modes and anytime in special modes This bit is used to enable the FLASH EEPROM or ROM memory in the memory map. 0 Disables the FLASH EEPROM or ROM from the memory map. 1 Enables the FLASH EEPROM or ROM in the memory map. Note: Removing the Mask-ROM from the memory map in a secured Mask-ROM device unsecures the device. This can be either achieved by writing a '0' to the ROMON bit or by starting up with the Mask-ROM disabled using the external ROMCTL pin. A secured Mask-ROM cannot be re-enabled once the device was unsecured using this method. Writing a '1' to the ROMON bit will not have any effect. Re-enabling a secured Mask-ROM requires a system reset. Additionally, when starting in special single chip mode, the BDM firmware in a Mask-ROM device will disable a secured ROM automatically before BDM access to the device is enabled.
0 ROMON
MC3S12RG128 Data Sheet, Rev. 1.05 118 Freescale Semiconductor
Chapter 3 Module Mapping Control (MMCV5) Block Description
Table 3-4. External Stretch Bit Definition
Stretch Bit EXSTR1 0 0 1 1 Stretch Bit EXSTR0 0 1 0 1 Number of E Clocks Stretched 0 1 2 3
3.3.1.4
Reserved Test Register 0 (MTST0)
Module Base + 0x0014 Starting address location affected by INITRG register setting.
7 6 5 4 3 2 1 0
R W Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 3-6. Reserved Test Register 0 (MTST0)
Read: Anytime Write: No effect -- this register location is used for internal test purposes.
3.3.1.5
Reserved Test Register 1 (MTST1)
Module Base + 0x0017 Starting address location affected by INITRG register setting.
7 6 5 4 3 2 1 0
R W Reset
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
= Unimplemented or Reserved
Figure 3-7. Reserved Test Register 1 (MTST1)
Read: Anytime Write: No effect -- this register location is used for internal test purposes.
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Chapter 3 Module Mapping Control (MMCV5) Block Description
3.3.1.6
Memory Size Register 0 (MEMSIZ0)
Module Base + 0x001C Starting address location affected by INITRG register setting.
7 6 5 4 3 2 1 0
R REG_SW0 W Reset --
0
EEP_SW1
EEP_SW0
0
RAM_SW2
RAM_SW1
RAM_SW0
--
--
--
--
--
--
--
= Unimplemented or Reserved
Figure 3-8. Memory Size Register 0 (MEMSIZ0)
Read: Anytime Write: Writes have no effect Reset: Defined at chip integration, see device overview section. The MEMSIZ0 register reflects the state of the register, EEPROM and RAM memory space configuration switches at the core boundary which are configured at system integration. This register allows read visibility to the state of these switches.
Table 3-5. MEMSIZ0 Field Descriptions
Field 7 REG_SW0 Description Allocated System Register Space 0 Allocated system register space size is 1K byte 1 Allocated system register space size is 2K byte
5:4 Allocated System EEPROM Memory Space -- The allocated system EEPROM memory space size is as EEP_SW[1:0] given in Table 3-6. 2 Allocated System RAM Memory Space -- The allocated system RAM memory space size is as given in RAM_SW[2:0] Table 3-7.
Table 3-6. Allocated EEPROM Memory Space
eep_sw1:eep_sw0 00 01 10 11 Allocated EEPROM Space 0K byte 2K bytes 4K bytes 8K bytes
Table 3-7. Allocated RAM Memory Space
ram_sw2:ram_sw0 000 001 010 Allocated RAM Space 2K bytes 4K bytes 6K bytes RAM Mappable Region 2K bytes 4K bytes 8K bytes2 INITRM Bits Used RAM[15:11] RAM[15:12] RAM[15:13] RAM Reset Base Address1 0x0800 0x0000 0x0800
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Chapter 3 Module Mapping Control (MMCV5) Block Description
Table 3-7. Allocated RAM Memory Space (continued)
ram_sw2:ram_sw0 011 100 101 110 111
1 2
Allocated RAM Space 8K bytes 10K bytes 12K bytes 14K bytes 16K bytes
RAM Mappable Region 8K bytes 16K bytes 16K bytes
2 2
INITRM Bits Used RAM[15:13] RAM[15:14] RAM[15:14] RAM[15:14] RAM[15:14]
RAM Reset Base Address1 0x0000 0x1800 0x1000 0x0800 0x0000
16K bytes 2 16K bytes
The RAM Reset BASE Address is based on the reset value of the INITRM register, 0x0009. Alignment of the Allocated RAM space within the RAM mappable region is dependent on the value of RAMHAL.
NOTE As stated, the bits in this register provide read visibility to the system physical memory space allocations defined at system integration. The actual array size for any given type of memory block may differ from the allocated size. Please refer to the device overview chapter for actual sizes.
3.3.1.7
Memory Size Register 1 (MEMSIZ1)
Module Base + 0x001D Starting address location affected by INITRG register setting.
7 6 5 4 3 2 1 0
R ROM_SW1 W Reset --
ROM_SW0
0
0
0
0
PAG_SW1
PAG_SW0
--
--
--
--
--
--
--
= Unimplemented or Reserved
Figure 3-9. Memory Size Register 1 (MEMSIZ1)
Read: Anytime Write: Writes have no effect Reset: Defined at chip integration, see device overview section. The MEMSIZ1 register reflects the state of the FLASH or ROM physical memory space and paging switches at the core boundary which are configured at system integration. This register allows read visibility to the state of these switches.
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Chapter 3 Module Mapping Control (MMCV5) Block Description
Table 3-8. MEMSIZ0 Field Descriptions
Field Description
7:6 Allocated System FLASH or ROM Physical Memory Space -- The allocated system FLASH or ROM ROM_SW[1:0] physical memory space is as given in Table 3-9. 1:0 Allocated Off-Chip FLASH or ROM Memory Space -- The allocated off-chip FLASH or ROM memory space PAG_SW[1:0] size is as given in Table 3-10.
Table 3-9. Allocated FLASH/ROM Physical Memory Space
rom_sw1:rom_sw0 00 01 10 11 Allocated FLASH or ROM Space 0K byte 16K bytes 48K bytes(1) 64K bytes(1)
NOTES: 1. The ROMHM software bit in the MISC register determines the accessibility of the FLASH/ROM memory space. Please refer to Section 3.3.1.7, "Memory Size Register 1 (MEMSIZ1)," for a detailed functional description of the ROMHM bit.
Table 3-10. Allocated Off-Chip Memory Options
pag_sw1:pag_sw0 00 01 10 11 Off-Chip Space 876K bytes 768K bytes 512K bytes 0K byte On-Chip Space 128K bytes 256K bytes 512K bytes 1M byte
NOTE As stated, the bits in this register provide read visibility to the system memory space and on-chip/off-chip partitioning allocations defined at system integration. The actual array size for any given type of memory block may differ from the allocated size. Please refer to the device overview chapter for actual sizes.
MC3S12RG128 Data Sheet, Rev. 1.05 122 Freescale Semiconductor
Chapter 3 Module Mapping Control (MMCV5) Block Description
3.3.1.8
Program Page Index Register (PPAGE)
Module Base + 0x0030 Starting address location affected by INITRG register setting.
7 6 5 4 3 2 1 0
R W Reset1
0
0 PIX5 PIX4 -- PIX3 -- PIX2 -- PIX1 -- PIX0 --
--
--
--
1. The reset state of this register is controlled at chip integration. Please refer to the device overview section to determine the actual reset state of this register. = Unimplemented or Reserved
Figure 3-10. Program Page Index Register (PPAGE)
Read: Anytime Write: Determined at chip integration. Generally it's: "write anytime in all modes;" on some devices it will be: "write only in special modes." Check specific device documentation to determine which applies. Reset: Defined at chip integration as either 0x00 (paired with write in any mode) or 0x3C (paired with write only in special modes), see device overview chapter. The HCS12 core architecture limits the physical address space available to 64K bytes. The program page index register allows for integrating up to 1M byte of FLASH or ROM into the system by using the six page index bits to page 16K byte blocks into the program page window located from 0x8000 to 0xBFFF as defined in Table 3-12. CALL and RTC instructions have special access to read and write this register without using the address bus. NOTE Normal writes to this register take one cycle to go into effect. Writes to this register using the special access of the CALL and RTC instructions will be complete before the end of the associated instruction.
Table 3-11. MEMSIZ0 Field Descriptions
Field 5:0 PIX[5:0] Description Program Page Index Bits 5:0 -- These page index bits are used to select which of the 64 FLASH or ROM array pages is to be accessed in the program page window as shown in Table 3-12.
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Chapter 3 Module Mapping Control (MMCV5) Block Description
Table 3-12. Program Page Index Register Bits
PIX5 0 0 0 0 . . . . . 1 1 1 1 PIX4 0 0 0 0 . . . . . 1 1 1 1 PIX3 0 0 0 0 . . . . 1 1 1 1 PIX2 0 0 0 0 . . . . . 1 1 1 1 PIX1 0 0 1 1 . . . . . 0 0 1 1 PIX0 0 1 0 1 . . . . . 0 1 0 1 Program Space Selected 16K page 0 16K page 1 16K page 2 16K page 3 . . . . . 16K page 60 16K page 61 16K page 62 16K page 63
3.4
Functional Description
The MMC sub-block performs four basic functions of the core operation: bus control, address decoding and select signal generation, memory expansion, and security decoding for the system. Each aspect is described in the following subsections.
3.4.1
Bus Control
The MMC controls the address bus and data buses that interface the core with the rest of the system. This includes the multiplexing of the input data buses to the core onto the main CPU read data bus and control of data flow from the CPU to the output address and data buses of the core. In addition, the MMC manages all CPU read data bus swapping operations.
3.4.2
Address Decoding
As data flows on the core address bus, the MMC decodes the address information, determines whether the internal core register or firmware space, the peripheral space or a memory register or array space is being addressed and generates the correct select signal. This decoding operation also interprets the mode of operation of the system and the state of the mapping control registers in order to generate the proper select. The MMC also generates two external chip select signals, emulation chip select (ECS) and external chip select (XCS).
3.4.2.1
Select Priority and Mode Considerations
Although internal resources such as control registers and on-chip memory have default addresses, each can be relocated by changing the default values in control registers. Normally, I/O addresses, control registers,
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Chapter 3 Module Mapping Control (MMCV5) Block Description
vector spaces, expansion windows, and on-chip memory are mapped so that their address ranges do not overlap. The MMC will make only one select signal active at any given time. This activation is based upon the priority outlined in Table 3-13. If two or more blocks share the same address space, only the select signal for the block with the highest priority will become active. An example of this is if the registers and the RAM are mapped to the same space, the registers will have priority over the RAM and the portion of RAM mapped in this shared space will not be accessible. The expansion windows have the lowest priority. This means that registers, vectors, and on-chip memory are always visible to a program regardless of the values in the page select registers.
Table 3-13. Select Signal Priority
Priority Highest ... ... ... ... Lowest Address Space BDM (internal to core) firmware or register space Internal register space RAM memory block EEPROM memory block On-chip FLASH or ROM Remaining external space
In expanded modes, all address space not used by internal resources is by default external memory space. The data registers and data direction registers for ports A and B are removed from the on-chip memory map and become external accesses. If the EME bit in the MODE register (see MEBI block description chapter) is set, the data and data direction registers for port E are also removed from the on-chip memory map and become external accesses. In special peripheral mode, the first 16 registers associated with bus expansion are removed from the on-chip memory map (PORTA, PORTB, DDRA, DDRB, PORTE, DDRE, PEAR, MODE, PUCR, RDRIV, and the EBI reserved registers). In emulation modes, if the EMK bit in the MODE register (see MEBI block description chapter) is set, the data and data direction registers for port K are removed from the on-chip memory map and become external accesses.
3.4.2.2
Emulation Chip Select Signal
When the EMK bit in the MODE register (see MEBI block description chapter) is set, port K bit 7 is used as an active-low emulation chip select signal, ECS. This signal is active when the system is in emulation mode, the EMK bit is set and the FLASH or ROM space is being addressed subject to the conditions outlined in Section 3.4.3.2, "Extended Address (XAB19:14) and ECS Signal Functionality." When the EMK bit is clear, this pin is used for general purpose I/O.
3.4.2.3
External Chip Select Signal
When the EMK bit in the MODE register (see MEBI block description chapter) is set, port K bit 6 is used as an active-low external chip select signal, XCS. This signal is active only when the ECS signal described above is not active and when the system is addressing the external address space. Accesses to
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Chapter 3 Module Mapping Control (MMCV5) Block Description
unimplemented locations within the register space or to locations that are removed from the map (i.e., ports A and B in expanded modes) will not cause this signal to become active. When the EMK bit is clear, this pin is used for general purpose I/O.
3.4.3
Memory Expansion
The HCS12 core architecture limits the physical address space available to 64K bytes. The program page index register allows for integrating up to 1M byte of FLASH or ROM into the system by using the six page index bits to page 16K byte blocks into the program page window located from 0x8000 to 0xBFFF in the physical memory space. The paged memory space can consist of solely on-chip memory or a combination of on-chip and off-chip memory. This partitioning is configured at system integration through the use of the paging configuration switches (pag_sw1:pag_sw0) at the core boundary. The options available to the integrator are as given in Table 3-14 (this table matches Table 3-10 but is repeated here for easy reference).
Table 3-14. Allocated Off-Chip Memory Options
pag_sw1:pag_sw0 00 01 10 11 Off-Chip Space 876K bytes 768K bytes 512K bytes 0K byte On-Chip Space 128K bytes 256K bytes 512K bytes 1M byte
Based upon the system configuration, the program page window will consider its access to be either internal or external as defined in Table 3-15.
Table 3-15. External/Internal Page Window Access
pag_sw1:pag_sw0 00 Partitioning 876K off-Chip, 128K on-Chip 768K off-chip, 256K on-chip 512K off-chip, 512K on-chip 0K off-chip, 1M on-chip PIX5:0 Value 0x0000-0x0037 0x0038-0x003F 0x0000-0x002F 0x0030-0x003F 0x0000-0x001F 0x0020-0x003F N/A 0x0000-0x003F Page Window Access External Internal External Internal External Internal External Internal
01
10
11
NOTE The partitioning as defined in Table 3-15 applies only to the allocated memory space and the actual on-chip memory sizes implemented in the system may differ. Please refer to the device overview chapter for actual sizes.
MC3S12RG128 Data Sheet, Rev. 1.05 126 Freescale Semiconductor
Chapter 3 Module Mapping Control (MMCV5) Block Description
The PPAGE register holds the page select value for the program page window. The value of the PPAGE register can be manipulated by normal read and write (some devices don't allow writes in some modes) instructions as well as the CALL and RTC instructions. Control registers, vector spaces, and a portion of on-chip memory are located in unpaged portions of the 64K byte physical address space. The stack and I/O addresses should also be in unpaged memory to make them accessible from any page. The starting address of a service routine must be located in unpaged memory because the 16-bit exception vectors cannot point to addresses in paged memory. However, a service routine can call other routines that are in paged memory. The upper 16K byte block of memory space (0xC000-0xFFFF) is unpaged. It is recommended that all reset and interrupt vectors point to locations in this area.
3.4.3.1
CALL and Return from Call Instructions
CALL and RTC are uninterruptable instructions that automate page switching in the program expansion window. CALL is similar to a JSR instruction, but the subroutine that is called can be located anywhere in the normal 64K byte address space or on any page of program expansion memory. CALL calculates and stacks a return address, stacks the current PPAGE value, and writes a new instruction-supplied value to PPAGE. The PPAGE value controls which of the 64 possible pages is visible through the 16K byte expansion window in the 64K byte memory map. Execution then begins at the address of the called subroutine. During the execution of a CALL instruction, the CPU: * Writes the old PPAGE value into an internal temporary register and writes the new instruction-supplied PPAGE value into the PPAGE register. * Calculates the address of the next instruction after the CALL instruction (the return address), and pushes this 16-bit value onto the stack. * Pushes the old PPAGE value onto the stack. * Calculates the effective address of the subroutine, refills the queue, and begins execution at the new address on the selected page of the expansion window. This sequence is uninterruptable; there is no need to inhibit interrupts during CALL execution. A CALL can be performed from any address in memory to any other address. The PPAGE value supplied by the instruction is part of the effective address. For all addressing mode variations except indexed-indirect modes, the new page value is provided by an immediate operand in the instruction. In indexed-indirect variations of CALL, a pointer specifies memory locations where the new page value and the address of the called subroutine are stored. Using indirect addressing for both the new page value and the address within the page allows values calculated at run time rather than immediate values that must be known at the time of assembly. The RTC instruction terminates subroutines invoked by a CALL instruction. RTC unstacks the PPAGE value and the return address and refills the queue. Execution resumes with the next instruction after the CALL.
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Chapter 3 Module Mapping Control (MMCV5) Block Description
During the execution of an RTC instruction, the CPU: * Pulls the old PPAGE value from the stack * Pulls the 16-bit return address from the stack and loads it into the PC * Writes the old PPAGE value into the PPAGE register * Refills the queue and resumes execution at the return address This sequence is uninterruptable; an RTC can be executed from anywhere in memory, even from a different page of extended memory in the expansion window. The CALL and RTC instructions behave like JSR and RTS, except they use more execution cycles. Therefore, routinely substituting CALL/RTC for JSR/RTS is not recommended. JSR and RTS can be used to access subroutines that are on the same page in expanded memory. However, a subroutine in expanded memory that can be called from other pages must be terminated with an RTC. And the RTC unstacks a PPAGE value. So any access to the subroutine, even from the same page, must use a CALL instruction so that the correct PPAGE value is in the stack.
3.4.3.2
Extended Address (XAB19:14) and ECS Signal Functionality
If the EMK bit in the MODE register is set (see MEBI block description chapter) the PIX5:0 values will be output on XAB19:14 respectively (port K bits 5:0) when the system is addressing within the physical program page window address space (0x8000-0xBFFF) and is in an expanded mode. When addressing anywhere else within the physical address space (outside of the paging space), the XAB19:14 signals will be assigned a constant value based upon the physical address space selected. In addition, the active-low emulation chip select signal, ECS, will likewise function based upon the assigned memory allocation. In the cases of 48K byte and 64K byte allocated physical FLASH/ROM space, the operation of the ECS signal will additionally depend upon the state of the ROMHM bit (see Section 3.3.1.3, "Miscellaneous System Control Register (MISC)") in the MISC register. Table 3-16, Table 3-17, Table 3-18, and Table 3-19 summarize the functionality of these signals based upon the allocated memory configuration. Again, this signal information is only available externally when the EMK bit is set and the system is in an expanded mode.
Table 3-16. 0K Byte Physical FLASH/ROM Allocated
Address Space 0x0000-0x3FFF 0x4000-0x7FFF 0x8000-0xBFFF 0xC000-0xFFFF Page Window Access N/A N/A N/A N/A ROMHM N/A N/A N/A N/A ECS 1 1 0 0 XAB19:14 0x3D 0x3E PIX[5:0] 0x3F
Table 3-17. 16K Byte Physical FLASH/ROM Allocated
Address Space 0x0000-0x3FFF 0x4000-0x7FFF 0x8000-0xBFFF 0xC000-0xFFFF Page Window Access N/A N/A N/A N/A ROMHM N/A N/A N/A N/A ECS 1 1 1 0 XAB19:14 0x3D 0x3E PIX[5:0] 0x3F
MC3S12RG128 Data Sheet, Rev. 1.05 128 Freescale Semiconductor
Chapter 3 Module Mapping Control (MMCV5) Block Description
Table 3-18. 48K Byte Physical FLASH/ROM Allocated
Address Space 0x0000-0x3FFF 0x4000-0x7FFF 0x8000-0xBFFF 0xC000-0xFFFF Page Window Access N/A N/A N/A External Internal N/A ROMHM N/A 0 1 N/A N/A N/A ECS 1 0 1 1 0 0 0x3F PIX[5:0] XAB19:14 0x3D 0x3E
Table 3-19. 64K Byte Physical FLASH/ROM Allocated
Address Space 0x0000-0x3FFF 0x4000-0x7FFF 0x8000-0xBFFF 0xC000-0xFFFF Page Window Access N/A N/A N/A N/A External Internal N/A ROMHM 0 1 0 1 N/A N/A N/A ECS 0 1 0 1 1 0 0 0x3F PIX[5:0] 0x3E XAB19:14 0x3D
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Chapter 3 Module Mapping Control (MMCV5) Block Description
A graphical example of a memory paging for a system configured as 1M byte on-chip FLASH/ROM with 64K allocated physical space is given in Figure 3-11.
0x0000 61
16K FLASH (UNPAGED)
0x4000
62
16K FLASH (UNPAGED) ONE 16K FLASH/ROM PAGE ACCESSIBLE AT A TIME (SELECTED BY PPAGE = 0 TO 63) 0x8000 0 1 2 3 59 60 61 62 63
16K FLASH (PAGED)
0xC000 63 These 16K FLASH/ROM pages accessible from 0x0000 to 0x7FFF if selected by the ROMHM bit in the MISC register. 16K FLASH (UNPAGED)
0xFF00 0xFFFF VECTORS NORMAL SINGLE CHIP
Figure 3-11. Memory Paging Example: 1M Byte On-Chip FLASH/ROM, 64K Allocation
MC3S12RG128 Data Sheet, Rev. 1.05 130 Freescale Semiconductor
Chapter 4 Multiplexed External Bus Interface (MEBIV3) Block Description
4.1 Introduction
This section describes the functionality of the multiplexed external bus interface (MEBI) sub-block of the S12 core platform. The functionality of the module is closely coupled with the S12 CPU and the memory map controller (MMC) sub-blocks. Figure 4-1 is a block diagram of the MEBI. In Figure 4-1, the signals on the right hand side represent pins that are accessible externally. On some chips, these may not all be bonded out. The MEBI sub-block of the core serves to provide access and/or visibility to internal core data manipulation operations including timing reference information at the external boundary of the core and/or system. Depending upon the system operating mode and the state of bits within the control registers of the MEBI, the internal 16-bit read and write data operations will be represented in 8-bit or 16-bit accesses externally. Using control information from other blocks within the system, the MEBI will determine the appropriate type of data access to be generated.
4.1.1
Features
The block name includes these distinctive features: * External bus controller with four 8-bit ports A,B, E, and K * Data and data direction registers for ports A, B, E, and K when used as general-purpose I/O * Control register to enable/disable alternate functions on ports E and K * Mode control register * Control register to enable/disable pull-ups on ports A, B, E, and K * Control register to enable/disable reduced output drive on ports A, B, E, and K * Control register to configure external clock behavior * Control register to configure IRQ pin operation * Logic to capture and synchronize external interrupt pin inputs
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Chapter 4 Multiplexed External Bus Interface (MEBIV3) Block Description
REGS
Port K
ADDR
PK[7:0]/ECS/XCS/X[19:14]
Internal Bus
Data[15:0]
EXT BUS I/F CTL
ADDR DATA
Port A
Addr[19:0]
PA[7:0]/A[15:8]/ D[15:8]/D[7:0]
(Control)
Port B
ADDR
PB[7:0]/A[7:0]/ D[7:0]
DATA
PE[7:2]/NOACC/ IPIPE1/MODB/CLKTO IPIPE0/MODA/ ECLK/ LSTRB/TAGLO R/W PE1/IRQ PE0/XIRQ
ECLK CTL
CPU pipe info IRQ interrupt XIRQ interrupt
PIPE CTL IRQ CTL TAG CTL
mode
BDM tag info
Port E
BKGD
BKGD/MODC/TAGHI
Control signal(s) Data signal (unidirectional) Data signal (bidirectional) Data bus (unidirectional) Data bus (bidirectional)
Figure 4-1. MEBI Block Diagram
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Chapter 4 Multiplexed External Bus Interface (MEBIV3) Block Description
4.1.2
*
Modes of Operation
Normal expanded wide mode Ports A and B are configured as a 16-bit multiplexed address and data bus and port E provides bus control and status signals. This mode allows 16-bit external memory and peripheral devices to be interfaced to the system. Normal expanded narrow mode Ports A and B are configured as a 16-bit address bus and port A is multiplexed with 8-bit data. Port E provides bus control and status signals. This mode allows 8-bit external memory and peripheral devices to be interfaced to the system. Normal single-chip mode There is no external expansion bus in this mode. The processor program is executed from internal memory. Ports A, B, K, and most of E are available as general-purpose I/O. Special single-chip mode This mode is generally used for debugging single-chip operation, boot-strapping, or security related operations. The active background mode is in control of CPU execution and BDM firmware is waiting for additional serial commands through the BKGD pin. There is no external expansion bus after reset in this mode. Emulation expanded wide mode Developers use this mode for emulation systems in which the users target application is normal expanded wide mode. Emulation expanded narrow mode Developers use this mode for emulation systems in which the users target application is normal expanded narrow mode. Special test mode Ports A and B are configured as a 16-bit multiplexed address and data bus and port E provides bus control and status signals. In special test mode, the write protection of many control bits is lifted so that they can be thoroughly tested without needing to go through reset. Special peripheral mode This mode is intended for Freescale Semiconductor factory testing of the system. The CPU is inactive and an external (tester) bus master drives address, data, and bus control signals.
*
*
*
*
*
*
*
4.2
External Signal Description
In typical implementations, the MEBI sub-block of the core interfaces directly with external system pins. Some pins may not be bonded out in all implementations. Table 4-1 outlines the pin names and functions and gives a brief description of their operation reset state of these pins and associated pull-ups or pull-downs is dependent on the mode of operation and on the integration of this block at the chip level (chip dependent).
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Chapter 4 Multiplexed External Bus Interface (MEBIV3) Block Description
.
Table 4-1. External System Pins Associated With MEBI
Pin Name Pin Functions MODC BKGD TAGHI Description At the rising edge on RESET, the state of this pin is registered into the MODC bit to set the mode. (This pin always has an internal pullup.) Pseudo open-drain communication pin for the single-wire background debug mode. There is an internal pull-up resistor on this pin. When instruction tagging is on, a 0 at the falling edge of E tags the high half of the instruction word being read into the instruction queue. General-purpose I/O pins, see PORTA and DDRA registers. High-order address lines multiplexed during ECLK low. Outputs except in special peripheral mode where they are inputs from an external tester system. High-order bidirectional data lines multiplexed during ECLK high in expanded wide modes, special peripheral mode, and visible internal accesses (IVIS = 1) in emulation expanded narrow mode. Direction of data transfer is generally indicated by R/W. Alternate high-order and low-order bytes of the bidirectional data lines multiplexed during ECLK high in expanded narrow modes and narrow accesses in wide modes. Direction of data transfer is generally indicated by R/W. General-purpose I/O pins, see PORTB and DDRB registers. Low-order address lines multiplexed during ECLK low. Outputs except in special peripheral mode where they are inputs from an external tester system. Low-order bidirectional data lines multiplexed during ECLK high in expanded wide modes, special peripheral mode, and visible internal accesses (with IVIS = 1) in emulation expanded narrow mode. Direction of data transfer is generally indicated by R/W. General-purpose I/O pin, see PORTE and DDRE registers. CPU No Access output. Indicates whether the current cycle is a free cycle. Only available in expanded modes. At the rising edge of RESET, the state of this pin is registered into the MODB bit to set the mode. General-purpose I/O pin, see PORTE and DDRE registers. Instruction pipe status bit 1, enabled by PIPOE bit in PEAR. System clock test output. Only available in special modes. PIPOE = 1 overrides this function. The enable for this function is in the clock module. At the rising edge on RESET, the state of this pin is registered into the MODA bit to set the mode. General-purpose I/O pin, see PORTE and DDRE registers. Instruction pipe status bit 0, enabled by PIPOE bit in PEAR.
BKGD/MODC/ TAGHI
PA7/A15/D15/D7 thru PA0/A8/D8/D0
PA7-PA0 A15-A8 D15-D8
D15/D7 thru D8/D0 PB7/A7/D7 thru PB0/A0/D0 PB7-PB0 A7-A0 D7-D0
PE7/NOACC
PE7 NOACC
PE6/IPIPE1/ MODB/CLKTO
MODB PE6 IPIPE1 CLKTO
PE5/IPIPE0/MODA
MODA PE5 IPIPE0
MC3S12RG128 Data Sheet, Rev. 1.05 134 Freescale Semiconductor
Chapter 4 Multiplexed External Bus Interface (MEBIV3) Block Description
Table 4-1. External System Pins Associated With MEBI (continued)
Pin Name PE4/ECLK Pin Functions PE4 ECLK Description General-purpose I/O pin, see PORTE and DDRE registers. Bus timing reference clock, can operate as a free-running clock at the system clock rate or to produce one low-high clock per visible access, with the high period stretched for slow accesses. ECLK is controlled by the NECLK bit in PEAR, the IVIS bit in MODE, and the ESTR bit in EBICTL. General-purpose I/O pin, see PORTE and DDRE registers. Low strobe bar, 0 indicates valid data on D7-D0. In special peripheral mode, this pin is an input indicating the size of the data transfer (0 = 16-bit; 1 = 8-bit). In expanded wide mode or emulation narrow modes, when instruction tagging is on and low strobe is enabled, a 0 at the falling edge of E tags the low half of the instruction word being read into the instruction queue. General-purpose I/O pin, see PORTE and DDRE registers. Read/write, indicates the direction of internal data transfers. This is an output except in special peripheral mode where it is an input. General-purpose input-only pin, can be read even if IRQ enabled. Maskable interrupt request, can be level sensitive or edge sensitive. General-purpose input-only pin. Non-maskable interrupt input. General-purpose I/O pin, see PORTK and DDRK registers. Emulation chip select General-purpose I/O pin, see PORTK and DDRK registers. External data chip select General-purpose I/O pins, see PORTK and DDRK registers. Memory expansion addresses
PE3/LSTRB/ TAGLO
PE3 LSTRB SZ8 TAGLO
PE2/R/W
PE2 R/W
PE1/IRQ
PE1 IRQ
PE0/XIRQ
PE0 XIRQ
PK7/ECS
PK7 ECS
PK6/XCS
PK6 XCS
PK5/X19 thru PK0/X14
PK5-PK0 X19-X14
Detailed descriptions of these pins can be found in the device overview chapter.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 135
Chapter 4 Multiplexed External Bus Interface (MEBIV3) Block Description
4.3
Memory Map and Register Definition
A summary of the registers associated with the MEBI sub-block is shown in Figure 4-2. Detailed descriptions of the registers and bits are given in the subsections that follow. On most chips the registers are mappable. Therefore, the upper bits may not be all 0s as shown in the table and descriptions.
4.3.1
Name 0x0000 PORTA 0x0001 PORTB 0x0002 DDRA 0x0003 DDRB
Module Memory Map
Bit 7 R W R W R W R W R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 7 6 6 5 5 4 4 3 3 2 2 1 1 Bit 0 Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7 0
6 0
5 0
4 0
3 0
2 0
1 0
Bit 0 0
0x0004 Reserved 0x0005 Reserved 0x0006 Reserved 0x0007 Reserved 0x0008 PORTE 0x0009 DDRE 0x000A PEAR 0x000B MODE 0x000C PUCR
Bit 7
6 0
5
4
3
2
0
0
NOACCE
PIPOE
NECLK 0
LSTRE
RDWE 0
0
0
MODC
MODB 0
MODA 0
IVIS 0
EMK
EME
PUPKE
PUPEE
0
PUPBE
PUPAE
Figure 4-2. MEBI Register Summary
MC3S12RG128 Data Sheet, Rev. 1.05 136 Freescale Semiconductor
Chapter 4 Multiplexed External Bus Interface (MEBIV3) Block Description
Name 0x000D RDRIV 0x000E EBICTL 0x000F Reserved 0x001E IRQCR 0x0032 PORTK 0x0033 DDRK R W R W R W R W R W R W
Bit 7 RDPK 0
6 0
5 0
4 RDPE 0
3 0
2 0
1 RDPB 0
Bit 0 RDPA
0
0
0
0
ESTR 0
0
0
0
0
0
0
0
IRQE
IRQEN
0
0
0
0
0
0
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
= Unimplemented or Reserved
Figure 4-2. MEBI Register Summary (continued)
4.3.2
4.3.2.1
Register Descriptions
Port A Data Register (PORTA)
Module Base + 0x0000 Starting address location affected by INITRG register setting.
7 6 5 4 3 2 1 0
R Bit 7 W Reset Single Chip 0 PA7 0 PA6 AB/DB14 0 PA5 AB/DB13 0 PA4 AB/DB12 0 PA3 AB/DB11 0 PA2 AB/DB10 0 PA1 AB/DB9 AB9 and DB9/DB1 0 PA0 AB/DB8 AB8 and DB8/DB0 6 5 4 3 2 1 Bit 0
Expanded Wide, Emulation Narrow with AB/DB15 IVIS, and Peripheral
Expanded Narrow AB15 and AB14 and AB13 and AB12 and AB11 and AB10 and DB15/DB7 DB14/DB6 DB13/DB5 DB12/DB4 DB11/DB3 DB10/DB2
Figure 4-3. Port A Data Register (PORTA)
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 137
Chapter 4 Multiplexed External Bus Interface (MEBIV3) Block Description
Read: Anytime when register is in the map Write: Anytime when register is in the map Port A bits 7 through 0 are associated with address lines A15 through A8 respectively and data lines D15/D7 through D8/D0 respectively. When this port is not used for external addresses such as in single-chip mode, these pins can be used as general-purpose I/O. Data direction register A (DDRA) determines the primary direction of each pin. DDRA also determines the source of data for a read of PORTA. This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these accesses will be echoed externally. NOTE To ensure that you read the value present on the PORTA pins, always wait at least one cycle after writing to the DDRA register before reading from the PORTA register.
4.3.2.2
Port B Data Register (PORTB)
Module Base + 0x0001 Starting address location affected by INITRG register setting.
7 6 5 4 3 2 1 0
R Bit 7 W Reset Single Chip Expanded Wide, Emulation Narrow with IVIS, and Peripheral Expanded Narrow 0 PB7 AB/DB7 AB7 0 PB6 AB/DB6 AB6 0 PB5 AB/DB5 AB5 0 PB4 AB/DB4 AB4 0 PB3 AB/DB3 AB3 0 PB2 AB/DB2 AB2 0 PB1 AB/DB1 AB1 0 PB0 AB/DB0 AB0 6 5 4 3 2 1 Bit 0
Figure 4-4. Port A Data Register (PORTB)
Read: Anytime when register is in the map Write: Anytime when register is in the map Port B bits 7 through 0 are associated with address lines A7 through A0 respectively and data lines D7 through D0 respectively. When this port is not used for external addresses, such as in single-chip mode, these pins can be used as general-purpose I/O. Data direction register B (DDRB) determines the primary direction of each pin. DDRB also determines the source of data for a read of PORTB. This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these accesses will be echoed externally.
MC3S12RG128 Data Sheet, Rev. 1.05 138 Freescale Semiconductor
Chapter 4 Multiplexed External Bus Interface (MEBIV3) Block Description
NOTE To ensure that you read the value present on the PORTB pins, always wait at least one cycle after writing to the DDRB register before reading from the PORTB register.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 139
Chapter 4 Multiplexed External Bus Interface (MEBIV3) Block Description
4.3.2.3
Data Direction Register A (DDRA)
Module Base + 0x0002 Starting address location affected by INITRG register setting.
7 6 5 4 3 2 1 0
R Bit 7 W Reset 0 0 0 0 0 0 0 0 6 5 4 3 2 1 Bit 0
Figure 4-5. Data Direction Register A (DDRA)
Read: Anytime when register is in the map Write: Anytime when register is in the map This register controls the data direction for port A. When port A is operating as a general-purpose I/O port, DDRA determines the primary direction for each port A pin. A 1 causes the associated port pin to be an output and a 0 causes the associated pin to be a high-impedance input. The value in a DDR bit also affects the source of data for reads of the corresponding PORTA register. If the DDR bit is 0 (input) the buffered pin input state is read. If the DDR bit is 1 (output) the associated port data register bit state is read. This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these accesses will be echoed externally. It is reset to 0x00 so the DDR does not override the three-state control signals.
Table 4-2. DDRA Field Descriptions
Field 7:0 DDRA Description Data Direction Port A 0 Configure the corresponding I/O pin as an input 1 Configure the corresponding I/O pin as an output
MC3S12RG128 Data Sheet, Rev. 1.05 140 Freescale Semiconductor
Chapter 4 Multiplexed External Bus Interface (MEBIV3) Block Description
4.3.2.4
Data Direction Register B (DDRB)
Module Base + 0x0003 Starting address location affected by INITRG register setting.
7 6 5 4 3 2 1 0
R Bit 7 W Reset 0 0 0 0 0 0 0 0 6 5 4 3 2 1 Bit 0
Figure 4-6. Data Direction Register B (DDRB)
Read: Anytime when register is in the map Write: Anytime when register is in the map This register controls the data direction for port B. When port B is operating as a general-purpose I/O port, DDRB determines the primary direction for each port B pin. A 1 causes the associated port pin to be an output and a 0 causes the associated pin to be a high-impedance input. The value in a DDR bit also affects the source of data for reads of the corresponding PORTB register. If the DDR bit is 0 (input) the buffered pin input state is read. If the DDR bit is 1 (output) the associated port data register bit state is read. This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these accesses will be echoed externally. It is reset to 0x00 so the DDR does not override the three-state control signals.
Table 4-3. DDRB Field Descriptions
Field 7:0 DDRB Description Data Direction Port B 0 Configure the corresponding I/O pin as an input 1 Configure the corresponding I/O pin as an output
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 141
Chapter 4 Multiplexed External Bus Interface (MEBIV3) Block Description
4.3.2.5
Reserved Registers
Module Base + 0x0004 Starting address location affected by INITRG register setting.
7 6 5 4 3 2 1 0
R W Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 4-7. Reserved Register
Module Base + 0x0005 Starting address location affected by INITRG register setting.
7 6 5 4 3 2 1 0
R W Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 4-8. Reserved Register
Module Base + 0x0006 Starting address location affected by INITRG register setting.
7 6 5 4 3 2 1 0
R W Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 4-9. Reserved Register
Module Base + 0x0007 Starting address location affected by INITRG register setting.
7 6 5 4 3 2 1 0
R W Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 4-10. Reserved Register
MC3S12RG128 Data Sheet, Rev. 1.05 142 Freescale Semiconductor
Chapter 4 Multiplexed External Bus Interface (MEBIV3) Block Description
These register locations are not used (reserved). All unused registers and bits in this block return logic 0s when read. Writes to these registers have no effect. These registers are not in the on-chip map in special peripheral mode.
4.3.2.6
Port E Data Register (PORTE)
Module Base + 0x0008 Starting address location affected by INITRG register setting.
7 6 5 4 3 2 1 0
R Bit 7 W Reset Alternate Pin Function 0 NOACC 0 MODB or IPIPE1 or CLKTO 0 MODA or IPIPE0 0 ECLK 0 LSTRB or TAGLO 0 R/W 6 5 4 3 2
Bit 1
Bit 0
u IRQ
u XIRQ
= Unimplemented or Reserved
u = Unaffected by reset
Figure 4-11. Port E Data Register (PORTE)
Read: Anytime when register is in the map Write: Anytime when register is in the map Port E is associated with external bus control signals and interrupt inputs. These include mode select (MODB/IPIPE1, MODA/IPIPE0), E clock, size (LSTRB/TAGLO), read/write (R/W), IRQ, and XIRQ. When not used for one of these specific functions, port E pins 7:2 can be used as general-purpose I/O and pins 1:0 can be used as general-purpose input. The port E assignment register (PEAR) selects the function of each pin and DDRE determines whether each pin is an input or output when it is configured to be general-purpose I/O. DDRE also determines the source of data for a read of PORTE. Some of these pins have software selectable pull-ups (PE7, ECLK, LSTRB, R/W, IRQ, and XIRQ). A single control bit enables the pull-ups for all of these pins when they are configured as inputs. This register is not in the on-chip map in special peripheral mode or in expanded modes when the EME bit is set. Therefore, these accesses will be echoed externally. NOTE It is unwise to write PORTE and DDRE as a word access. If you are changing port E pins from being inputs to outputs, the data may have extra transitions during the write. It is best to initialize PORTE before enabling as outputs. NOTE To ensure that you read the value present on the PORTE pins, always wait at least one cycle after writing to the DDRE register before reading from the PORTE register.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 143
Chapter 4 Multiplexed External Bus Interface (MEBIV3) Block Description
4.3.2.7
Data Direction Register E (DDRE)
Module Base + 0x0009 Starting address location affected by INITRG register setting.
7 6 5 4 3 2 1 0
R Bit 7 W Reset 0 0 0 0 0 0 6 5 4 3 Bit 2
0
0
0
0
= Unimplemented or Reserved
Figure 4-12. Data Direction Register E (DDRE)
Read: Anytime when register is in the map Write: Anytime when register is in the map Data direction register E is associated with port E. For bits in port E that are configured as general-purpose I/O lines, DDRE determines the primary direction of each of these pins. A 1 causes the associated bit to be an output and a 0 causes the associated bit to be an input. Port E bit 1 (associated with IRQ) and bit 0 (associated with XIRQ) cannot be configured as outputs. Port E, bits 1 and 0, can be read regardless of whether the alternate interrupt function is enabled. The value in a DDR bit also affects the source of data for reads of the corresponding PORTE register. If the DDR bit is 0 (input) the buffered pin input state is read. If the DDR bit is 1 (output) the associated port data register bit state is read. This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these accesses will be echoed externally. Also, it is not in the map in expanded modes while the EME control bit is set.
Table 4-4. DDRE Field Descriptions
Field 7:2 DDRE Description Data Direction Port E 0 Configure the corresponding I/O pin as an input 1 Configure the corresponding I/O pin as an output Note: It is unwise to write PORTE and DDRE as a word access. If you are changing port E pins from inputs to outputs, the data may have extra transitions during the write. It is best to initialize PORTE before enabling as outputs.
MC3S12RG128 Data Sheet, Rev. 1.05 144 Freescale Semiconductor
Chapter 4 Multiplexed External Bus Interface (MEBIV3) Block Description
4.3.2.8
Port E Assignment Register (PEAR)
Module Base + 0x000A Starting address location affected by INITRG register setting.
7 6 5 4 3 2 1 0
R NOACCE W Reset Special Single Chip Special Test Peripheral Emulation Expanded Narrow Emulation Expanded Wide Normal Single Chip Normal Expanded Narrow Normal Expanded Wide 0 0 0 1 1 0 0 0
0 PIPOE NECLK LSTRE RDWE
0
0
0 0 0 0 0 0 0 0
0 1 0 1 1 0 0 0
0 0 0 0 0 1 0 0
0 1 0 1 1 0 0 0
0 1 0 1 1 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 4-13. Port E Assignment Register (PEAR)
Read: Anytime (provided this register is in the map). Write: Each bit has specific write conditions. Please refer to the descriptions of each bit on the following pages. Port E serves as general-purpose I/O or as system and bus control signals. The PEAR register is used to choose between the general-purpose I/O function and the alternate control functions. When an alternate control function is selected, the associated DDRE bits are overridden. The reset condition of this register depends on the mode of operation because bus control signals are needed immediately after reset in some modes. In normal single-chip mode, no external bus control signals are needed so all of port E is configured for general-purpose I/O. In normal expanded modes, only the E clock is configured for its alternate bus control function and the other bits of port E are configured for general-purpose I/O. As the reset vector is located in external memory, the E clock is required for this access. R/W is only needed by the system when there are external writable resources. If the normal expanded system needs any other bus control signals, PEAR would need to be written before any access that needed the additional signals. In special test and emulation modes, IPIPE1, IPIPE0, E, LSTRB, and R/W are configured out of reset as bus control signals. This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these accesses will be echoed externally.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 145
Chapter 4 Multiplexed External Bus Interface (MEBIV3) Block Description
Table 4-5. PEAR Field Descriptions
Field 7 NOACCE Description CPU No Access Output Enable Normal: write once Emulation: write never Special: write anytime 1 The associated pin (port E, bit 7) is general-purpose I/O. 0 The associated pin (port E, bit 7) is output and indicates whether the cycle is a CPU free cycle. This bit has no effect in single-chip or special peripheral modes. Pipe Status Signal Output Enable Normal: write once Emulation: write never Special: write anytime. 0 The associated pins (port E, bits 6:5) are general-purpose I/O. 1 The associated pins (port E, bits 6:5) are outputs and indicate the state of the instruction queue This bit has no effect in single-chip or special peripheral modes. No External E Clock Normal and special: write anytime Emulation: write never 0 The associated pin (port E, bit 4) is the external E clock pin. External E clock is free-running if ESTR = 0 1 The associated pin (port E, bit 4) is a general-purpose I/O pin. External E clock is available as an output in all modes. Low Strobe (LSTRB) Enable Normal: write once Emulation: write never Special: write anytime. 0 The associated pin (port E, bit 3) is a general-purpose I/O pin. 1 The associated pin (port E, bit 3) is configured as the LSTRB bus control output. If BDM tagging is enabled, TAGLO is multiplexed in on the rising edge of ECLK and LSTRB is driven out on the falling edge of ECLK. This bit has no effect in single-chip, peripheral, or normal expanded narrow modes. Note: LSTRB is used during external writes. After reset in normal expanded mode, LSTRB is disabled to provide an extra I/O pin. If LSTRB is needed, it should be enabled before any external writes. External reads do not normally need LSTRB because all 16 data bits can be driven even if the system only needs 8 bits of data. Read/Write Enable Normal: write once Emulation: write never Special: write anytime 0 The associated pin (port E, bit 2) is a general-purpose I/O pin. 1 The associated pin (port E, bit 2) is configured as the R/W pin This bit has no effect in single-chip or special peripheral modes. Note: R/W is used for external writes. After reset in normal expanded mode, R/W is disabled to provide an extra I/O pin. If R/W is needed it should be enabled before any external writes.
5 PIPOE
4 NECLK
3 LSTRE
2 RDWE
MC3S12RG128 Data Sheet, Rev. 1.05 146 Freescale Semiconductor
Chapter 4 Multiplexed External Bus Interface (MEBIV3) Block Description
4.3.2.9
Mode Register (MODE)
Module Base + 0x000B Starting address location affected by INITRG register setting.
7 6 5 4 3 2 1 0
R MODC W Reset Special Single Chip Emulation Expanded Narrow Special Test Emulation Expanded Wide Normal Single Chip Normal Expanded Narrow Peripheral Normal Expanded Wide 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 MODB MODA
0 IVIS
0 EMK EME
0 0 0 0 0 0 0 0
0 1 1 1 0 0 0 0
0 0 0 0 0 0 0 0
0 1 0 1 0 0 0 0
0 1 0 1 0 0 0 0
= Unimplemented or Reserved
Figure 4-14. Mode Register (MODE)
Read: Anytime (provided this register is in the map). Write: Each bit has specific write conditions. Please refer to the descriptions of each bit on the following pages. The MODE register is used to establish the operating mode and other miscellaneous functions (i.e., internal visibility and emulation of port E and K). In special peripheral mode, this register is not accessible but it is reset as shown to system configuration features. Changes to bits in the MODE register are delayed one cycle after the write. This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these accesses will be echoed externally.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 147
Chapter 4 Multiplexed External Bus Interface (MEBIV3) Block Description
Table 4-6. MODE Field Descriptions
Field 7:5 MOD[C:A] Description Mode Select Bits -- These bits indicate the current operating mode. If MODA = 1, then MODC, MODB, and MODA are write never. If MODC = MODA = 0, then MODC, MODB, and MODA are writable with the exception that you cannot change to or from special peripheral mode If MODC = 1, MODB = 0, and MODA = 0, then MODC is write never. MODB and MODA are write once, except that you cannot change to special peripheral mode. From normal single-chip, only normal expanded narrow and normal expanded wide modes are available. See Table 4-7 and Table 4-15. 3 IVIS Internal Visibility (for both read and write accesses) -- This bit determines whether internal accesses generate a bus cycle that is visible on the external bus. Normal: write once Emulation: write never Special: write anytime 0 No visibility of internal bus operations on external bus. 1 Internal bus operations are visible on external bus. Emulate Port K Normal: write once Emulation: write never Special: write anytime 0 PORTK and DDRK are in the memory map so port K can be used for general-purpose I/O. 1 If in any expanded mode, PORTK and DDRK are removed from the memory map. In single-chip modes, PORTK and DDRK are always in the map regardless of the state of this bit. In special peripheral mode, PORTK and DDRK are never in the map regardless of the state of this bit. Emulate Port E Normal and Emulation: write never Special: write anytime 0 PORTE and DDRE are in the memory map so port E can be used for general-purpose I/O. 1 If in any expanded mode or special peripheral mode, PORTE and DDRE are removed from the memory map. Removing the registers from the map allows the user to emulate the function of these registers externally. In single-chip modes, PORTE and DDRE are always in the map regardless of the state of this bit.
1 EMK
0 EME
MC3S12RG128 Data Sheet, Rev. 1.05 148 Freescale Semiconductor
Chapter 4 Multiplexed External Bus Interface (MEBIV3) Block Description
Table 4-7. MODC, MODB, and MODA Write Capability1
MODC 0 0 0 0 1 MODB 0 0 1 1 0 MODA 0 1 0 1 0 Mode Special single chip Emulation narrow Special test Emulation wide Normal single chip MODx Write Capability MODC, MODB, and MODA write anytime but not to 1102 No write MODC, MODB, and MODA write anytime but not to 110(2) No write MODC write never, MODB and MODA write once but not to 110 No write No write No write
1 1 1
1 2
0 1 1
1 0 1
Normal expanded narrow Special peripheral Normal expanded wide
No writes to the MOD bits are allowed while operating in a secure mode. For more details, refer to the device overview chapter. If you are in a special single-chip or special test mode and you write to this register, changing to normal single-chip mode, then one allowed write to this register remains. If you write to normal expanded or emulation mode, then no writes remain.
4.3.2.10
Pull-Up Control Register (PUCR)
Module Base + 0x000C Starting address location affected by INITRG register setting.
7 6 5 4 3 2 1 0
R PUPKE W Reset1 1
0
0 PUPEE
0
0 PUPBE PUPAE 0
0
0
1
0
0
0
NOTES: 1. The default value of this parameter is shown. Please refer to the device overview chapter to determine the actual reset state of this register. = Unimplemented or Reserved
Figure 4-15. Pullup Control Register (PUCR)
Read: Anytime (provided this register is in the map). Write: Anytime (provided this register is in the map). This register is used to select pull resistors for the pins associated with the core ports. Pull resistors are assigned on a per-port basis and apply to any pin in the corresponding port that is currently configured as an input. The polarity of these pull resistors is determined by chip integration. Please refer to the device overview chapter to determine the polarity of these resistors.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 149
Chapter 4 Multiplexed External Bus Interface (MEBIV3) Block Description
This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these accesses will be echoed externally. NOTE These bits have no effect when the associated pin(s) are outputs. (The pull resistors are inactive.)
Table 4-8. PUCR Field Descriptions
Field 7 PUPKE 4 PUPEE Pull-Up Port K Enable 0 Port K pull resistors are disabled. 1 Enable pull resistors for port K input pins. Pull-Up Port E Enable 0 Port E pull resistors on bits 7, 4:0 are disabled. 1 Enable pull resistors for port E input pins bits 7, 4:0. Note: Pins 5 and 6 of port E have pull resistors which are only enabled during reset. This bit has no effect on these pins. Pull-Up Port B Enable 0 Port B pull resistors are disabled. 1 Enable pull resistors for all port B input pins. Pull-Up Port A Enable 0 Port A pull resistors are disabled. 1 Enable pull resistors for all port A input pins. Description
1 PUPBE 0 PUPAE
4.3.2.11
Reduced Drive Register (RDRIV)
Module Base + 0x000D Starting address location affected by INITRG register setting.
7 6 5 4 3 2 1 0
R RDRK W Reset 0
0
0 RDPE
0
0 RDPB RDPA 0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 4-16. Reduced Drive Register (RDRIV)
Read: Anytime (provided this register is in the map) Write: Anytime (provided this register is in the map) This register is used to select reduced drive for the pins associated with the core ports. This gives reduced power consumption and reduced RFI with a slight increase in transition time (depending on loading). This feature would be used on ports which have a light loading. The reduced drive function is independent of which function is being used on a particular port. This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these accesses will be echoed externally.
MC3S12RG128 Data Sheet, Rev. 1.05 150 Freescale Semiconductor
Chapter 4 Multiplexed External Bus Interface (MEBIV3) Block Description
Table 4-9. RDRIV Field Descriptions
Field 7 RDRK 4 RDPE 1 RDPB 0 RDPA Description Reduced Drive of Port K 0 All port K output pins have full drive enabled. 1 All port K output pins have reduced drive enabled. Reduced Drive of Port E 0 All port E output pins have full drive enabled. 1 All port E output pins have reduced drive enabled. Reduced Drive of Port B 0 All port B output pins have full drive enabled. 1 All port B output pins have reduced drive enabled. Reduced Drive of Ports A 0 All port A output pins have full drive enabled. 1 All port A output pins have reduced drive enabled.
4.3.2.12
External Bus Interface Control Register (EBICTL)
Module Base + 0x000E Starting address location affected by INITRG register setting.
7 6 5 4 3 2 1 0
R W Reset: Peripheral All other modes
0
0
0
0
0
0
0 ESTR
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 1
= Unimplemented or Reserved
Figure 4-17. External Bus Interface Control Register (EBICTL)
Read: Anytime (provided this register is in the map) Write: Refer to individual bit descriptions below The EBICTL register is used to control miscellaneous functions (i.e., stretching of external E clock). This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these accesses will be echoed externally.
Table 4-10. EBICTL Field Descriptions
Field 0 ESTR Description E Clock Stretches -- This control bit determines whether the E clock behaves as a simple free-running clock or as a bus control signal that is active only for external bus cycles. Normal and Emulation: write once Special: write anytime 0 E never stretches (always free running). 1 E stretches high during stretched external accesses and remains low during non-visible internal accesses. This bit has no effect in single-chip modes.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 151
Chapter 4 Multiplexed External Bus Interface (MEBIV3) Block Description
4.3.2.13
Reserved Register
Module Base + 0x000F Starting address location affected by INITRG register setting.
7 6 5 4 3 2 1 0
R W Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 4-18. Reserved Register
This register location is not used (reserved). All bits in this register return logic 0s when read. Writes to this register have no effect. This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these accesses will be echoed externally.
4.3.2.14
IRQ Control Register (IRQCR)
Module Base + 0x001E Starting address location affected by INITRG register setting.
7 6 5 4 3 2 1 0
R IRQE W Reset 0 1 IRQEN
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 4-19. IRQ Control Register (IRQCR)
Read: See individual bit descriptions below Write: See individual bit descriptions below
Table 4-11. IRQCR Field Descriptions
Field 7 IRQE Description IRQ Select Edge Sensitive Only Special modes: read or write anytime Normal and Emulation modes: read anytime, write once 0 IRQ configured for low level recognition. 1 IRQ configured to respond only to falling edges. Falling edges on the IRQ pin will be detected anytime IRQE = 1 and will be cleared only upon a reset or the servicing of the IRQ interrupt. External IRQ Enable Normal, emulation, and special modes: read or write anytime 0 External IRQ pin is disconnected from interrupt logic. 1 External IRQ pin is connected to interrupt logic. Note: When IRQEN = 0, the edge detect latch is disabled.
6 IRQEN
MC3S12RG128 Data Sheet, Rev. 1.05 152 Freescale Semiconductor
Chapter 4 Multiplexed External Bus Interface (MEBIV3) Block Description
4.3.2.15
Port K Data Register (PORTK)
Module Base + 0x0032 Starting address location affected by INITRG register setting.
7 6 5 4 3 2 1 0
R Bit 7 W Reset Alternate Pin Function 0 ECS 0 XCS 0 XAB19 0 XAB18 0 XAB17 0 XAB16 0 XAB15 0 XAB14 6 5 4 3 2 1 Bit 0
Figure 4-20. Port K Data Register (PORTK)
Read: Anytime Write: Anytime This port is associated with the internal memory expansion emulation pins. When the port is not enabled to emulate the internal memory expansion, the port pins are used as general-purpose I/O. When port K is operating as a general-purpose I/O port, DDRK determines the primary direction for each port K pin. A 1 causes the associated port pin to be an output and a 0 causes the associated pin to be a high-impedance input. The value in a DDR bit also affects the source of data for reads of the corresponding PORTK register. If the DDR bit is 0 (input) the buffered pin input is read. If the DDR bit is 1 (output) the output of the port data register is read. This register is not in the map in peripheral or expanded modes while the EMK control bit in MODE register is set. Therefore, these accesses will be echoed externally. When inputs, these pins can be selected to be high impedance or pulled up, based upon the state of the PUPKE bit in the PUCR register.
Table 4-12. PORTK Field Descriptions
Field 7 Port K, Bit 7 Description Port K, Bit 7 -- This bit is used as an emulation chip select signal for the emulation of the internal memory expansion, or as general-purpose I/O, depending upon the state of the EMK bit in the MODE register. While this bit is used as a chip select, the external bit will return to its de-asserted state (VDD) for approximately 1/4 cycle just after the negative edge of ECLK, unless the external access is stretched and ECLK is free-running (ESTR bit in EBICTL = 0). See the MMC block description chapter for additional details on when this signal will be active. Port K, Bit 6 -- This bit is used as an external chip select signal for most external accesses that are not selected by ECS (see the MMC block description chapter for more details), depending upon the state the of the EMK bit in the MODE register. While this bit is used as a chip select, the external pin will return to its de-asserted state (VDD) for approximately 1/4 cycle just after the negative edge of ECLK, unless the external access is stretched and ECLK is free-running (ESTR bit in EBICTL = 0).
6 Port K, Bit 6
5:0 Port K, Bits 5:0 -- These six bits are used to determine which FLASH/ROM or external memory array page Port K, Bits 5:0 is being accessed. They can be viewed as expanded addresses XAB19-XAB14 of the 20-bit address used to access up to1M byte internal FLASH/ROM or external memory array. Alternatively, these bits can be used for general-purpose I/O depending upon the state of the EMK bit in the MODE register.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 153
Chapter 4 Multiplexed External Bus Interface (MEBIV3) Block Description
4.3.2.16
Port K Data Direction Register (DDRK)
Module Base + 0x0033 Starting address location affected by INITRG register setting.
7 6 5 4 3 2 1 0
R Bit 7 W Reset 0 0 0 0 0 0 0 0 6 5 4 3 2 1 Bit 0
Figure 4-21. Port K Data Direction Register (DDRK)
Read: Anytime Write: Anytime This register determines the primary direction for each port K pin configured as general-purpose I/O. This register is not in the map in peripheral or expanded modes while the EMK control bit in MODE register is set. Therefore, these accesses will be echoed externally.
Table 4-13. EBICTL Field Descriptions
Field 7:0 DDRK Description Data Direction Port K Bits 0 Associated pin is a high-impedance input 1 Associated pin is an output Note: It is unwise to write PORTK and DDRK as a word access. If you are changing port K pins from inputs to outputs, the data may have extra transitions during the write. It is best to initialize PORTK before enabling as outputs. Note: To ensure that you read the correct value from the PORTK pins, always wait at least one cycle after writing to the DDRK register before reading from the PORTK register.
4.4
4.4.1
Functional Description
Detecting Access Type from External Signals
The external signals LSTRB, R/W, and AB0 indicate the type of bus access that is taking place. Accesses to the internal RAM module are the only type of access that would produce LSTRB = AB0 = 1, because the internal RAM is specifically designed to allow misaligned 16-bit accesses in a single cycle. In these cases the data for the address that was accessed is on the low half of the data bus and the data for address + 1 is on the high half of the data bus. This is summarized in Table 4-14.
Table 4-14. Access Type vs. Bus Control Pins
LSTRB 1 0 1 0 AB0 0 1 0 1 R/W 1 1 0 0 Type of Access 8-bit read of an even address 8-bit read of an odd address 8-bit write of an even address 8-bit write of an odd address
MC3S12RG128 Data Sheet, Rev. 1.05 154 Freescale Semiconductor
Chapter 4 Multiplexed External Bus Interface (MEBIV3) Block Description
Table 4-14. Access Type vs. Bus Control Pins
LSTRB 0 1 0 1 AB0 0 1 0 1 R/W 1 1 0 0 Type of Access 16-bit read of an even address 16-bit read of an odd address (low/high data swapped) 16-bit write to an even address 16-bit write to an odd address (low/high data swapped)
4.4.2
Stretched Bus Cycles
In order to allow fast internal bus cycles to coexist in a system with slower external memory resources, the HCS12 supports the concept of stretched bus cycles (module timing reference clocks for timers and baud rate generators are not affected by this stretching). Control bits in the MISC register in the MMC sub-block of the core specify the amount of stretch (0, 1, 2, or 3 periods of the internal bus-rate clock). While stretching, the CPU state machines are all held in their current state. At this point in the CPU bus cycle, write data would already be driven onto the data bus so the length of time write data is valid is extended in the case of a stretched bus cycle. Read data would not be captured by the system until the E clock falling edge. In the case of a stretched bus cycle, read data is not required until the specified setup time before the falling edge of the stretched E clock. The chip selects, and R/W signals remain valid during the period of stretching (throughout the stretched E high time). NOTE The address portion of the bus cycle is not stretched.
4.4.3
Modes of Operation
The operating mode out of reset is determined by the states of the MODC, MODB, and MODA pins during reset (Table 4-15). The MODC, MODB, and MODA bits in the MODE register show the current operating mode and provide limited mode switching during operation. The states of the MODC, MODB, and MODA pins are latched into these bits on the rising edge of the reset signal.
Table 4-15. Mode Selection
MODC 0 0 0 0 1 1 1 1 MODB 0 0 1 1 0 0 1 1 MODA 0 1 0 1 0 1 0 1 Mode Description Special Single Chip, BDM allowed and ACTIVE. BDM is allowed in all other modes but a serial command is required to make BDM active. Emulation Expanded Narrow, BDM allowed Special Test (Expanded Wide), BDM allowed Emulation Expanded Wide, BDM allowed Normal Single Chip, BDM allowed Normal Expanded Narrow, BDM allowed Peripheral; BDM allowed but bus operations would cause bus conflicts (must not be used) Normal Expanded Wide, BDM allowed
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Chapter 4 Multiplexed External Bus Interface (MEBIV3) Block Description
There are two basic types of operating modes: 1. Normal modes: Some registers and bits are protected against accidental changes. 2. Special modes: Allow greater access to protected control registers and bits for special purposes such as testing. A system development and debug feature, background debug mode (BDM), is available in all modes. In special single-chip mode, BDM is active immediately after reset. Some aspects of Port E are not mode dependent. Bit 1 of Port E is a general purpose input or the IRQ interrupt input. IRQ can be enabled by bits in the CPU's condition codes register but it is inhibited at reset so this pin is initially configured as a simple input with a pull-up. Bit 0 of Port E is a general purpose input or the XIRQ interrupt input. XIRQ can be enabled by bits in the CPU's condition codes register but it is inhibited at reset so this pin is initially configured as a simple input with a pull-up. The ESTR bit in the EBICTL register is set to one by reset in any user mode. This assures that the reset vector can be fetched even if it is located in an external slow memory device. The PE6/MODB/IPIPE1 and PE5/MODA/IPIPE0 pins act as high-impedance mode select inputs during reset. The following paragraphs discuss the default bus setup and describe which aspects of the bus can be changed after reset on a per mode basis.
4.4.3.1
Normal Operating Modes
These modes provide three operating configurations. Background debug is available in all three modes, but must first be enabled for some operations by means of a BDM background command, then activated. 4.4.3.1.1 Normal Single-Chip Mode
There is no external expansion bus in this mode. All pins of Ports A, B and E are configured as general purpose I/O pins Port E bits 1 and 0 are available as general purpose input only pins with internal pull-ups enabled. All other pins of Port E are bidirectional I/O pins that are initially configured as high-impedance inputs with internal pull-ups enabled. Ports A and B are configured as high-impedance inputs with their internal pull-ups disabled. The pins associated with Port E bits 6, 5, 3, and 2 cannot be configured for their alternate functions IPIPE1, IPIPE0, LSTRB, and R/W while the MCU is in single chip modes. In single chip modes, the associated control bits PIPOE, LSTRE, and RDWE are reset to zero. Writing the opposite state into them in single chip mode does not change the operation of the associated Port E pins. In normal single chip mode, the MODE register is writable one time. This allows a user program to change the bus mode to narrow or wide expanded mode and/or turn on visibility of internal accesses. Port E, bit 4 can be configured for a free-running E clock output by clearing NECLK=0. Typically the only use for an E clock output while the MCU is in single chip modes would be to get a constant speed clock for use in the external application system.
MC3S12RG128 Data Sheet, Rev. 1.05 156 Freescale Semiconductor
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4.4.3.1.2
Normal Expanded Wide Mode
In expanded wide modes, Ports A and B are configured as a 16-bit multiplexed address and data bus and Port E bit 4 is configured as the E clock output signal. These signals allow external memory and peripheral devices to be interfaced to the MCU. Port E pins other than PE4/ECLK are configured as general purpose I/O pins (initially high-impedance inputs with internal pull-up resistors enabled). Control bits PIPOE, NECLK, LSTRE, and RDWE in the PEAR register can be used to configure Port E pins to act as bus control outputs instead of general purpose I/O pins. It is possible to enable the pipe status signals on Port E bits 6 and 5 by setting the PIPOE bit in PEAR, but it would be unusual to do so in this mode. Development systems where pipe status signals are monitored would typically use the special variation of this mode. The Port E bit 2 pin can be reconfigured as the R/W bus control signal by writing "1" to the RDWE bit in PEAR. If the expanded system includes external devices that can be written, such as RAM, the RDWE bit would need to be set before any attempt to write to an external location. If there are no writable resources in the external system, PE2 can be left as a general purpose I/O pin. The Port E bit 3 pin can be reconfigured as the LSTRB bus control signal by writing "1" to the LSTRE bit in PEAR. The default condition of this pin is a general purpose input because the LSTRB function is not needed in all expanded wide applications. The Port E bit 4 pin is initially configured as ECLK output with stretch. The E clock output function depends upon the settings of the NECLK bit in the PEAR register, the IVIS bit in the MODE register and the ESTR bit in the EBICTL register. The E clock is available for use in external select decode logic or as a constant speed clock for use in the external application system. 4.4.3.1.3 Normal Expanded Narrow Mode
This mode is used for lower cost production systems that use 8-bit wide external EPROMs or RAMs. Such systems take extra bus cycles to access 16-bit locations but this may be preferred over the extra cost of additional external memory devices. Ports A and B are configured as a 16-bit address bus and Port A is multiplexed with data. Internal visibility is not available in this mode because the internal cycles would need to be split into two 8-bit cycles. Since the PEAR register can only be written one time in this mode, use care to set all bits to the desired states during the single allowed write. The PE3/LSTRB pin is always a general purpose I/O pin in normal expanded narrow mode. Although it is possible to write the LSTRE bit in PEAR to "1" in this mode, the state of LSTRE is overridden and Port E bit 3 cannot be reconfigured as the LSTRB output. It is possible to enable the pipe status signals on Port E bits 6 and 5 by setting the PIPOE bit in PEAR, but it would be unusual to do so in this mode. LSTRB would also be needed to fully understand system activity. Development systems where pipe status signals are monitored would typically use special expanded wide mode or occasionally special expanded narrow mode.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 157
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The PE4/ECLK pin is initially configured as ECLK output with stretch. The E clock output function depends upon the settings of the NECLK bit in the PEAR register, the IVIS bit in the MODE register and the ESTR bit in the EBICTL register. In normal expanded narrow mode, the E clock is available for use in external select decode logic or as a constant speed clock for use in the external application system. The PE2/R/W pin is initially configured as a general purpose input with a pull-up but this pin can be reconfigured as the R/W bus control signal by writing "1" to the RDWE bit in PEAR. If the expanded narrow system includes external devices that can be written such as RAM, the RDWE bit would need to be set before any attempt to write to an external location. If there are no writable resources in the external system, PE2 can be left as a general purpose I/O pin. 4.4.3.1.4 Emulation Expanded Wide Mode
In expanded wide modes, Ports A and B are configured as a 16-bit multiplexed address and data bus and Port E provides bus control and status signals. These signals allow external memory and peripheral devices to be interfaced to the MCU. These signals can also be used by a logic analyzer to monitor the progress of application programs. The bus control related pins in Port E (PE7/NOACC, PE6/MODB/IPIPE1, PE5/MODA/IPIPE0, PE4/ECLK, PE3/LSTRB/TAGLO, and PE2/R/W) are all configured to serve their bus control output functions rather than general purpose I/O. Notice that writes to the bus control enable bits in the PEAR register in emulation mode are restricted. 4.4.3.1.5 Emulation Expanded Narrow Mode
Expanded narrow modes are intended to allow connection of single 8-bit external memory devices for lower cost systems that do not need the performance of a full 16-bit external data bus. Accesses to internal resources that have been mapped external (i.e. PORTA, PORTB, DDRA, DDRB, PORTE, DDRE, PEAR, PUCR, RDRIV) will be accessed with a 16-bit data bus on Ports A and B. Accesses of 16-bit external words to addresses which are normally mapped external will be broken into two separate 8-bit accesses using Port A as an 8-bit data bus. Internal operations continue to use full 16-bit data paths. They are only visible externally as 16-bit information if IVIS=1. Ports A and B are configured as multiplexed address and data output ports. During external accesses, address A15, data D15 and D7 are associated with PA7, address A0 is associated with PB0 and data D8 and D0 are associated with PA0. During internal visible accesses and accesses to internal resources that have been mapped external, address A15 and data D15 is associated with PA7 and address A0 and data D0 is associated with PB0. The bus control related pins in Port E (PE7/NOACC, PE6/MODB/IPIPE1, PE5/MODA/IPIPE0, PE4/ECLK, PE3/LSTRB/TAGLO, and PE2/R/W) are all configured to serve their bus control output functions rather than general purpose I/O. Notice that writes to the bus control enable bits in the PEAR register in emulation mode are restricted. The main difference between special modes and normal modes is that some of the bus control and system control signals cannot be written in emulation modes.
MC3S12RG128 Data Sheet, Rev. 1.05 158 Freescale Semiconductor
Chapter 4 Multiplexed External Bus Interface (MEBIV3) Block Description
4.4.3.2
Special Operating Modes
There are two special operating modes that correspond to normal operating modes. These operating modes are commonly used in factory testing and system development. 4.4.3.2.1 Special Single-Chip Mode
When the MCU is reset in this mode, the background debug mode is enabled and active. The MCU does not fetch the reset vector and execute application code as it would in other modes. Instead the active background mode is in control of CPU execution and BDM firmware is waiting for additional serial commands through the BKGD pin. When a serial command instructs the MCU to return to normal execution, the system will be configured as described below unless the reset states of internal control registers have been changed through background commands after the MCU was reset. There is no external expansion bus after reset in this mode. Ports A and B are initially simple bidirectional I/O pins that are configured as high-impedance inputs with internal pull-ups disabled; however, writing to the mode select bits in the MODE register (which is allowed in special modes) can change this after reset. All of the Port E pins (except PE4/ECLK) are initially configured as general purpose high-impedance inputs with pull-ups enabled. PE4/ECLK is configured as the E clock output in this mode. The pins associated with Port E bits 6, 5, 3, and 2 cannot be configured for their alternate functions IPIPE1, IPIPE0, LSTRB, and R/W while the MCU is in single chip modes. In single chip modes, the associated control bits PIPOE, LSTRE and RDWE are reset to zero. Writing the opposite value into these bits in single chip mode does not change the operation of the associated Port E pins. Port E, bit 4 can be configured for a free-running E clock output by clearing NECLK=0. Typically the only use for an E clock output while the MCU is in single chip modes would be to get a constant speed clock for use in the external application system. 4.4.3.2.2 Special Test Mode
In expanded wide modes, Ports A and B are configured as a 16-bit multiplexed address and data bus and Port E provides bus control and status signals. In special test mode, the write protection of many control bits is lifted so that they can be thoroughly tested without needing to go through reset.
4.4.3.3
Test Operating Mode
There is a test operating mode in which an external master, such as an I.C. tester, can control the on-chip peripherals. 4.4.3.3.1 Peripheral Mode
This mode is intended for factory testing of the MCU. In this mode, the CPU is inactive and an external (tester) bus master drives address, data and bus control signals in through Ports A, B and E. In effect, the whole MCU acts as if it was a peripheral under control of an external CPU. This allows faster testing of on-chip memory and peripherals than previous testing methods. Since the mode control register is not accessible in peripheral mode, the only way to change to another mode is to reset the MCU into a different
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Chapter 4 Multiplexed External Bus Interface (MEBIV3) Block Description
mode. Background debugging should not be used while the MCU is in special peripheral mode as internal bus conflicts between BDM and the external master can cause improper operation of both functions.
4.4.4
Internal Visibility
Internal visibility is available when the MCU is operating in expanded wide modes or emulation narrow mode. It is not available in single-chip, peripheral or normal expanded narrow modes. Internal visibility is enabled by setting the IVIS bit in the MODE register. If an internal access is made while E, R/W, and LSTRB are configured as bus control outputs and internal visibility is off (IVIS=0), E will remain low for the cycle, R/W will remain high, and address, data and the LSTRB pins will remain at their previous state. When internal visibility is enabled (IVIS=1), certain internal cycles will be blocked from going external. During cycles when the BDM is selected, R/W will remain high, data will maintain its previous state, and address and LSTRB pins will be updated with the internal value. During CPU no access cycles when the BDM is not driving, R/W will remain high, and address, data and the LSTRB pins will remain at their previous state. NOTE When the system is operating in a secure mode, internal visibility is not available (i.e., IVIS = 1 has no effect). Also, the IPIPE signals will not be visible, regardless of operating mode. IPIPE1-IPIPE0 will display 0es if they are enabled. In addition, the MOD bits in the MODE control register cannot be written.
4.4.5
Low-Power Options
The MEBI does not contain any user-controlled options for reducing power consumption. The operation of the MEBI in low-power modes is discussed in the following subsections.
4.4.5.1
Operation in Run Mode
The MEBI does not contain any options for reducing power in run mode; however, the external addresses are conditioned to reduce power in single-chip modes. Expanded bus modes will increase power consumption.
4.4.5.2
Operation in Wait Mode
The MEBI does not contain any options for reducing power in wait mode.
4.4.5.3
Operation in Stop Mode
The MEBI will cease to function after execution of a CPU STOP instruction.
Figure 4-22.
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Chapter 4 Multiplexed External Bus Interface (MEBIV3) Block Description
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MC3S12RG128 Data Sheet, Rev. 1.05 162 Freescale Semiconductor
Chapter 4 Multiplexed External Bus Interface (MEBIV3) Block Description
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Chapter 4 Multiplexed External Bus Interface (MEBIV3) Block Description
MC3S12RG128 Data Sheet, Rev. 1.05 164 Freescale Semiconductor
Chapter 4 Multiplexed External Bus Interface (MEBIV3) Block Description
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MC3S12RG128 Data Sheet, Rev. 1.05 166 Freescale Semiconductor
Chapter 5 Interrupt (INTV1) Block Description
5.1 Introduction
This section describes the functionality of the interrupt (INT) sub-block of the S12 core platform. A block diagram of the interrupt sub-block is shown in Figure 5-1.
INT
WRITE DATA BUS
HPRIO (OPTIONAL)
HIGHEST PRIORITY I-INTERRUPT
INTERRUPTS XMASK IMASK INTERRUPT INPUT REGISTERS AND CONTROL REGISTERS READ DATA BUS
WAKEUP HPRIO VECTOR
QUALIFIED INTERRUPTS
INTERRUPT PENDING RESET FLAGS VECTOR REQUEST PRIORITY DECODER VECTOR ADDRESS
Figure 5-1. INT Block Diagram
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 167
Chapter 5 Interrupt (INTV1) Block Description
The interrupt sub-block decodes the priority of all system exception requests and provides the applicable vector for processing the exception. The INT supports I-bit maskable and X-bit maskable interrupts, a non-maskable unimplemented opcode trap, a non-maskable software interrupt (SWI) or background debug mode request, and three system reset vector requests. All interrupt related exception requests are managed by the interrupt sub-block (INT).
5.1.1
Features
The INT includes these features: * Provides two to 122 I-bit maskable interrupt vectors (0xFF00-0xFFF2) * Provides one X-bit maskable interrupt vector (0xFFF4) * Provides a non-maskable software interrupt (SWI) or background debug mode request vector (0xFFF6) * Provides a non-maskable unimplemented opcode trap (TRAP) vector (0xFFF8) * Provides three system reset vectors (0xFFFA-0xFFFE) (reset, CMR, and COP) * Determines the appropriate vector and drives it onto the address bus at the appropriate time * Signals the CPU that interrupts are pending * Provides control registers which allow testing of interrupts * Provides additional input signals which prevents requests for servicing I and X interrupts * Wakes the system from stop or wait mode when an appropriate interrupt occurs or whenever XIRQ is active, even if XIRQ is masked * Provides asynchronous path for all I and X interrupts, (0xFF00-0xFFF4) * (Optional) selects and stores the highest priority I interrupt based on the value written into the HPRIO register
5.1.2
Modes of Operation
The functionality of the INT sub-block in various modes of operation is discussed in the subsections that follow. * Normal operation The INT operates the same in all normal modes of operation. * Special operation Interrupts may be tested in special modes through the use of the interrupt test registers. * Emulation modes The INT operates the same in emulation modes as in normal modes. * Low power modes See Section 5.4.1, "Low-Power Modes," for details
MC3S12RG128 Data Sheet, Rev. 1.05 168 Freescale Semiconductor
Chapter 5 Interrupt (INTV1) Block Description
5.2
External Signal Description
Most interfacing with the interrupt sub-block is done within the core. However, the interrupt does receive direct input from the multiplexed external bus interface (MEBI) sub-block of the core for the IRQ and XIRQ pin data.
5.3
Memory Map and Register Definition
Detailed descriptions of the registers and associated bits are given in the subsections that follow.
5.3.1
Name 0x0015 ITCR 0x0016 ITEST 0x001F HPRIO
Module Memory Map
Bit 7 R W R W R W INTE INTC INTA 0 6 0 5 0 4 WRTINT 3 ADR3 2 ADR2 1 ADR1 Bit 0 ADR0
INT8
INT6
INT4
INT2
INT0 0
PSEL7
PSEL6
PSEL5
PSEL4
PSEL3
PSEL2
PSEL1
= Unimplemented or Reserved
Figure 5-2. INT Register Summary
5.3.2
5.3.2.1
Register Descriptions
Interrupt Test Control Register
Module Base + 0x0015 Starting address location affected by INITRG register setting.
7 6 5 4 3 2 1 0
R W Reset
0
0
0 WRTINT ADR3 1 ADR2 1 ADR1 1 ADR0 1
0
0
0
0
= Unimplemented or Reserved
Figure 5-3. Interrupt Test Control Register (ITCR)
Read: See individual bit descriptions Write: See individual bit descriptions
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Chapter 5 Interrupt (INTV1) Block Description
Table 5-1. ITCR Field Descriptions
Field 4 WRTINT Description Write to the Interrupt Test Registers Read: anytime Write: only in special modes and with I-bit mask and X-bit mask set. 0 Disables writes to the test registers; reads of the test registers will return the state of the interrupt inputs. 1 Disconnect the interrupt inputs from the priority decoder and use the values written into the ITEST registers instead. Note: Any interrupts which are pending at the time that WRTINT is set will remain until they are overwritten. Test Register Select Bits Read: anytime Write: anytime These bits determine which test register is selected on a read or write. The hexadecimal value written here will be the same as the upper nibble of the lower byte of the vector selects. That is, an "F" written into ADR[3:0] will select vectors 0xFFFE-0xFFF0 while a "7" written to ADR[3:0] will select vectors 0xFF7E-0xFF70.
3:0 ADR[3:0]
5.3.2.2
Interrupt Test Registers
Module Base + 0x0016 Starting address location affected by INITRG register setting.
7 6 5 4 3 2 1 0
R INTE W Reset 0 0 0 0 0 0 0 0 INTC INTA INT8 INT6 INT4 INT2 INT0
= Unimplemented or Reserved
Figure 5-4. Interrupt TEST Registers (ITEST)
Read: Only in special modes. Reads will return either the state of the interrupt inputs of the interrupt sub-block (WRTINT = 0) or the values written into the TEST registers (WRTINT = 1). Reads will always return 0s in normal modes. Write: Only in special modes and with WRTINT = 1 and CCR I mask = 1.
MC3S12RG128 Data Sheet, Rev. 1.05 170 Freescale Semiconductor
Chapter 5 Interrupt (INTV1) Block Description
Table 5-2. ITEST Field Descriptions
Field 7:0 INT[E:0] Description Interrupt TEST Bits -- These registers are used in special modes for testing the interrupt logic and priority independent of the system configuration. Each bit is used to force a specific interrupt vector by writing it to a logic 1 state. Bits are named INTE through INT0 to indicate vectors 0xFFxE through 0xFFx0. These bits can be written only in special modes and only with the WRTINT bit set (logic 1) in the interrupt test control register (ITCR). In addition, I interrupts must be masked using the I bit in the CCR. In this state, the interrupt input lines to the interrupt sub-block will be disconnected and interrupt requests will be generated only by this register. These bits can also be read in special modes to view that an interrupt requested by a system block (such as a peripheral block) has reached the INT module. There is a test register implemented for every eight interrupts in the overall system. All of the test registers share the same address and are individually selected using the value stored in the ADR[3:0] bits of the interrupt test control register (ITCR). Note: When ADR[3:0] have the value of 0x000F, only bits 2:0 in the ITEST register will be accessible. That is, vectors higher than 0xFFF4 cannot be tested using the test registers and bits 7:3 will always read as a logic 0. If ADR[3:0] point to an unimplemented test register, writes will have no effect and reads will always return a logic 0 value.
5.3.2.3
Highest Priority I Interrupt (Optional)
Module Base + 0x001F Starting address location affected by INITRG register setting.
7 6 5 4 3 2 1 0
R PSEL7 W Reset 1 1 1 1 0 0 1 PSEL6 PSEL5 PSEL4 PSEL3 PSEL2 PSEL1
0
0
= Unimplemented or Reserved
Figure 5-5. Highest Priority I Interrupt Register (HPRIO)
Read: Anytime Write: Only if I mask in CCR = 1
Table 5-3. HPRIO Field Descriptions
Field 7:1 PSEL[7:1] Description Highest Priority I Interrupt Select Bits -- The state of these bits determines which I-bit maskable interrupt will be promoted to highest priority (of the I-bit maskable interrupts). To promote an interrupt, the user writes the least significant byte of the associated interrupt vector address to this register. If an unimplemented vector address or a non I-bit masked vector address (value higher than 0x00F2) is written, IRQ (0xFFF2) will be the default highest priority interrupt.
5.4
Functional Description
The interrupt sub-block processes all exception requests made by the CPU. These exceptions include interrupt vector requests and reset vector requests. Each of these exception types and their overall priority level is discussed in the subsections below.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 171
Chapter 5 Interrupt (INTV1) Block Description
5.4.1
Low-Power Modes
The INT does not contain any user-controlled options for reducing power consumption. The operation of the INT in low-power modes is discussed in the following subsections.
5.4.1.1
Operation in Run Mode
The INT does not contain any options for reducing power in run mode.
5.4.1.2
Operation in Wait Mode
Clocks to the INT can be shut off during system wait mode and the asynchronous interrupt path will be used to generate the wake-up signal upon recognition of a valid interrupt or any XIRQ request.
5.4.1.3
Operation in Stop Mode
Clocks to the INT can be shut off during system stop mode and the asynchronous interrupt path will be used to generate the wake-up signal upon recognition of a valid interrupt or any XIRQ request.
5.5
Resets
The INT supports three system reset exception request types: normal system reset or power-on-reset request, crystal monitor reset request, and COP watchdog reset request. The type of reset exception request must be decoded by the system and the proper request made to the core. The INT will then provide the service routine address for the type of reset requested.
5.6
Interrupts
As shown in the block diagram in Figure 5-1, the INT contains a register block to provide interrupt status and control, an optional highest priority I interrupt (HPRIO) block, and a priority decoder to evaluate whether pending interrupts are valid and assess their priority.
5.6.1
Interrupt Registers
The INT registers are accessible only in special modes of operation and function as described in Section 5.3.2.1, "Interrupt Test Control Register," and Section 5.3.2.2, "Interrupt Test Registers," previously.
5.6.2
Highest Priority I-Bit Maskable Interrupt
When the optional HPRIO block is implemented, the user is allowed to promote a single I-bit maskable interrupt to be the highest priority I interrupt. The HPRIO evaluates all interrupt exception requests and passes the HPRIO vector to the priority decoder if the highest priority I interrupt is active. RTI replaces the promoted interrupt source.
MC3S12RG128 Data Sheet, Rev. 1.05 172 Freescale Semiconductor
Chapter 5 Interrupt (INTV1) Block Description
5.6.3
Interrupt Priority Decoder
The priority decoder evaluates all interrupts pending and determines their validity and priority. When the CPU requests an interrupt vector, the decoder will provide the vector for the highest priority interrupt request. Because the vector is not supplied until the CPU requests it, it is possible that a higher priority interrupt request could override the original exception that caused the CPU to request the vector. In this case, the CPU will receive the highest priority vector and the system will process this exception instead of the original request. NOTE Care must be taken to ensure that all exception requests remain active until the system begins execution of the applicable service routine; otherwise, the exception request may not be processed. If for any reason the interrupt source is unknown (e.g., an interrupt request becomes inactive after the interrupt has been recognized but prior to the vector request), the vector address will default to that of the last valid interrupt that existed during the particular interrupt sequence. If the CPU requests an interrupt vector when there has never been a pending interrupt request, the INT will provide the software interrupt (SWI) vector address.
5.7
Exception Priority
The priority (from highest to lowest) and address of all exception vectors issued by the INT upon request by the CPU is shown in Table 5-4.
Table 5-4. Exception Vector Map and Priority
Vector Address 0xFFFE-0xFFFF 0xFFFC-0xFFFD 0xFFFA-0xFFFB 0xFFF8-0xFFF9 0xFFF6-0xFFF7 0xFFF4-0xFFF5 0xFFF2-0xFFF3 0xFFF0-0xFF00 System reset Crystal monitor reset COP reset Unimplemented opcode trap Software interrupt instruction (SWI) or BDM vector request XIRQ signal IRQ signal Device-specific I-bit maskable interrupt sources (priority in descending order) Source
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 173
Chapter 5 Interrupt (INTV1) Block Description
MC3S12RG128 Data Sheet, Rev. 1.05 174 Freescale Semiconductor
Chapter 6 Background Debug Module (BDMV4) Block Description
6.1 Introduction
This section describes the functionality of the background debug module (BDM) sub-block of the HCS12 core platform. A block diagram of the BDM is shown in Figure 6-1.
HOST SYSTEM BKGD 16-BIT SHIFT REGISTER
ADDRESS ENTAG BDMACT TRACE INSTRUCTION DECODE AND EXECUTION BUS INTERFACE AND CONTROL LOGIC DATA CLOCKS
SDV ENBDM
STANDARD BDM FIRMWARE LOOKUP TABLE
CLKSW
Figure 6-1. BDM Block Diagram
The background debug module (BDM) sub-block is a single-wire, background debug system implemented in on-chip hardware for minimal CPU intervention. All interfacing with the BDM is done via the BKGD pin. BDMV4 has enhanced capability for maintaining synchronization between the target and host while allowing more flexibility in clock rates. This includes a sync signal to show the clock rate and a handshake signal to indicate when an operation is complete. The system is backwards compatible with older external interfaces.
6.1.1
* * * * * *
Features
Single-wire communication with host development system BDMV4 (and BDM2): Enhanced capability for allowing more flexibility in clock rates BDMV4: SYNC command to determine communication rate BDMV4: GO_UNTIL command BDMV4: Hardware handshake protocol to increase the performance of the serial communication Active out of reset in special single-chip mode
MC3S12RG128 Data Sheet, Rev. 1.05
Freescale Semiconductor
175
Chapter 6 Background Debug Module (BDMV4) Block Description
* * * * * * *
Nine hardware commands using free cycles, if available, for minimal CPU intervention Hardware commands not requiring active BDM 15 firmware commands execute from the standard BDM firmware lookup table Instruction tagging capability Software control of BDM operation during wait mode Software selectable clocks When secured, hardware commands are allowed to access the register space in special single-chip mode, if the FLASH and EEPROM erase tests fail.
6.1.2
Modes of Operation
BDM is available in all operating modes but must be enabled before firmware commands are executed. Some system peripherals may have a control bit which allows suspending the peripheral function during background debug mode.
6.1.2.1
Regular Run Modes
All of these operations refer to the part in run mode. The BDM does not provide controls to conserve power during run mode. * Normal operation General operation of the BDM is available and operates the same in all normal modes. * Special single-chip mode In special single-chip mode, background operation is enabled and active out of reset. This allows programming a system with blank memory. * Special peripheral mode BDM is enabled and active immediately out of reset. BDM can be disabled by clearing the BDMACT bit in the BDM status (BDMSTS) register. The BDM serial system should not be used in special peripheral mode. * Emulation modes General operation of the BDM is available and operates the same as in normal modes.
6.1.2.2
Secure Mode Operation
If the part is in secure mode, the operation of the BDM is reduced to a small subset of its regular run mode operation. Secure operation prevents access to FLASH or EEPROM other than allowing erasure.
6.2
External Signal Description
A single-wire interface pin is used to communicate with the BDM system. Two additional pins are used for instruction tagging. These pins are part of the multiplexed external bus interface (MEBI) sub-block and all interfacing between the MEBI and BDM is done within the core interface boundary. Functional descriptions of the pins are provided below for completeness.
MC3S12RG128 Data Sheet, Rev. 1.05 176 Freescale Semiconductor
Chapter 6 Background Debug Module (BDMV4) Block Description
* * * * *
BKGD -- Background interface pin TAGHI -- High byte instruction tagging pin TAGLO -- Low byte instruction tagging pin BKGD and TAGHI share the same pin. TAGLO and LSTRB share the same pin. NOTE Generally these pins are shared as described, but it is best to check the device overview chapter to make certain. All MCUs at the time of this writing have followed this pin sharing scheme.
6.2.1
BKGD -- Background Interface Pin
Debugging control logic communicates with external devices serially via the single-wire background interface pin (BKGD). During reset, this pin is a mode select input which selects between normal and special modes of operation. After reset, this pin becomes the dedicated serial interface pin for the background debug mode.
6.2.2
TAGHI -- High Byte Instruction Tagging Pin
This pin is used to tag the high byte of an instruction. When instruction tagging is on, a logic 0 at the falling edge of the external clock (ECLK) tags the high half of the instruction word being read into the instruction queue.
6.2.3
TAGLO -- Low Byte Instruction Tagging Pin
This pin is used to tag the low byte of an instruction. When instruction tagging is on and low strobe is enabled, a logic 0 at the falling edge of the external clock (ECLK) tags the low half of the instruction word being read into the instruction queue.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 177
Chapter 6 Background Debug Module (BDMV4) Block Description
6.3
Memory Map and Register Definition
A summary of the registers associated with the BDM is shown in Figure 6-2. Registers are accessed by host-driven communications to the BDM hardware using READ_BD and WRITE_BD commands. Detailed descriptions of the registers and associated bits are given in the subsections that follow.
MC3S12RG128 Data Sheet, Rev. 1.05 178 Freescale Semiconductor
Chapter 6 Background Debug Module (BDMV4) Block Description
6.3.1
Register Name 0xFF00 Reserved 0xFF01 BDMSTS 0xFF02 Reserved 0xFF03 Reserved 0xFF04 Reserved 0xFF05 Reserved 0xFF06 BDMCCR 0xFF07 BDMINR 0xFF08 Reserved 0xFF09 Reserved 0xFF0A Reserved 0xFF0B Reserved
Register Descriptions
Bit 7 R W R W R W R W R W R W R W R W R W R W R W R W X 6 X 5 X 4 X 3 X 2 X 1 0 Bit 0 0
ENBDM X
BDMACT
ENTAG X
SDV
TRACE
CLKSW X
UNSEC
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
CCR7 0
CCR6 REG14
CCR5 REG13
CCR4 REG12
CCR3 REG11
CCR2 0
CCR1 0
CCR0 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
= Unimplemented, Reserved X = Indeterminate 0
= Implemented (do not alter) = Always read zero
Figure 6-2. BDM Register Summary
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 179
Chapter 6 Background Debug Module (BDMV4) Block Description
6.3.1.1
0xFF01
BDM Status Register (BDMSTS)
7
6
5
4
3
2
1
0
R ENBDM W Reset: Special single-chip mode: Special peripheral mode: All other modes: 11 0 0 0
BDMACT ENTAG
SDV
TRACE CLKSW
UNSEC
0
1 1 1 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
02 0 0 0
0 0 0 0
= Unimplemented or Reserved
= Implemented (do not alter)
Figure 6-3. BDM Status Register (BDMSTS)
Note:
1
ENBDM is read as "1" by a debugging environment in Special single-chip mode when the device is not secured or secured but fully erased (Flash and EEPROM).This is because the ENBDM bit is set by the standard firmware before a BDM command can be fully transmitted and executed. UNSEC is read as "1" by a debugging environment in Special single-chip mode when the device is secured and fully erased, else it is "0" and can only be read if not secure (see also bit description).
2
Read: All modes through BDM operation Write: All modes but subject to the following: * BDMACT can only be set by BDM hardware upon entry into BDM. It can only be cleared by the standard BDM firmware lookup table upon exit from BDM active mode. * CLKSW can only be written via BDM hardware or standard BDM firmware write commands. * All other bits, while writable via BDM hardware or standard BDM firmware write commands, should only be altered by the BDM hardware or standard firmware lookup table as part of BDM command execution. * ENBDM should only be set via a BDM hardware command if the BDM firmware commands are needed. (This does not apply in special single-chip mode).
MC3S12RG128 Data Sheet, Rev. 1.05 180 Freescale Semiconductor
Chapter 6 Background Debug Module (BDMV4) Block Description
Table 6-1. BDMSTS Field Descriptions
Field 7 ENBDM Description Enable BDM -- This bit controls whether the BDM is enabled or disabled. When enabled, BDM can be made active to allow firmware commands to be executed. When disabled, BDM cannot be made active but BDM hardware commands are allowed. 0 BDM disabled 1 BDM enabled Note: ENBDM is set by the firmware immediately out of reset in special single-chip mode. In secure mode, this bit will not be set by the firmware until after the EEPROM and FLASH erase verify tests are complete. BDM Active Status -- This bit becomes set upon entering BDM. The standard BDM firmware lookup table is then enabled and put into the memory map. BDMACT is cleared by a carefully timed store instruction in the standard BDM firmware as part of the exit sequence to return to user code and remove the BDM memory from the map. 0 BDM not active 1 BDM active Tagging Enable -- This bit indicates whether instruction tagging in enabled or disabled. It is set when the TAGGO command is executed and cleared when BDM is entered. The serial system is disabled and the tag function enabled 16 cycles after this bit is written. BDM cannot process serial commands while tagging is active. 0 Tagging not enabled or BDM active 1 Tagging enabled Shift Data Valid -- This bit is set and cleared by the BDM hardware. It is set after data has been transmitted as part of a firmware read command or after data has been received as part of a firmware write command. It is cleared when the next BDM command has been received or BDM is exited. SDV is used by the standard BDM firmware to control program flow execution. 0 Data phase of command not complete 1 Data phase of command is complete TRACE1 BDM Firmware Command is Being Executed -- This bit gets set when a BDM TRACE1 firmware command is first recognized. It will stay set as long as continuous back-to-back TRACE1 commands are executed. This bit will get cleared when the next command that is not a TRACE1 command is recognized. 0 TRACE1 command is not being executed 1 TRACE1 command is being executed
6 BDMACT
5 ENTAG
4 SDV
3 TRACE
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 181
Chapter 6 Background Debug Module (BDMV4) Block Description
Table 6-1. BDMSTS Field Descriptions (continued)
Field 2 CLKSW Description Clock Switch -- The CLKSW bit controls which clock the BDM operates with. It is only writable from a hardware BDM command. A 150 cycle delay at the clock speed that is active during the data portion of the command will occur before the new clock source is guaranteed to be active. The start of the next BDM command uses the new clock for timing subsequent BDM communications. Table 6-2 shows the resulting BDM clock source based on the CLKSW and the PLLSEL (Pll select from the clock and reset generator) bits. Note: The BDM alternate clock source can only be selected when CLKSW = 0 and PLLSEL = 1. The BDM serial interface is now fully synchronized to the alternate clock source, when enabled. This eliminates frequency restriction on the alternate clock which was required on previous versions. Refer to the device overview section to determine which clock connects to the alternate clock source input. Note: If the acknowledge function is turned on, changing the CLKSW bit will cause the ACK to be at the new rate for the write command which changes it. Unsecure -- This bit is only writable in special single-chip mode from the BDM secure firmware and always gets reset to zero. It is in a zero state as secure mode is entered so that the secure BDM firmware lookup table is enabled and put into the memory map along with the standard BDM firmware lookup table. The secure BDM firmware lookup table verifies that the on-chip EEPROM and FLASH EEPROM are erased. This being the case, the UNSEC bit is set and the BDM program jumps to the start of the standard BDM firmware lookup table and the secure BDM firmware lookup table is turned off. If the erase test fails, the UNSEC bit will not be asserted. 0 System is in a secured mode 1 System is in a unsecured mode Note: When UNSEC is set, security is off and the user can change the state of the secure bits in the on-chip FLASH EEPROM. Note that if the user does not change the state of the bits to "unsecured" mode, the system will be secured again when it is next taken out of reset.
1 UNSEC
Table 6-2. BDM Clock Sources
PLLSEL 0 0 1 1 CLKSW 0 1 0 1 Bus clock Bus clock Alternate clock (refer to the device overview chapter to determine the alternate clock source) Bus clock dependent on the PLL BDMCLK
MC3S12RG128 Data Sheet, Rev. 1.05 182 Freescale Semiconductor
Chapter 6 Background Debug Module (BDMV4) Block Description
6.3.1.2
0xFF06
BDM CCR Holding Register (BDMCCR)
7
6
5
4
3
2
1
0
R CCR7 W Reset 0 0 0 0 0 0 0 0 CCR6 CCR5 CCR4 CCR3 CCR2 CCR1 CCR0
Figure 6-4. BDM CCR Holding Register (BDMCCR)
Read: All modes Write: All modes NOTE When BDM is made active, the CPU stores the value of the CCR register in the BDMCCR register. However, out of special single-chip reset, the BDMCCR is set to 0xD8 and not 0xD0 which is the reset value of the CCR register. When entering background debug mode, the BDM CCR holding register is used to save the contents of the condition code register of the user's program. It is also used for temporary storage in the standard BDM firmware mode. The BDM CCR holding register can be written to modify the CCR value.
6.3.1.3
0xFF07
BDM Internal Register Position Register (BDMINR)
7
6
5
4
3
2
1
0
R W Reset
0
REG14
REG13
REG12
REG11
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 6-5. BDM Internal Register Position (BDMINR)
Read: All modes Write: Never
Table 6-3. BDMINR Field Descriptions
Field Description
6:3 Internal Register Map Position -- These four bits show the state of the upper five bits of the base address for REG[14:11] the system's relocatable register block. BDMINR is a shadow of the INITRG register which maps the register block to any 2K byte space within the first 32K bytes of the 64K byte address space.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 183
Chapter 6 Background Debug Module (BDMV4) Block Description
6.4
Functional Description
The BDM receives and executes commands from a host via a single wire serial interface. There are two types of BDM commands, namely, hardware commands and firmware commands. Hardware commands are used to read and write target system memory locations and to enter active background debug mode, see Section 6.4.3, "BDM Hardware Commands." Target system memory includes all memory that is accessible by the CPU. Firmware commands are used to read and write CPU resources and to exit from active background debug mode, see Section 6.4.4, "Standard BDM Firmware Commands." The CPU resources referred to are the accumulator (D), X index register (X), Y index register (Y), stack pointer (SP), and program counter (PC). Hardware commands can be executed at any time and in any mode excluding a few exceptions as highlighted, see Section 6.4.3, "BDM Hardware Commands." Firmware commands can only be executed when the system is in active background debug mode (BDM).
6.4.1
Security
If the user resets into special single-chip mode with the system secured, a secured mode BDM firmware lookup table is brought into the map overlapping a portion of the standard BDM firmware lookup table. The secure BDM firmware verifies that the on-chip EEPROM and FLASH EEPROM are erased. This being the case, the UNSEC bit will get set. The BDM program jumps to the start of the standard BDM firmware and the secured mode BDM firmware is turned off and all BDM commands are allowed. If the EEPROM or FLASH do not verify as erased, the BDM firmware sets the ENBDM bit, without asserting UNSEC, and the firmware enters a loop. This causes the BDM hardware commands to become enabled, but does not enable the firmware commands. This allows the BDM hardware to be used to erase the EEPROM and FLASH. After execution of the secure firmware, regardless of the results of the erase tests, the CPU registers and PPAGE will no longer be in their reset state.
6.4.2
Enabling and Activating BDM
The system must be in active BDM to execute standard BDM firmware commands. BDM can be activated only after being enabled. BDM is enabled by setting the ENBDM bit in the BDM status (BDMSTS) register. The ENBDM bit is set by writing to the BDM status (BDMSTS) register, via the single-wire interface, using a hardware command such as WRITE_BD_BYTE. After being enabled, BDM is activated by one of the following1: * Hardware BACKGROUND command * BDM external instruction tagging mechanism * CPU BGND instruction * Breakpoint sub-block's force or tag mechanism2 When BDM is activated, the CPU finishes executing the current instruction and then begins executing the firmware in the standard BDM firmware lookup table. When BDM is activated by the breakpoint
1. BDM is enabled and active immediately out of special single-chip reset. 2. This method is only available on systems that have a a breakpoint or a debug sub-block. MC3S12RG128 Data Sheet, Rev. 1.05 184 Freescale Semiconductor
Chapter 6 Background Debug Module (BDMV4) Block Description
sub-block, the type of breakpoint used determines if BDM becomes active before or after execution of the next instruction. NOTE If an attempt is made to activate BDM before being enabled, the CPU resumes normal instruction execution after a brief delay. If BDM is not enabled, any hardware BACKGROUND commands issued are ignored by the BDM and the CPU is not delayed. In active BDM, the BDM registers and standard BDM firmware lookup table are mapped to addresses 0xFF00 to 0xFFFF. BDM registers are mapped to addresses 0xFF00 to 0xFF07. The BDM uses these registers which are readable anytime by the BDM. However, these registers are not readable by user programs.
6.4.3
BDM Hardware Commands
Hardware commands are used to read and write target system memory locations and to enter active background debug mode. Target system memory includes all memory that is accessible by the CPU such as on-chip RAM, EEPROM, FLASH EEPROM, I/O and control registers, and all external memory. Hardware commands are executed with minimal or no CPU intervention and do not require the system to be in active BDM for execution, although they can continue to be executed in this mode. When executing a hardware command, the BDM sub-block waits for a free CPU bus cycle so that the background access does not disturb the running application program. If a free cycle is not found within 128 clock cycles, the CPU is momentarily frozen so that the BDM can steal a cycle. When the BDM finds a free cycle, the operation does not intrude on normal CPU operation provided that it can be completed in a single cycle. However, if an operation requires multiple cycles the CPU is frozen until the operation is complete, even though the BDM found a free cycle.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 185
Chapter 6 Background Debug Module (BDMV4) Block Description
The BDM hardware commands are listed in Table 6-4.
Table 6-4. Hardware Commands
Command BACKGROUND ACK_ENABLE ACK_DISABLE READ_BD_BYTE READ_BD_WORD READ_BYTE READ_WORD WRITE_BD_BYTE WRITE_BD_WORD WRITE_BYTE WRITE_WORD Opcode (hex) 90 D5 D6 E4 EC E0 E8 C4 CC C0 C8 Data None None None 16-bit address 16-bit data out 16-bit address 16-bit data out 16-bit address 16-bit data out 16-bit address 16-bit data out 16-bit address 16-bit data in 16-bit address 16-bit data in 16-bit address 16-bit data in 16-bit address 16-bit data in Description Enter background mode if firmware is enabled. If enabled, an ACK will be issued when the part enters active background mode. Enable handshake. Issues an ACK pulse after the command is executed. Disable handshake. This command does not issue an ACK pulse. Read from memory with standard BDM firmware lookup table in map. Odd address data on low byte; even address data on high byte. Read from memory with standard BDM firmware lookup table in map. Must be aligned access. Read from memory with standard BDM firmware lookup table out of map. Odd address data on low byte; even address data on high byte. Read from memory with standard BDM firmware lookup table out of map. Must be aligned access. Write to memory with standard BDM firmware lookup table in map. Odd address data on low byte; even address data on high byte. Write to memory with standard BDM firmware lookup table in map. Must be aligned access. Write to memory with standard BDM firmware lookup table out of map. Odd address data on low byte; even address data on high byte. Write to memory with standard BDM firmware lookup table out of map. Must be aligned access.
NOTE: If enabled, ACK will occur when data is ready for transmission for all BDM READ commands and will occur after the write is complete for all BDM WRITE commands.
The READ_BD and WRITE_BD commands allow access to the BDM register locations. These locations are not normally in the system memory map but share addresses with the application in memory. To distinguish between physical memory locations that share the same address, BDM memory resources are enabled just for the READ_BD and WRITE_BD access cycle. This allows the BDM to access BDM locations unobtrusively, even if the addresses conflict with the application memory map.
6.4.4
Standard BDM Firmware Commands
Firmware commands are used to access and manipulate CPU resources. The system must be in active BDM to execute standard BDM firmware commands, see Section 6.4.2, "Enabling and Activating BDM." Normal instruction execution is suspended while the CPU executes the firmware located in the standard BDM firmware lookup table. The hardware command BACKGROUND is the usual way to activate BDM. As the system enters active BDM, the standard BDM firmware lookup table and BDM registers become visible in the on-chip memory map at 0xFF00-0xFFFF, and the CPU begins executing the standard BDM
MC3S12RG128 Data Sheet, Rev. 1.05 186 Freescale Semiconductor
Chapter 6 Background Debug Module (BDMV4) Block Description
firmware. The standard BDM firmware watches for serial commands and executes them as they are received. The firmware commands are shown in Table 6-5.
Table 6-5. Firmware Commands
Command1 READ_NEXT READ_PC READ_D READ_X READ_Y READ_SP WRITE_NEXT WRITE_PC WRITE_D WRITE_X WRITE_Y WRITE_SP GO GO_UNTIL2 TRACE1 TAGGO
1
Opcode (hex) 62 63 64 65 66 67 42 43 44 45 46 47 08 0C 10 18
Data 16-bit data out 16-bit data out 16-bit data out 16-bit data out 16-bit data out 16-bit data out 16-bit data in 16-bit data in 16-bit data in 16-bit data in 16-bit data in 16-bit data in None None None None
Description Increment X by 2 (X = X + 2), then read word X points to. Read program counter. Read D accumulator. Read X index register. Read Y index register. Read stack pointer. Increment X by 2 (X = X + 2), then write word to location pointed to by X. Write program counter. Write D accumulator. Write X index register. Write Y index register. Write stack pointer. Go to user program. If enabled, ACK will occur when leaving active background mode. Go to user program. If enabled, ACK will occur upon returning to active background mode. Execute one user instruction then return to active BDM. If enabled, ACK will occur upon returning to active background mode. Enable tagging and go to user program. There is no ACK pulse related to this command.
If enabled, ACK will occur when data is ready for transmission for all BDM READ commands and will occur after the write is complete for all BDM WRITE commands. 2 Both WAIT (with clocks to the S12 CPU core disabled) and STOP disable the ACK function. The GO_UNTIL command will not get an Acknowledge if one of these two CPU instructions occurs before the "UNTIL" instruction. This can be a problem for any instruction that uses ACK, but GO_UNTIL is a lot more difficult for the development tool to time-out.
6.4.5
BDM Command Structure
Hardware and firmware BDM commands start with an 8-bit opcode followed by a 16-bit address and/or a 16-bit data word depending on the command. All the read commands return 16 bits of data despite the byte or word implication in the command name. NOTE 8-bit reads return 16-bits of data, of which, only one byte will contain valid data. If reading an even address, the valid data will appear in the MSB. If reading an odd address, the valid data will appear in the LSB.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 187
Chapter 6 Background Debug Module (BDMV4) Block Description
NOTE 16-bit misaligned reads and writes are not allowed. If attempted, the BDM will ignore the least significant bit of the address and will assume an even address from the remaining bits. For hardware data read commands, the external host must wait 150 bus clock cycles after sending the address before attempting to obtain the read data. This is to be certain that valid data is available in the BDM shift register, ready to be shifted out. For hardware write commands, the external host must wait 150 bus clock cycles after sending the data to be written before attempting to send a new command. This is to avoid disturbing the BDM shift register before the write has been completed. The 150 bus clock cycle delay in both cases includes the maximum 128 cycle delay that can be incurred as the BDM waits for a free cycle before stealing a cycle. For firmware read commands, the external host should wait 44 bus clock cycles after sending the command opcode and before attempting to obtain the read data. This includes the potential of an extra 7 cycles when the access is external with a narrow bus access (+1 cycle) and / or a stretch (+1, 2, or 3 cycles), (7 cycles could be needed if both occur). The 44 cycle wait allows enough time for the requested data to be made available in the BDM shift register, ready to be shifted out. NOTE This timing has increased from previous BDM modules due to the new capability in which the BDM serial interface can potentially run faster than the bus. On previous BDM modules this extra time could be hidden within the serial time. For firmware write commands, the external host must wait 32 bus clock cycles after sending the data to be written before attempting to send a new command. This is to avoid disturbing the BDM shift register before the write has been completed. The external host should wait 64 bus clock cycles after a TRACE1 or GO command before starting any new serial command. This is to allow the CPU to exit gracefully from the standard BDM firmware lookup table and resume execution of the user code. Disturbing the BDM shift register prematurely may adversely affect the exit from the standard BDM firmware lookup table. NOTE If the bus rate of the target processor is unknown or could be changing, it is recommended that the ACK (acknowledge function) be used to indicate when an operation is complete. When using ACK, the delay times are automated. Figure 6-6 represents the BDM command structure. The command blocks illustrate a series of eight bit times starting with a falling edge. The bar across the top of the blocks indicates that the BKGD line idles in the high state. The time for an 8-bit command is 8 x 16 target clock cycles.1
1. Target clock cycles are cycles measured using the target MCU's serial clock rate. See Section 6.4.6, "BDM Serial Interface," and Section 6.3.1.1, "BDM Status Register (BDMSTS)," for information on how serial clock rate is selected. MC3S12RG128 Data Sheet, Rev. 1.05 188 Freescale Semiconductor
Chapter 6 Background Debug Module (BDMV4) Block Description
8 BITS AT 16 TC/BIT HARDWARE READ COMMAND
16 BITS AT 16 TC/BIT ADDRESS
150-BC DELAY
16 BITS AT 16 TC/BIT DATA 150-BC DELAY NEXT COMMAND
HARDWARE WRITE
COMMAND 44-BC DELAY
ADDRESS
DATA
NEXT COMMAND
FIRMWARE READ
COMMAND
DATA 32-BC DELAY
NEXT COMMAND
FIRMWARE WRITE
COMMAND 64-BC DELAY
DATA
NEXT COMMAND
GO, TRACE
COMMAND
NEXT COMMAND
BC = BUS CLOCK CYCLES TC = TARGET CLOCK CYCLES
Figure 6-6. BDM Command Structure
6.4.6
BDM Serial Interface
The BDM communicates with external devices serially via the BKGD pin. During reset, this pin is a mode select input which selects between normal and special modes of operation. After reset, this pin becomes the dedicated serial interface pin for the BDM. The BDM serial interface is timed using the clock selected by the CLKSW bit in the status register see Section 6.3.1.1, "BDM Status Register (BDMSTS)." This clock will be referred to as the target clock in the following explanation. The BDM serial interface uses a clocking scheme in which the external host generates a falling edge on the BKGD pin to indicate the start of each bit time. This falling edge is sent for every bit whether data is transmitted or received. Data is transferred most significant bit (MSB) first at 16 target clock cycles per bit. The interface times out if 512 clock cycles occur between falling edges from the host. The BKGD pin is a pseudo open-drain pin and has an weak on-chip active pull-up that is enabled at all times. It is assumed that there is an external pull-up and that drivers connected to BKGD do not typically drive the high level. Because R-C rise time could be unacceptably long, the target system and host provide brief driven-high (speedup) pulses to drive BKGD to a logic 1. The source of this speedup pulse is the host for transmit cases and the target for receive cases. The timing for host-to-target is shown in Figure 6-7 and that of target-to-host in Figure 6-8 and Figure 6-9. All four cases begin when the host drives the BKGD pin low to generate a falling edge. Because the host and target are operating from separate clocks, it can take the target system up to one full clock cycle to recognize this edge. The target measures delays from this perceived start of the bit time while the host measures delays from the point it actually drove BKGD low to start the bit up to one target clock cycle
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 189
Chapter 6 Background Debug Module (BDMV4) Block Description
earlier. Synchronization between the host and target is established in this manner at the start of every bit time. Figure 6-7 shows an external host transmitting a logic 1 and transmitting a logic 0 to the BKGD pin of a target system. The host is asynchronous to the target, so there is up to a one clock-cycle delay from the host-generated falling edge to where the target recognizes this edge as the beginning of the bit time. Ten target clock cycles later, the target senses the bit level on the BKGD pin. Internal glitch detect logic requires the pin be driven high no later that eight target clock cycles after the falling edge for a logic 1 transmission. Because the host drives the high speedup pulses in these two cases, the rising edges look like digitally driven signals.
CLOCK TARGET SYSTEM
HOST TRANSMIT 1
HOST TRANSMIT 0 PERCEIVED START OF BIT TIME 10 CYCLES SYNCHRONIZATION UNCERTAINTY TARGET SENSES BIT EARLIEST START OF NEXT BIT
Figure 6-7. BDM Host-to-Target Serial Bit Timing
The receive cases are more complicated. Figure 6-8 shows the host receiving a logic 1 from the target system. Because the host is asynchronous to the target, there is up to one clock-cycle delay from the host-generated falling edge on BKGD to the perceived start of the bit time in the target. The host holds the BKGD pin low long enough for the target to recognize it (at least two target clock cycles). The host must release the low drive before the target drives a brief high speedup pulse seven target clock cycles after the perceived start of the bit time. The host should sample the bit level about 10 target clock cycles after it started the bit time.
MC3S12RG128 Data Sheet, Rev. 1.05 190 Freescale Semiconductor
Chapter 6 Background Debug Module (BDMV4) Block Description
CLOCK TARGET SYSTEM
HOST DRIVE TO BKGD PIN TARGET SYSTEM SPEEDUP PULSE PERCEIVED START OF BIT TIME R-C RISE BKGD PIN
HIGH-IMPEDANCE
HIGH-IMPEDANCE
HIGH-IMPEDANCE
10 CYCLES 10 CYCLES EARLIEST START OF NEXT BIT
HOST SAMPLES BKGD PIN
Figure 6-8. BDM Target-to-Host Serial Bit Timing (Logic 1)
Figure 6-9 shows the host receiving a logic 0 from the target. Because the host is asynchronous to the target, there is up to a one clock-cycle delay from the host-generated falling edge on BKGD to the start of the bit time as perceived by the target. The host initiates the bit time but the target finishes it. Because the target wants the host to receive a logic 0, it drives the BKGD pin low for 13 target clock cycles then briefly drives it high to speed up the rising edge. The host samples the bit level about 10 target clock cycles after starting the bit time.
CLOCK TARGET SYS.
HOST DRIVE TO BKGD PIN TARGET SYS. DRIVE AND SPEEDUP PULSE PERCEIVED START OF BIT TIME BKGD PIN
HIGH-IMPEDANCE SPEEDUP PULSE
10 CYCLES 10 CYCLES EARLIEST START OF NEXT BIT
HOST SAMPLES BKGD PIN
Figure 6-9. BDM Target-to-Host Serial Bit Timing (Logic 0)
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 191
Chapter 6 Background Debug Module (BDMV4) Block Description
6.4.7
Serial Interface Hardware Handshake Protocol
BDM commands that require CPU execution are ultimately treated at the MCU bus rate. Because the BDM clock source can be asynchronously related to the bus frequency, when CLKSW = 0, it is very helpful to provide a handshake protocol in which the host could determine when an issued command is executed by the CPU. The alternative is to always wait the amount of time equal to the appropriate number of cycles at the slowest possible rate the clock could be running. This sub-section will describe the hardware handshake protocol. The hardware handshake protocol signals to the host controller when an issued command was successfully executed by the target. This protocol is implemented by a 16 serial clock cycle low pulse followed by a brief speedup pulse in the BKGD pin. This pulse is generated by the target MCU when a command, issued by the host, has been successfully executed (see Figure 6-10). This pulse is referred to as the ACK pulse. After the ACK pulse has finished: the host can start the bit retrieval if the last issued command was a read command, or start a new command if the last command was a write command or a control command (BACKGROUND, GO, GO_UNTIL, or TRACE1). The ACK pulse is not issued earlier than 32 serial clock cycles after the BDM command was issued. The end of the BDM command is assumed to be the 16th tick of the last bit. This minimum delay assures enough time for the host to perceive the ACK pulse. Note also that, there is no upper limit for the delay between the command and the related ACK pulse, because the command execution depends upon the CPU bus frequency, which in some cases could be very slow compared to the serial communication rate. This protocol allows a great flexibility for the POD designers, because it does not rely on any accurate time measurement or short response time to any event in the serial communication.
BDM CLOCK (TARGET MCU)
16 CYCLES TARGET TRANSMITS ACK PULSE HIGH-IMPEDANCE 32 CYCLES SPEEDUP PULSE MINIMUM DELAY FROM THE BDM COMMAND BKGD PIN EARLIEST START OF NEXT BIT HIGH-IMPEDANCE
16th TICK OF THE LAST COMMAD BIT
Figure 6-10. Target Acknowledge Pulse (ACK)
NOTE If the ACK pulse was issued by the target, the host assumes the previous command was executed. If the CPU enters WAIT or STOP prior to executing a hardware command, the ACK pulse will not be issued meaning that the BDM command was not executed. After entering wait or stop mode, the BDM command is no longer pending.
MC3S12RG128 Data Sheet, Rev. 1.05 192 Freescale Semiconductor
Chapter 6 Background Debug Module (BDMV4) Block Description
Figure 6-11 shows the ACK handshake protocol in a command level timing diagram. The READ_BYTE instruction is used as an example. First, the 8-bit instruction opcode is sent by the host, followed by the address of the memory location to be read. The target BDM decodes the instruction. A bus cycle is grabbed (free or stolen) by the BDM and it executes the READ_BYTE operation. Having retrieved the data, the BDM issues an ACK pulse to the host controller, indicating that the addressed byte is ready to be retrieved. After detecting the ACK pulse, the host initiates the byte retrieval process. Note that data is sent in the form of a word and the host needs to determine which is the appropriate byte based on whether the address was odd or even.
TARGET HOST NEW BDM COMMAND HOST BDM ISSUES THE ACK PULSE (OUT OF SCALE) BDM EXECUTES THE READ_BYTE COMMAND TARGET
BKGD PIN
READ_BYTE HOST
BYTE ADDRESS TARGET
(2) BYTES ARE RETRIEVED
BDM DECODES THE COMMAND
Figure 6-11. Handshake Protocol at Command Level
Differently from the normal bit transfer (where the host initiates the transmission), the serial interface ACK handshake pulse is initiated by the target MCU by issuing a falling edge in the BKGD pin. The hardware handshake protocol in Figure 6-10 specifies the timing when the BKGD pin is being driven, so the host should follow this timing constraint in order to avoid the risk of an electrical conflict in the BKGD pin. NOTE The only place the BKGD pin can have an electrical conflict is when one side is driving low and the other side is issuing a speedup pulse (high). Other "highs" are pulled rather than driven. However, at low rates the time of the speedup pulse can become lengthy and so the potential conflict time becomes longer as well. The ACK handshake protocol does not support nested ACK pulses. If a BDM command is not acknowledge by an ACK pulse, the host needs to abort the pending command first in order to be able to issue a new BDM command. When the CPU enters WAIT or STOP while the host issues a command that requires CPU execution (e.g., WRITE_BYTE), the target discards the incoming command due to the WAIT or STOP being detected. Therefore, the command is not acknowledged by the target, which means that the ACK pulse will not be issued in this case. After a certain time the host should decide to abort the ACK sequence in order to be free to issue a new command. Therefore, the protocol should provide a mechanism in which a command, and therefore a pending ACK, could be aborted. NOTE Differently from a regular BDM command, the ACK pulse does not provide a time out. This means that in the case of a WAIT or STOP instruction being executed, the ACK would be prevented from being issued. If not aborted, the ACK would remain pending indefinitely. See the handshake abort procedure described in Section 6.4.8, "Hardware Handshake Abort Procedure."
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 193
Chapter 6 Background Debug Module (BDMV4) Block Description
6.4.8
Hardware Handshake Abort Procedure
The abort procedure is based on the SYNC command. In order to abort a command, which had not issued the corresponding ACK pulse, the host controller should generate a low pulse in the BKGD pin by driving it low for at least 128 serial clock cycles and then driving it high for one serial clock cycle, providing a speedup pulse. By detecting this long low pulse in the BKGD pin, the target executes the SYNC protocol, see Section 6.4.9, "SYNC -- Request Timed Reference Pulse," and assumes that the pending command and therefore the related ACK pulse, are being aborted. Therefore, after the SYNC protocol has been completed the host is free to issue new BDM commands. Although it is not recommended, the host could abort a pending BDM command by issuing a low pulse in the BKGD pin shorter than 128 serial clock cycles, which will not be interpreted as the SYNC command. The ACK is actually aborted when a falling edge is perceived by the target in the BKGD pin. The short abort pulse should have at least 4 clock cycles keeping the BKGD pin low, in order to allow the falling edge to be detected by the target. In this case, the target will not execute the SYNC protocol but the pending command will be aborted along with the ACK pulse. The potential problem with this abort procedure is when there is a conflict between the ACK pulse and the short abort pulse. In this case, the target may not perceive the abort pulse. The worst case is when the pending command is a read command (i.e., READ_BYTE). If the abort pulse is not perceived by the target the host will attempt to send a new command after the abort pulse was issued, while the target expects the host to retrieve the accessed memory byte. In this case, host and target will run out of synchronism. However, if the command to be aborted is not a read command the short abort pulse could be used. After a command is aborted the target assumes the next falling edge, after the abort pulse, is the first bit of a new BDM command. NOTE The details about the short abort pulse are being provided only as a reference for the reader to better understand the BDM internal behavior. It is not recommended that this procedure be used in a real application. Because the host knows the target serial clock frequency, the SYNC command (used to abort a command) does not need to consider the lower possible target frequency. In this case, the host could issue a SYNC very close to the 128 serial clock cycles length. Providing a small overhead on the pulse length in order to assure the SYNC pulse will not be misinterpreted by the target. See Section 6.4.9, "SYNC -- Request Timed Reference Pulse." Figure 6-12 shows a SYNC command being issued after a READ_BYTE, which aborts the READ_BYTE command. Note that, after the command is aborted a new command could be issued by the host computer. NOTE Figure 6-12 does not represent the signals in a true timing scale
MC3S12RG128 Data Sheet, Rev. 1.05 194 Freescale Semiconductor
Chapter 6 Background Debug Module (BDMV4) Block Description
READ_BYTE CMD IS ABORTED BY THE SYNC REQUEST (OUT OF SCALE)
SYNC RESPONSE FROM THE TARGET (OUT OF SCALE)
BKGD PIN
READ_BYTE HOST
MEMORY ADDRESS TARGET
READ_STATUS HOST TARGET
NEW BDM COMMAND HOST TARGET
BDM DECODE AND STARTS TO EXECUTES THE READ_BYTE CMD
NEW BDM COMMAND
Figure 6-12. ACK Abort Procedure at the Command Level
Figure 6-13 shows a conflict between the ACK pulse and the SYNC request pulse. This conflict could occur if a POD device is connected to the target BKGD pin and the target is already in debug active mode. Consider that the target CPU is executing a pending BDM command at the exact moment the POD is being connected to the BKGD pin. In this case, an ACK pulse is issued along with the SYNC command. In this case, there is an electrical conflict between the ACK speedup pulse and the SYNC pulse. Because this is not a probable situation, the protocol does not prevent this conflict from happening.
AT LEAST 128 CYCLES BDM CLOCK (TARGET MCU) ACK PULSE TARGET MCU DRIVES TO BKGD PIN HOST DRIVES SYNC TO BKGD PIN HOST AND TARGET DRIVE TO BKGD PIN HOST SYNC REQUEST PULSE BKGD PIN HIGH-IMPEDANCE ELECTRICAL CONFLICT
SPEEDUP PULSE
16 CYCLES
Figure 6-13. ACK Pulse and SYNC Request Conflict
NOTE This information is being provided so that the MCU integrator will be aware that such a conflict could eventually occur. The hardware handshake protocol is enabled by the ACK_ENABLE and disabled by the ACK_DISABLE BDM commands. This provides backwards compatibility with the existing POD devices which are not able to execute the hardware handshake protocol. It also allows for new POD devices, that support the hardware handshake protocol, to freely communicate with the target device. If desired, without the need for waiting for the ACK pulse.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 195
Chapter 6 Background Debug Module (BDMV4) Block Description
The commands are described as follows: * ACK_ENABLE -- enables the hardware handshake protocol. The target will issue the ACK pulse when a CPU command is executed by the CPU. The ACK_ENABLE command itself also has the ACK pulse as a response. * ACK_DISABLE -- disables the ACK pulse protocol. In this case, the host needs to use the worst case delay time at the appropriate places in the protocol. The default state of the BDM after reset is hardware handshake protocol disabled. All the read commands will ACK (if enabled) when the data bus cycle has completed and the data is then ready for reading out by the BKGD serial pin. All the write commands will ACK (if enabled) after the data has been received by the BDM through the BKGD serial pin and when the data bus cycle is complete. See Section 6.4.3, "BDM Hardware Commands," and Section 6.4.4, "Standard BDM Firmware Commands," for more information on the BDM commands. The ACK_ENABLE sends an ACK pulse when the command has been completed. This feature could be used by the host to evaluate if the target supports the hardware handshake protocol. If an ACK pulse is issued in response to this command, the host knows that the target supports the hardware handshake protocol. If the target does not support the hardware handshake protocol the ACK pulse is not issued. In this case, the ACK_ENABLE command is ignored by the target because it is not recognized as a valid command. The BACKGROUND command will issue an ACK pulse when the CPU changes from normal to background mode. The ACK pulse related to this command could be aborted using the SYNC command. The GO command will issue an ACK pulse when the CPU exits from background mode. The ACK pulse related to this command could be aborted using the SYNC command. The GO_UNTIL command is equivalent to a GO command with exception that the ACK pulse, in this case, is issued when the CPU enters into background mode. This command is an alternative to the GO command and should be used when the host wants to trace if a breakpoint match occurs and causes the CPU to enter active background mode. Note that the ACK is issued whenever the CPU enters BDM, which could be caused by a breakpoint match or by a BGND instruction being executed. The ACK pulse related to this command could be aborted using the SYNC command. The TRACE1 command has the related ACK pulse issued when the CPU enters background active mode after one instruction of the application program is executed. The ACK pulse related to this command could be aborted using the SYNC command. The TAGGO command will not issue an ACK pulse because this would interfere with the tagging function shared on the same pin.
MC3S12RG128 Data Sheet, Rev. 1.05 196 Freescale Semiconductor
Chapter 6 Background Debug Module (BDMV4) Block Description
6.4.9
SYNC -- Request Timed Reference Pulse
The SYNC command is unlike other BDM commands because the host does not necessarily know the correct communication speed to use for BDM communications until after it has analyzed the response to the SYNC command. To issue a SYNC command, the host should perform the following steps: 1. Drive the BKGD pin low for at least 128 cycles at the lowest possible BDM serial communication frequency (the lowest serial communication frequency is determined by the crystal oscillator or the clock chosen by CLKSW.) 2. Drive BKGD high for a brief speedup pulse to get a fast rise time (this speedup pulse is typically one cycle of the host clock.) 3. Remove all drive to the BKGD pin so it reverts to high impedance. 4. Listen to the BKGD pin for the sync response pulse. Upon detecting the SYNC request from the host, the target performs the following steps: 1. Discards any incomplete command received or bit retrieved. 2. Waits for BKGD to return to a logic 1. 3. Delays 16 cycles to allow the host to stop driving the high speedup pulse. 4. Drives BKGD low for 128 cycles at the current BDM serial communication frequency. 5. Drives a one-cycle high speedup pulse to force a fast rise time on BKGD. 6. Removes all drive to the BKGD pin so it reverts to high impedance. The host measures the low time of this 128 cycle SYNC response pulse and determines the correct speed for subsequent BDM communications. Typically, the host can determine the correct communication speed within a few percent of the actual target speed and the communication protocol can easily tolerate speed errors of several percent. As soon as the SYNC request is detected by the target, any partially received command or bit retrieved is discarded. This is referred to as a soft-reset, equivalent to a time-out in the serial communication. After the SYNC response, the target will consider the next falling edge (issued by the host) as the start of a new BDM command or the start of new SYNC request. Another use of the SYNC command pulse is to abort a pending ACK pulse. The behavior is exactly the same as in a regular SYNC command. Note that one of the possible causes for a command to not be acknowledged by the target is a host-target synchronization problem. In this case, the command may not have been understood by the target and so an ACK response pulse will not be issued.
6.4.10
Instruction Tracing
When a TRACE1 command is issued to the BDM in active BDM, the CPU exits the standard BDM firmware and executes a single instruction in the user code. As soon as this has occurred, the CPU is forced to return to the standard BDM firmware and the BDM is active and ready to receive a new command. If the TRACE1 command is issued again, the next user instruction will be executed. This facilitates stepping or tracing through the user code one instruction at a time.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 197
Chapter 6 Background Debug Module (BDMV4) Block Description
If an interrupt is pending when a TRACE1 command is issued, the interrupt stacking operation occurs but no user instruction is executed. Upon return to standard BDM firmware execution, the program counter points to the first instruction in the interrupt service routine.
6.4.11
Instruction Tagging
The instruction queue and cycle-by-cycle CPU activity are reconstructible in real time or from trace history that is captured by a logic analyzer. However, the reconstructed queue cannot be used to stop the CPU at a specific instruction. This is because execution already has begun by the time an operation is visible outside the system. A separate instruction tagging mechanism is provided for this purpose. The tag follows program information as it advances through the instruction queue. When a tagged instruction reaches the head of the queue, the CPU enters active BDM rather than executing the instruction. NOTE Tagging is disabled when BDM becomes active and BDM serial commands are not processed while tagging is active. Executing the BDM TAGGO command configures two system pins for tagging. The TAGLO signal shares a pin with the LSTRB signal, and the TAGHI signal shares a pin with the BKGD signal. Table 6-6 shows the functions of the two tagging pins. The pins operate independently, that is the state of one pin does not affect the function of the other. The presence of logic level 0 on either pin at the fall of the external clock (ECLK) performs the indicated function. High tagging is allowed in all modes. Low tagging is allowed only when low strobe is enabled (LSTRB is allowed only in wide expanded modes and emulation expanded narrow mode).
Table 6-6. Tag Pin Function
TAGHI 1 1 0 0 TAGLO 1 0 1 0 Tag No tag Low byte High byte Both bytes
6.4.12
Serial Communication Time-Out
The host initiates a host-to-target serial transmission by generating a falling edge on the BKGD pin. If BKGD is kept low for more than 128 target clock cycles, the target understands that a SYNC command was issued. In this case, the target will keep waiting for a rising edge on BKGD in order to answer the SYNC request pulse. If the rising edge is not detected, the target will keep waiting forever without any time-out limit. Consider now the case where the host returns BKGD to logic one before 128 cycles. This is interpreted as a valid bit transmission, and not as a SYNC request. The target will keep waiting for another falling edge marking the start of a new bit. If, however, a new falling edge is not detected by the target within 512 clock cycles since the last falling edge, a time-out occurs and the current command is discarded without affecting memory or the operating mode of the MCU. This is referred to as a soft-reset.
MC3S12RG128 Data Sheet, Rev. 1.05 198 Freescale Semiconductor
Chapter 6 Background Debug Module (BDMV4) Block Description
If a read command is issued but the data is not retrieved within 512 serial clock cycles, a soft-reset will occur causing the command to be disregarded. The data is not available for retrieval after the time-out has occurred. This is the expected behavior if the handshake protocol is not enabled. However, consider the behavior where the BDC is running in a frequency much greater than the CPU frequency. In this case, the command could time out before the data is ready to be retrieved. In order to allow the data to be retrieved even with a large clock frequency mismatch (between BDC and CPU) when the hardware handshake protocol is enabled, the time out between a read command and the data retrieval is disabled. Therefore, the host could wait for more then 512 serial clock cycles and continue to be able to retrieve the data from an issued read command. However, as soon as the handshake pulse (ACK pulse) is issued, the time-out feature is re-activated, meaning that the target will time out after 512 clock cycles. Therefore, the host needs to retrieve the data within a 512 serial clock cycles time frame after the ACK pulse had been issued. After that period, the read command is discarded and the data is no longer available for retrieval. Any falling edge of the BKGD pin after the time-out period is considered to be a new command or a SYNC request. Note that whenever a partially issued command, or partially retrieved data, has occurred the time out in the serial communication is active. This means that if a time frame higher than 512 serial clock cycles is observed between two consecutive negative edges and the command being issued or data being retrieved is not complete, a soft-reset will occur causing the partially received command or data retrieved to be disregarded. The next falling edge of the BKGD pin, after a soft-reset has occurred, is considered by the target as the start of a new BDM command, or the start of a SYNC request pulse.
6.4.13
Operation in Wait Mode
The BDM cannot be used in wait mode if the system disables the clocks to the BDM. There is a clearing mechanism associated with the WAIT instruction when the clocks to the BDM (CPU core platform) are disabled. As the clocks restart from wait mode, the BDM receives a soft reset (clearing any command in progress) and the ACK function will be disabled. This is a change from previous BDM modules.
6.4.14
Operation in Stop Mode
The BDM is completely shutdown in stop mode. There is a clearing mechanism associated with the STOP instruction. STOP must be enabled and the part must go into stop mode for this to occur. As the clocks restart from stop mode, the BDM receives a soft reset (clearing any command in progress) and the ACK function will be disabled. This is a change from previous BDM modules.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 199
Chapter 6 Background Debug Module (BDMV4) Block Description
MC3S12RG128 Data Sheet, Rev. 1.05 200 Freescale Semiconductor
Chapter 7 Breakpoint Module (BKPV1) Block Description
7.1 Introduction
This block guide describes the functionality of the Breakpoint (BKP) sub-block of the HCS12 Core Platform. The Breakpoint contains three main sub-blocks: * Register Block * Compare Block * Control Block The Register Block consists of the eight registers that make up the Breakpoint register space. The Compare Block performs all required address and data signal comparisons. The Control Block generates the signals for the CPU for the tag high, tag low, force SWI, and force BDM functions. In addition, it generates the register read and write signals and the comparator block enable signals. NOTE There is a two-cycle latency for address compares and for forces, a two-cycle latency for write data compares, and a three-cycle latency for read data compares. The Breakpoint sub-block of the Core Platform provides for hardware breakpoints that are used to debug software on the CPU by comparing actual address and data values to predetermine data in setup registers. A successful comparison will place the CPU in Background Debug Mode or initiate a software interrupt (SWI). The choice between Background Debug Mode and SWI is software selectable. There are two types of breakpoints, forced and tagged. Forced breakpoints occur at the next instruction boundary if a match occurs and tagged breakpoints allow for breaking just before a specific instruction executes. Tagged breakpoints will only occur on addresses of program fetches. Tagging on data is not allowed; however, if this occurs nothing will happen within the BKP. The range function of the BKP allows breaking within a 256-byte address range. The page function allows breaking within expanded memory. In data matching operations, 8-bit or 16-bit data can be matched. Forced breakpoints are mainly used on a read or a write cycle, but can be used on any bus cycle.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 201
Chapter 7 Breakpoint Module (BKPV1) Block Description
7.1.1
*
Features
Full or Dual Breakpoint Mode -- Compare on address and data (Full) -- Compare on either of two addresses (Dual) BDM or SWI Breakpoint -- Enter BDM on breakpoint (BDM) -- Execute SWI on breakpoint (SWI) Tagged or Forced Breakpoint -- Break just before a specific instruction will begin execution (TAG) -- Break on the first instruction boundary after a match occurs (Force) Single, Range, or Page address compares -- Compare on address (Single) -- Compare on address 256 byte (Range) -- Compare on any 16K Page (Page) Compare address on read or write on forced breakpoints High and/or low byte data compares
*
*
*
* *
7.1.2
Modes of Operation
The Breakpoint sub-block contains two modes of operation: 1. Dual Address Mode, where a match on either of two addresses will cause the system to enter Background Debug Mode or initiate a Software Interrupt (SWI). 2. Full Breakpoint Mode, where a match on address and data will cause the system to enter Background Debug Mode or initiate a Software Interrupt (SWI).
7.1.3
Block Diagram
A block diagram of the Breakpoint sub-block is shown in Figure 7-1.
7.2
External Signal Description
The breakpoint sub-module relies on the external bus interface (generally the MEBI) when the breakpoint is matching on the external bus. The tag pins in Table 7-1 (part of the MEBI) may also be a part of the breakpoint operation.
Table 7-1. External System Pins Associated With Breakpoint and MEBI
Pin Name BKGD/MODC/ TAGHI PE3/LSTRB/ TAGLO Pin Functions TAGHI TAGLO Description When instruction tagging is on, a 0 at the falling edge of PE4/ECLK tags the high half of the instruction word being read into the instruction queue. In expanded wide mode or emulation narrow modes, when instruction tagging is on and low strobe is enabled, a 0 at the falling edge of PE4/ECLK tags the low half of the instruction word being read into the instruction queue.
MC3S12RG128 Data Sheet, Rev. 1.05 202 Freescale Semiconductor
Chapter 7 Breakpoint Module (BKPV1) Block Description CLOCKS AND CONTROL SIGNALS CONTROL BLOCK BREAKPOINT MODES AND GENERATION OF SWI, FORCE BDM, AND TAGS CONTROL SIGNALS RESULTS SIGNALS CONTROL BITS READ/WRITE CONTROL BKP CONTROL SIGNALS
......
......
EXPANSION ADDRESS ADDRESS WRITE DATA READ DATA
REGISTER BLOCK BKPCT0
BKPCT1 COMPARE BLOCK BKP READ DATA BUS WRITE DATA BUS BKP0X COMPARATOR EXPANSION ADDRESSES
BKP0H
COMPARATOR
ADDRESS HIGH
ADDRESS LOW BKP0L COMPARATOR EXPANSION ADDRESSES BKP1X COMPARATOR DATA HIGH BKP1H COMPARATOR DATA/ADDRESS HIGH MUX DATA/ADDRESS LOW MUX READ DATA HIGH COMPARATOR READ DATA LOW COMPARATOR ADDRESS HIGH DATA LOW ADDRESS LOW
BKP1L
COMPARATOR
Figure 7-1. Breakpoint Block Diagram
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 203
Chapter 7 Breakpoint Module (BKPV1) Block Description
7.3
Memory Map and Registers
This section provides a detailed description of all memory and registers.
7.3.1
Module Memory Map
A summary of the registers associated with the Breakpoint sub-block is shown in Figure 7-2. Detailed descriptions of the registers and bits are given in the subsections that follow.
Address 0x0028 Name R BKPCT0 W R 0x0029 BKPCT1 W R 0x002A BKP0X W R 0x002B BKP0H W R 0x002C BKP0L W R 0x002D BKP1X W R 0x002E BKP1H W R 0x002F BKP1L W = Unimplemented or Reserved X = Indeterminate Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 0 0 BK1V5 BK1V4 BK1V3 BK1V2 BK1V1 BK1V0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 0 0 BK0V5 BK0V4 BK0V3 BK0V2 BK0V1 BK0V0 BK0MBH BK0MBL BK1MBH BK1MBL BK0RWE BK0RW BK1RWE BK1RW BKEN BKFULL BKBDM BKTAG Bit 7 6 5 4 3 0 2 0 1 0 Bit 0 0
Figure 7-2. BKP Register Summary
MC3S12RG128 Data Sheet, Rev. 1.05 204 Freescale Semiconductor
Chapter 7 Breakpoint Module (BKPV1) Block Description
7.3.1.1
Breakpoint Control Register 0 (BKPCT0)
Module Base + 0x0028
7 6 5 4 3 2 1 0
R BKEN W Reset 0 0 0 0 BKFULL BKBDM BKTAG
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 7-3. Breakpoint Control Register 0 (BKPCT0)
Read: Anytime Write: Anytime This register is used to set the breakpoint modes.
Table 7-2. BKPCT0 Field Descriptions
Field 7 BKEN 6 BKFULL 4 BKBDM Description Breakpoint Enable -- This bit enables the module 0 Breakpoints disabled 1 Breakpoints enabled, breakpoint mode is determined by bits BKFULL, BKBDM, and BKTAG Full Breakpoint Mode Enable -- This bit controls whether the breakpoint module is in Dual Mode or Full Mode 0 Dual Address Mode enabled 1 Full Breakpoint Mode enabled Breakpoint Background Debug Mode Enable -- This bit determines if the breakpoint causes the system to enter Background Debug Mode (BDM) or initiate a Software Interrupt (SWI) 0 Go to Software Interrupt on a compare 1 Go to BDM on a compare Breakpoint on Tag -- This bit controls whether the breakpoint will cause a break on the next instruction boundary (force) or on a match that will be an executable opcode (tagged). Non-executed opcodes cannot cause a tagged breakpoint 0 On match, break at the next instruction boundary (force) 1 On match, break if the match is an instruction that will be executed (tagged)
4 BKTAG
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 205
Chapter 7 Breakpoint Module (BKPV1) Block Description
7.3.1.2
Breakpoint Control Register 1 (BKPCT1)
Module Base + 0x0029
7 6 5 4 3 2 1 0
R BK0MBH W Reset 0 0 0 0 0 0 0 0 BK0MBL BK1MBH BK1MBL BK0RWE BK0RW BK1RWE BK1RW
Figure 7-4. Breakpoint Control Register 1 (BKPCT1)
Read: Anytime Write: Anytime This register is used to configure the functionality of the Breakpoint sub-block within the Core.
Table 7-3. BKPCT1 Field Descriptions
Field 7-6 BK0MBH BK0MBL Description Breakpoint Mask High Byte and Low Byte for First Address -- In Dual or Full Mode, these bits may be used to mask (disable) the comparison of the high and low bytes of the first address breakpoint. The functionality is as given in Table 7-4 below. The x:0 case is for a Full Address Compare. When a program page is selected, the full address compare will be based on bits for a 20-bit compare. The registers used for the compare are {BKP0X[5:0], BKP0H[5:0], BKP0L[7:0]}. When a program page is not selected, the full address compare will be based on bits for a 16-bit compare. The registers used for the compare are {BKP0H[7:0], BKP0L[7:0]}. The 1:0 case is not sensible because it would ignore the high order address and compare the low order and expansion addresses. Logic forces this case to compare all address lines (effectively ignoring the BK0MBH control bit). The 1:1 case is useful for triggering a breakpoint on any access to a particular expansion page. This only makes sense if a program page is being accessed so that the breakpoint trigger will occur only if BKP0X compares. 5-4 BK1MBH BK1MBL Breakpoint Mask High Byte and Low Byte of Data (Second Address) -- In Dual Mode, these bits may be used to mask (disable) the comparison of the high and/or low bytes of the second address breakpoint. The functionality is as given in Table 7-5. The x:0 case is for a Full Address Compare. When a program page is selected, the full address compare will be based on bits for a 20-bit compare. The registers used for the compare are {BKP1X[5:0], BKP1H[5:0], BKP1L[7:0]}. When a program page is not selected, the full address compare will be based on bits for a 16-bit compare. The registers used for the compare are {BKP1H[7:0], BKP1L[7:0]}. The 1:0 case is not sensible because it would ignore the high order address and compare the low order and expansion addresses. Logic forces this case to compare all address lines (effectively ignoring the BK1MBH control bit). The 1:1 case is useful for triggering a breakpoint on any access to a particular expansion page. This only makes sense if a program page is being accessed so that the breakpoint trigger will occur only if BKP1X compares. In Full Mode, these bits may be used to mask (disable) the comparison of the high and/or low bytes of the data breakpoint. The functionality is as given in Table 7-6. 3 BK0RWE R/W Compare Enable -- Enables the comparison of the R/W signal for first address breakpoint. This bit is not useful in tagged breakpoints. 0 R/W is not used in the comparisons 1 R/W is used in comparisons
MC3S12RG128 Data Sheet, Rev. 1.05 206 Freescale Semiconductor
Chapter 7 Breakpoint Module (BKPV1) Block Description
Table 7-3. BKPCT1 Field Descriptions (continued)
Field 2 BK0RW Description R/W Compare Value -- When BK0RWE = 1, this bit determines the type of bus cycle to match on first address breakpoint. When BK0RWE = 0, this bit has no effect. 0 Write cycle will be matched 1 Read cycle will be matched R/W Compare Enable -- In Dual Mode, this bit enables the comparison of the R/W signal to further specify what causes a match for the second address breakpoint. This bit is not useful on tagged breakpoints or in Full Mode and is therefore a don't care. 0 R/W is not used in comparisons 1 R/W is used in comparisons R/W Compare Value -- When BK1RWE = 1, this bit determines the type of bus cycle to match on the second address breakpoint.When BK1RWE = 0, this bit has no effect. 0 Write cycle will be matched 1 Read cycle will be matched
1 BK1RWE
0 BK1RW
Table 7-4. Breakpoint Mask Bits for First Address
BK0MBH:BK0MBL x:0 0:1 1:1
1
Address Compare Full address compare 256 byte address range 16K byte address range
BKP0X Yes1 Yes1 Yes
1
BKP0H Yes Yes No
BKP0L Yes No No
If page is selected.
Table 7-5. Breakpoint Mask Bits for Second Address (Dual Mode)
BK1MBH:BK1MBL x:0 0:1 1:1
1
Address Compare Full address compare 256 byte address range 16K byte address range
BKP1X Yes1 Yes1 Yes
1
BKP1H Yes Yes No
BKP1L Yes No No
If page is selected.
Table 7-6. Breakpoint Mask Bits for Data Breakpoints (Full Mode)
BK1MBH:BK1MBL 0:0 0:1 1:0 1:1
1
Data Compare High and low byte compare High byte Low byte No compare
BKP1X No1 No
1
BKP1H Yes Yes No No
BKP1L Yes No Yes No
No1 No
1
Expansion addresses for breakpoint 1 are not available in this mode.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 207
Chapter 7 Breakpoint Module (BKPV1) Block Description
7.3.1.3
Breakpoint First Address Expansion Register (BKP0X)
Module Base + 0x002A
7 6 5 4 3 2 1 0
R W Reset
0
0 BK0V5 BK0V4 0 BK0V3 0 BK0V2 0 BK0V1 0 BK0V0 0
0
0
0
= Unimplemented or Reserved
Figure 7-5. Breakpoint First Address Expansion Register (BKP0X)
Read: Anytime Write: Anytime This register contains the data to be matched against expansion address lines for the first address breakpoint when a page is selected.
Table 7-7. BKP0X Field Descriptions
Field 5-0 BK0V[5:0] Description BK0V Bits -- Value of first breakpoint address to be matched in memory expansion space.
7.3.1.4
Breakpoint First Address High Byte Register (BKP0H)
Module Base + 0x002B
7 6 5 4 3 2 1 0
R Bit 15 W Reset 0 0 0 0 0 0 0 0 14 13 12 11 10 9 Bit 8
Figure 7-6. Breakpoint First Address High Byte Register (BKP0H)
Read: Anytime Write: Anytime This register is used to set the breakpoint when compared against the high byte of the address.
MC3S12RG128 Data Sheet, Rev. 1.05 208 Freescale Semiconductor
Chapter 7 Breakpoint Module (BKPV1) Block Description
7.3.1.5
Breakpoint First Address Low Byte Register (BKP0L)
Module Base + 0x002C
7 6 5 4 3 2 1 0
R Bit 7 W Reset 0 0 0 0 0 0 0 0 6 5 4 3 2 1 Bit 0
Figure 7-7. Breakpoint First Address Low Byte Register (BKP0L)
Read: Anytime Write: Anytime This register is used to set the breakpoint when compared against the low byte of the address.
7.3.1.6
Breakpoint Second Address Expansion Register (BKP1X)
Module Base + 0x002D
7 6 5 4 3 2 1 0
R W Reset
0
0 BK1V5 BK1V4 0 BK1V3 0 BK1V2 0 BK1V1 0 BK1V0 0
0
0
0
= Unimplemented or Reserved
Figure 7-8. Breakpoint Second Address Expansion Register (BKP1X)
Read: Anytime Write: Anytime In Dual Mode, this register contains the data to be matched against expansion address lines for the second address breakpoint when a page is selected. In Full Mode, this register is not used.
Table 7-8. BXP1X Field Descriptions
Field 5-0 BK1V[5:0] Description BK1V Bits -- Value of first breakpoint address to be matched in memory expansion space.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 209
Chapter 7 Breakpoint Module (BKPV1) Block Description
7.3.1.7
Breakpoint Data (Second Address) High Byte Register (BKP1H)
Module Base + 0x002E
7 6 5 4 3 2 1 0
R Bit 15 W Reset 0 0 0 0 0 0 0 0 14 13 12 11 10 9 Bit 8
Figure 7-9. Breakpoint Data High Byte Register (BKP1H)
Read: Anytime Write: Anytime In Dual Mode, this register is used to compare against the high order address lines. In Full Mode, this register is used to compare against the high order data lines.
7.3.1.8
Breakpoint Data (Second Address) Low Byte Register (BKP1L)
Module Base + 0x002F
7 6 5 4 3 2 1 0
R Bit 7 W Reset 0 0 0 0 0 0 0 0 6 5 4 3 2 1 Bit 0
Figure 7-10. Breakpoint Data Low Byte Register (BKP1L)
Read: Anytime Write: Anytime In Dual Mode, this register is used to compare against the low order address lines. In Full Mode, this register is used to compare against the low order data lines.
MC3S12RG128 Data Sheet, Rev. 1.05 210 Freescale Semiconductor
Chapter 7 Breakpoint Module (BKPV1) Block Description
7.4
Functional Description
The Breakpoint sub-block supports two modes of operation: Dual Address Mode and Full Breakpoint Mode. Within each of these modes, forced or tagged breakpoint types can be used. Forced breakpoints occur at the next instruction boundary if a match occurs and tagged breakpoints allow for breaking just before a specific instruction executes. The action taken upon a successful match can be to either place the CPU in Background Debug Mode or to initiate a software interrupt.
7.4.1
Modes of Operation
The Breakpoint can operate in Dual Address Mode or Full Breakpoint Mode. Each of these modes is discussed in the subsections below.
7.4.1.1
Dual Address Mode
When Dual Address Mode is enabled, two address breakpoints can be set. Each breakpoint can cause the system to enter Background Debug Mode or to initiate a software interrupt based upon the state of the BKBDM bit in the BKPCT0 Register being logic one or logic zero, respectively. BDM requests have a higher priority than SWI requests. No data breakpoints are allowed in this mode. The BKTAG bit in the BKPCT0 register selects whether the breakpoint mode is forced or tagged. The BKxMBH:L bits in the BKPCT1 register select whether or not the breakpoint is matched exactly or is a range breakpoint. They also select whether the address is matched on the high byte, low byte, both bytes, and/or memory expansion. The BKxRW and BKxRWE bits in the BKPCT1 register select whether the type of bus cycle to match is a read, write, or both when performing forced breakpoints.
7.4.1.2
Full Breakpoint Mode
Full Breakpoint Mode requires a match on address and data for a breakpoint to occur. Upon a successful match, the system will enter Background Debug Mode or initiate a software interrupt based upon the state of the BKBDM bit in the BKPCT0 Register being logic one or logic zero, respectively. BDM requests have a higher priority than SWI requests. R/W matches are also allowed in this mode. The BKTAG bit in the BKPCT0 register selects whether the breakpoint mode is forced or tagged. If the BKTAG bit is set in BKPCT0, then only address is matched, and data is ignored. The BK0MBH:L bits in the BKPCT1 register select whether or not the breakpoint is matched exactly, is a range breakpoint, or is in page space. The BK1MBH:L bits in the BKPCT1 register select whether the data is matched on the high byte, low byte, or both bytes. The BK0RW and BK0RWE bits in the BKPCT1 register select whether the type of bus cycle to match is a read or a write when performing forced breakpoints. BK1RW and BK1RWE bits in the BKPCT1 register are not used in Full Breakpoint Mode.
7.4.2
Breakpoint Priority
Breakpoint operation is first determined by the state of BDM. If BDM is already active, meaning the CPU is executing out of BDM firmware, Breakpoints are not allowed. In addition, while in BDM trace mode, tagging into BDM is not allowed. If BDM is not active, the Breakpoint will give priority to BDM requests over SWI requests. This condition applies to both forced and tagged breakpoints.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 211
Chapter 7 Breakpoint Module (BKPV1) Block Description
In all cases, BDM related breakpoints will have priority over those generated by the Breakpoint sub-block. This priority includes breakpoints enabled by the TAGLO and TAGHI external pins of the system that interface with the BDM directly and whose signal information passes through and is used by the Breakpoint sub-block. NOTE BDM should not be entered from a breakpoint unless the BKEN bit is set in the BDM. Even if the ENABLE bit in the BDM is negated, the CPU actually executes the BDM firmware code. It checks the ENABLE and returns if enable is not set. If the BDM is not serviced by the monitor then the breakpoint would be re-asserted when the BDM returns to normal CPU flow. There is no hardware to enforce restriction of breakpoint operation if the BDM is not enabled.
MC3S12RG128 Data Sheet, Rev. 1.05 212 Freescale Semiconductor
Chapter 8 Analog-to-Digital Converter (ATD10B8CV3)
8.1 Introduction
The ATD10B8C is an 8-channel, 10-bit, multiplexed input successive approximation analog-to-digital converter. Refer to device electrical specifications for ATD accuracy.
8.1.1
* * * * * * * * * * * * *
Features
8/10-bit resolution 7 sec, 10-bit single conversion time Sample buffer amplifier Programmable sample time Left/right justified, signed/unsigned result data External trigger control Conversion completion interrupt generation Analog input multiplexer for 8 analog input channels Analog/digital input pin multiplexing 1-to-8 conversion sequence lengths Continuous conversion mode Multiple channel scans Configurable external trigger functionality on any AD channel or any of four additional external trigger inputs. The four additional trigger inputs can be chip external or internal. Refer to the device overview chapter for availability and connectivity. Configurable location for channel wrap around (when converting multiple channels in a sequence).
*
8.1.2
8.1.2.1
Modes of Operation
Conversion Modes
There is software programmable selection between performing single or continuous conversion on a single channel or multiple channels.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 213
Chapter 8 Analog-to-Digital Converter (ATD10B8CV3)
8.1.2.2
*
MCU Operating Modes
*
*
Stop mode Entering stop mode causes all clocks to halt and thus the system is placed in a minimum power standby mode. This aborts any conversion sequence in progress. During recovery from stop mode, there must be a minimum delay for the stop recovery time tSR before initiating a new ATD conversion sequence. Wait mode Entering wait mode the ATD conversion either continues or aborts for low power depending on the logical value of the AWAIT bit. Freeze mode In freeze mode the ATD will behave according to the logical values of the FRZ1 and FRZ0 bits. This is useful for debugging and emulation.
8.1.3
Block Diagram
Figure 8-1 shows a block diagram of the ATD.
8.2
External Signal Description
This section lists all inputs to the ATD block.
8.2.1
ANx (x = 7, 6, 5, 4, 3, 2, 1, 0) -- Analog Input Pin
This pin serves as the analog input channel x. It can also be configured as general purpose digital port pin and/or external trigger for the ATD conversion.
8.2.2
ETRIG3, ETRIG2, ETRIG1, and ETRIG0 -- External Trigger Pins
These inputs can be configured to serve as an external trigger for the ATD conversion. Refer to the device overview chapter for availability and connectivity of these inputs.
8.2.3
VRH and VRL -- High and Low Reference Voltage Pins
VRH is the high reference voltage and VRL is the low reference voltage for ATD conversion.
8.2.4
VDDA and VSSA -- Power Supply Pins
These pins are the power supplies for the analog circuitry of the ATD block.
MC3S12RG128 Data Sheet, Rev. 1.05 214 Freescale Semiconductor
Chapter 8 Analog-to-Digital Converter (ATD10B8CV3)
Bus Clock
Clock Prescaler Trigger Mux
ATD clock
ATD10B8C
ETRIG0 ETRIG1 ETRIG2 ETRIG3 (See Device Overview chapter for availability and connectivity)
Mode and Timing Control
Sequence Complete Interrupt
ATDCTL1
ATDDIEN
PORTAD VDDA VSSA VRH VRL Successive Approximation Register (SAR) and DAC
Results ATD 0 ATD 1 ATD 2 ATD 3 ATD 4 ATD 5 ATD 6 ATD 7
AN7 AN6 AN5 AN4 AN3 Analog AN2 AN1 AN0 MUX 1 1 Sample & Hold - Comparator +
Figure 8-1. ATD Block Diagram
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 215
Chapter 8 Analog-to-Digital Converter (ATD10B8CV3)
8.3
Memory Map and Register Definition
This section provides a detailed description of all registers accessible in the ATD.
8.3.1
Module Memory Map
NOTE Register Address = Base Address + Address Offset, where the Base Address is defined at the MCU level and the Address Offset is defined at the module level.
Figure 8-2 gives an overview of all ATD registers.
8.3.2
Register Descriptions
This section describes in address order all the ATD registers and their individual bits.
Register Name 0x0000 ATDCTL0 0x0001 ATDCTL1 0x0002 ATDCTL2 0x0003 ATDCTL3 0x0004 ATDCTL4 0x0005 ATDCTL5 0x0006 ATDSTAT0 0x0007 Unimplemente d 0x0008 ATDTEST0 0x0009 ATDTEST1 R W Bit 7 0 6 0 5 0 4 0 3 0 2 WRAP2 1 WRAP1 Bit 0 WRAP0
R ETRIGSEL W R W R W R W R W R W R W R W R W U ADPU 0
0
0
0
0
ETRIGCH2 ETRIGCH1 ETRIGCH0 ASCIF
AFFC
AWAI
ETRIGLE
ETRIGP
ETRIGE
ASCIE
S8C
S4C
S2C
S1C
FIFO
FRZ1
FRZ0
SRES8
SMP1
SMP0
PRS4
PRS3 0
PRS2
PRS1
PRS0
DJM
DSGN 0
SCAN
MULT
CC CC2
CB CC1
CA CC0
SCF
ETORF
FIFOR
0
U
U
U
U
U
U
U
U
U
0
0
0
0
0
SC
= Unimplemented or Reserved
Figure 8-2. ATD Register Summary (Sheet 1 of 5)
MC3S12RG128 Data Sheet, Rev. 1.05 216 Freescale Semiconductor
Chapter 8 Analog-to-Digital Converter (ATD10B8CV3)
Register Name 0x000A Unimplemente d 0x000B ATDSTAT1 0x000C Unimplemente d 0x000D ATDDIEN 0x000E Unimplemente d 0x000F PORTAD R W R W R W R W R W R W
Bit 7
6
5
4
3
2
1
Bit 0
CCF7
CCF6
CCF5
CCF4
CCF3
CCF2
CCF1
CCF0
IEN7
IEN6
IEN5
IEN4
IEN3
IEN2
IEN1
IEN0
PTAD7
PTAD6
PTAD5
PTAD4
PTAD3
PTAD2
PTAD1
PTAD0
Left Justified Result Data Note: The read portion of the left justified result data registers has been divided to show the bit position when reading 10-bit and 8-bit conversion data. For more detailed information refer to Section 8.3.2.13, "ATD Conversion Result Registers (ATDDRx)". 0x0010 10-BIT BIT 9 MSB BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 ATDDR0H BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 8-BIT BIT 7 MSB W 0x0011 ATDDR0L 10-BIT 8-BIT W BIT 1 U BIT 0 U 0 0 0 0 0 0 0 0 0 0 0 0
0x0012 ATDDR1H
10-BIT BIT 9 MSB 8-BIT BIT 7 MSB W 10-BIT 8-BIT W BIT 1 U
BIT 8 BIT 6
BIT 7 BIT 5
BIT 6 BIT 4
BIT 5 BIT 3
BIT 4 BIT 2
BIT 3 BIT 1
BIT 2 BIT 0
0x0013 ATDDR1L
BIT 0 U
0 0
0 0
0 0
0 0
0 0
0 0
0x0014 ATDDR2H
10-BIT BIT 9 MSB 8-BIT BIT 7 MSB W 10-BIT 8-BIT W BIT 1 U
BIT 8 BIT 6
BIT 7 BIT 5
BIT 6 BIT 4
BIT 5 BIT 3
BIT 4 BIT 2
BIT 3 BIT 1
BIT 2 BIT 0
0x0015 ATDDR2L
BIT 0 U
0 0
0 0
0 0
0 0
0 0
0 0
= Unimplemented or Reserved
Figure 8-2. ATD Register Summary (Sheet 2 of 5)
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 217
Chapter 8 Analog-to-Digital Converter (ATD10B8CV3)
Register Name 0x0016 ATDDR3H
Bit 7 10-BIT BIT 9 MSB 8-BIT BIT 7 MSB W 10-BIT 8-BIT W BIT 1 U
6 BIT 8 BIT 6
5 BIT 7 BIT 5
4 BIT 6 BIT 4
3 BIT 5 BIT 3
2 BIT 4 BIT 2
1 BIT 3 BIT 1
Bit 0 BIT 2 BIT 0
0x0017 ATDDR3L
BIT 0 U
0 0
0 0
0 0
0 0
0 0
0 0
0x0018 ATDDR4H
10-BIT BIT 9 MSB 8-BIT BIT 7 MSB W 10-BIT 8-BIT W BIT 1 U
BIT 8 BIT 6
BIT 7 BIT 5
BIT 6 BIT 4
BIT 5 BIT 3
BIT 4 BIT 2
BIT 3 BIT 1
BIT 2 BIT 0
0x0019 ATDDR4L
BIT 0 U
0 0
0 0
0 0
0 0
0 0
0 0
0x001A ATDD45H
10-BIT BIT 9 MSB 8-BIT BIT 7 MSB W 10-BIT 8-BIT W BIT 1 U
BIT 8 BIT 6
BIT 7 BIT 5
BIT 6 BIT 4
BIT 5 BIT 3
BIT 4 BIT 2
BIT 3 BIT 1
BIT 2 BIT 0
0x001B ATDD45L
BIT 0 U
0 0
0 0
0 0
0 0
0 0
0 0
0x001C ATDD46H
10-BIT BIT 9 MSB 8-BIT BIT 7 MSB W 10-BIT 8-BIT W BIT 1 U
BIT 8 BIT 6
BIT 7 BIT 5
BIT 6 BIT 4
BIT 5 BIT 3
BIT 4 BIT 2
BIT 3 BIT 1
BIT 2 BIT 0
0x001D ATDDR6L
BIT 0 U
0 0
0 0
0 0
0 0
0 0
0 0
0x001E ATDD47H
10-BIT BIT 9 MSB 8-BIT BIT 7 MSB W 10-BIT 8-BIT W BIT 1 U
BIT 8 BIT 6
BIT 7 BIT 5
BIT 6 BIT 4
BIT 5 BIT 3
BIT 4 BIT 2
BIT 3 BIT 1
BIT 2 BIT 0
0x001F ATDD47L
BIT 0 U
0 0
0 0
0 0
0 0
0 0
0 0
Right Justified Result Data Note: The read portion of the right justified result data registers has been divided to show the bit position when reading 10-bit and 8-bit conversion data. For more detailed information refer to Section 8.3.2.13, "ATD Conversion Result Registers (ATDDRx)". 0x0010 10-BIT 0 0 0 0 0 0 BIT 9 MSB BIT 8 ATDDR0H 0 0 0 0 0 0 0 0 8-BIT W = Unimplemented or Reserved
Figure 8-2. ATD Register Summary (Sheet 3 of 5)
MC3S12RG128 Data Sheet, Rev. 1.05 218 Freescale Semiconductor
Chapter 8 Analog-to-Digital Converter (ATD10B8CV3)
Register Name 0x0011 ATDDR0L
Bit 7 10-BIT BIT 7 8-BIT BIT 7 MSB W 10-BIT 8-BIT W 0 0
6 BIT 6 BIT 6
5 BIT 5 BIT 5
4 BIT 4 BIT 4
3 BIT 3 BIT 3
2 BIT 2 BIT 2
1 BIT 1 BIT 1
Bit 0 BIT 0 BIT 0
0x0012 ATDDR1H
0 0
0 0
0 0
0 0
0 0
BIT 9 MSB 0
BIT 8 0
0x0013 ATDDR1L
10-BIT BIT 7 8-BIT BIT 7 MSB W 10-BIT 8-BIT W 0 0
BIT 6 BIT 6
BIT 5 BIT 5
BIT 4 BIT 4
BIT 3 BIT 3
BIT 2 BIT 2
BIT 1 BIT 1
BIT 0 BIT 0
0x0014 ATDDR2H
0 0
0 0
0 0
0 0
0 0
BIT 9 MSB 0
BIT 8 0
0x0015 ATDDR2L
10-BIT BIT 7 8-BIT BIT 7 MSB W 10-BIT 8-BIT W 0 0
BIT 6 BIT 6
BIT 5 BIT 5
BIT 4 BIT 4
BIT 3 BIT 3
BIT 2 BIT 2
BIT 1 BIT 1
BIT 0 BIT 0
0x0016 ATDDR3H
0 0
0 0
0 0
0 0
0 0
BIT 9 MSB 0
BIT 8 0
0x0017 ATDDR3L
10-BIT BIT 7 8-BIT BIT 7 MSB W 10-BIT 8-BIT W 0 0
BIT 6 BIT 6
BIT 5 BIT 5
BIT 4 BIT 4
BIT 3 BIT 3
BIT 2 BIT 2
BIT 1 BIT 1
BIT 0 BIT 0
0x0018 ATDDR4H
0 0
0 0
0 0
0 0
0 0
BIT 9 MSB 0
BIT 8 0
0x0019 ATDDR4L
10-BIT BIT 7 8-BIT BIT 7 MSB W 10-BIT 8-BIT W 0 0
BIT 6 BIT 6
BIT 5 BIT 5
BIT 4 BIT 4
BIT 3 BIT 3
BIT 2 BIT 2
BIT 1 BIT 1
BIT 0 BIT 0
0x001A ATDD45H
0 0
0 0
0 0
0 0
0 0
BIT 9 MSB 0
BIT 8 0
0x001B ATDD45L
10-BIT BIT 7 8-BIT BIT 7 MSB W 10-BIT 8-BIT W 0 0
BIT 6 BIT 6
BIT 5 BIT 5
BIT 4 BIT 4
BIT 3 BIT 3
BIT 2 BIT 2
BIT 1 BIT 1
BIT 0 BIT 0
0x001C ATDD46H
0 0
0 0
0 0
0 0
0 0
BIT 9 MSB 0
BIT 8 0
= Unimplemented or Reserved
Figure 8-2. ATD Register Summary (Sheet 4 of 5)
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 219
Chapter 8 Analog-to-Digital Converter (ATD10B8CV3)
Register Name 0x001D ATDDR6L
Bit 7 10-BIT BIT 7 8-BIT BIT 7 MSB W 10-BIT 8-BIT W 10-BIT 8-BIT 0 0
6 BIT 6 BIT 6
5 BIT 5 BIT 5
4 BIT 4 BIT 4
3 BIT 3 BIT 3
2 BIT 2 BIT 2
1 BIT 1 BIT 1
Bit 0 BIT 0 BIT 0
0x001E ATDD47H
0 0
0 0
0 0
0 0
0 0
BIT 9 MSB 0
BIT 8 0
0x001F ATDD47L
BIT 7 BIT 7 MSB
BIT 6 BIT 6
BIT 5 BIT 5
BIT 4 BIT 4
BIT 3 BIT 3
BIT 2 BIT 2
BIT 1 BIT 1
BIT 0 BIT 0
= Unimplemented or Reserved
Figure 8-2. ATD Register Summary (Sheet 5 of 5)
8.3.2.1
ATD Control Register 0 (ATDCTL0)
Writes to this register will abort current conversion sequence but will not start a new sequence.
Module Base + 0x0000
7 6 5 4 3 2 1 0
R W Reset
0 0
0 0
0 0
0 0
0 0
WRAP2 1
WRAP1 1
WRAP0 1
= Unimplemented or Reserved
Figure 8-3. ATD Control Register 0 (ATDCTL0)
Read: Anytime Write: Anytime
Table 8-1. ATDCTL0 Field Descriptions
Field 2-0 WRAP[2:0] Description Wrap Around Channel Select Bits -- These bits determine the channel for wrap around when doing multi-channel conversions. The coding is summarized in Table 8-2.
Table 8-2. Multi-Channel Wrap Around Coding
WRAP2 0 0 0 0 1 1 WRAP1 0 0 1 1 0 0 WRAP0 0 1 0 1 0 1 Multiple Channel Conversions (MULT = 1) Wrap Around to AN0 after Converting Reserved AN1 AN2 AN3 AN4 AN5
MC3S12RG128 Data Sheet, Rev. 1.05 220 Freescale Semiconductor
Chapter 8 Analog-to-Digital Converter (ATD10B8CV3)
Table 8-2. Multi-Channel Wrap Around Coding
WRAP2 1 1 WRAP1 1 1 WRAP0 0 1 Multiple Channel Conversions (MULT = 1) Wrap Around to AN0 after Converting AN6 AN7
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 221
Chapter 8 Analog-to-Digital Converter (ATD10B8CV3)
8.3.2.2
ATD Control Register 1 (ATDCTL1)
Writes to this register will abort current conversion sequence but will not start a new sequence.
Module Base + 0x0001
7 6 5 4 3 2 1 0
R W Reset
ETRIGSEL 0
0 0
0 0
0 0
0 0
ETRIGCH2 1
ETRIGCH1 1
ETRIGCH0 1
= Unimplemented or Reserved
Figure 8-4. ATD Control Register 1 (ATDCTL1)
Read: Anytime Write: Anytime
Table 8-3. ATDCTL1 Field Descriptions
Field 7 ETRIGSEL Description External Trigger Source Select -- This bit selects the external trigger source to be either one of the AD channels or one of the ETRIG3-0 inputs. See the device overview chapter for availability and connectivity of ETRIG3-0 inputs. If ETRIG3-0 input option is not available, writing a 1 to ETRISEL only sets the bit but has not effect, that means still one of the AD channels (selected by ETRIGCH2-0) is the source for external trigger. The coding is summarized in Table 8-4.
2-0 External Trigger Channel Select -- These bits select one of the AD channels or one of the ETRIG3-0 inputs ETRIGCH[2:0] as source for the external trigger. The coding is summarized in Table 8-4.
Table 8-4. External Trigger Channel Select Coding
ETRIGSEL 0 0 0 0 0 0 0 0 1 1 1 1 1
1
ETRIGCH2 0 0 0 0 1 1 1 1 0 0 0 0 1
ETRIGCH1 0 0 1 1 0 0 1 1 0 0 1 1 X
ETRIGCH0 0 1 0 1 0 1 0 1 0 1 0 1 X
External trigger source is AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 ETRIG01 ETRIG11 ETRIG21 ETRIG31 Reserved
Only if ETRIG3-0 input option is available (see device overview chapter), else ETRISEL is ignored, that means external trigger source is still on one of the AD channels selected by ETRIGCH2-0
MC3S12RG128 Data Sheet, Rev. 1.05 222 Freescale Semiconductor
Chapter 8 Analog-to-Digital Converter (ATD10B8CV3)
8.3.2.3
ATD Control Register 2 (ATDCTL2)
This register controls power down, interrupt and external trigger. Writes to this register will abort current conversion sequence but will not start a new sequence.
Module Base + 0x0002
7 6 5 4 3 2 1 0
R W Reset
ADPU 0
AFFC 0
AWAI 0
ETRIGLE 0
ETRIGP 0
ETRIGE 0
ASCIE 0
ASCIF 0
= Unimplemented or Reserved
Figure 8-5. ATD Control Register 2 (ATDCTL2)
Read: Anytime Write: Anytime
Table 8-5. ATDCTL2 Field Descriptions
Field 7 ADPU Description ATD Power Up -- This bit provides on/off control over the ATD block allowing reduced MCU power consumption. Because analog electronic is turned off when powered down, the ATD requires a recovery time period after ADPU bit is enabled. 0 Power down ATD. Flags (SCF, CCFx, ETORF, FIFOR) can not be cleared. 1 Normal ATD functionality ATD Fast Flag Clear All 0 ATD flag clearing operates normally (read the status register ATDSTAT1 before reading the result register to clear the associate CCF flag). 1 Changes all ATD conversion complete flags to a fast clear sequence. Any access to a result register will cause the associate CCF flag to clear automatically. ATD Power Down in Wait Mode -- When entering wait mode this bit provides on/off control over the ATD block allowing reduced MCU power. Because analog electronic is turned off when powered down, the ATD requires a recovery time period after exit from Wait mode. 0 ATD continues to run in Wait mode 1 Halt conversion and power down ATD during wait mode After exiting wait mode with an interrupt conversion will resume. But due to the recovery time the result of this conversion should be ignored. External Trigger Level/Edge Control -- This bit controls the sensitivity of the external trigger signal. See Table 8-6 for details. External Trigger Polarity -- This bit controls the polarity of the external trigger signal. See Table 8-6 for details. External Trigger Mode Enable -- This bit enables the external trigger on one of the AD channels or one of the ETRIG3-0 inputs as described in Table 8-4. If external trigger source is one of the AD channels, the digital input buffer of this channel is enabled. The external trigger allows to synchronize sample and ATD conversions processes with external events. 0 Disable external trigger 1 Enable external trigger Note: If using one of the AD channel as external trigger (ETRIGSEL = 0) the conversion results for this channel have no meaning while external trigger mode is enabled.
6 AFFC
5 AWAI
4 ETRIGLE 3 ETRIGP 2 ETRIGE
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 223
Chapter 8 Analog-to-Digital Converter (ATD10B8CV3)
Table 8-5. ATDCTL2 Field Descriptions (continued)
Field 1 ASCIE 0 ASCIF Description ATD Sequence Complete Interrupt Enable 0 ATD Sequence Complete interrupt requests are disabled. 1 ATD Interrupt will be requested whenever ASCIF = 1 is set. ATD Sequence Complete Interrupt Flag -- If ASCIE = 1 the ASCIF flag equals the SCF flag (see Section 8.3.2.7, "ATD Status Register 0 (ATDSTAT0)"), else ASCIF reads zero. Writes have no effect. 0 No ATD interrupt occurred 1 ATD sequence complete interrupt pending
Table 8-6. External Trigger Configurations
ETRIGLE 0 0 1 1 ETRIGP 0 1 0 1 External Trigger Sensitivity Falling edge Rising edge Low level High level
8.3.2.4
ATD Control Register 3 (ATDCTL3)
This register controls the conversion sequence length, FIFO for results registers and behavior in freeze mode. Writes to this register will abort current conversion sequence but will not start a new sequence.
Module Base + 0x0003
7 6 5 4 3 2 1 0
R W Reset
0 0
S8C 0
S4C 0
S2C 0
S1C 0
FIFO 0
FRZ1 0
FRZ0 0
= Unimplemented or Reserved
Figure 8-6. ATD Control Register 3 (ATDCTL3)
Read: Anytime Write: Anytime
Table 8-7. ATDCTL3 Field Descriptions
Field 6-3 S8C, S4C, S2C, S1C Description Conversion Sequence Length -- These bits control the number of conversions per sequence. Table 8-8 shows all combinations. At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity to HC12 Family.
MC3S12RG128 Data Sheet, Rev. 1.05 224 Freescale Semiconductor
Chapter 8 Analog-to-Digital Converter (ATD10B8CV3)
Table 8-7. ATDCTL3 Field Descriptions (continued)
Field 2 FIFO Description Result Register FIFO Mode -- If this bit is zero (non-FIFO mode), the A/D conversion results map into the result registers based on the conversion sequence; the result of the first conversion appears in the first result register, the second result in the second result register, and so on. If this bit is one (FIFO mode) the conversion counter is not reset at the beginning or ending of a conversion sequence; sequential conversion results are placed in consecutive result registers. In a continuously scanning conversion sequence, the result register counter will wrap around when it reaches the end of the result register file. The conversion counter value (CC2-0 in ATDSTAT0) can be used to determine where in the result register file, the current conversion result will be placed. Aborting a conversion or starting a new conversion by write to an ATDCTL register (ATDCTL5-0) clears the conversion counter even if FIFO=1. So the first result of a new conversion sequence, started by writing to ATDCTL5, will always be place in the first result register (ATDDDR0). Intended usage of FIFO mode is continuos conversion (SCAN=1) or triggered conversion (ETRIG=1). Finally, which result registers hold valid data can be tracked using the conversion complete flags. Fast flag clear mode may or may not be useful in a particular application to track valid data. 0 Conversion results are placed in the corresponding result register up to the selected sequence length. 1 Conversion results are placed in consecutive result registers (wrap around at end). Background Debug Freeze Enable -- When debugging an application, it is useful in many cases to have the ATD pause when a breakpoint (Freeze Mode) is encountered. These 2 bits determine how the ATD will respond to a breakpoint as shown in Table 8-9. Leakage onto the storage node and comparator reference capacitors may compromise the accuracy of an immediately frozen conversion depending on the length of the freeze period.
1-0 FRZ[1:0]
Table 8-8. Conversion Sequence Length Coding
S8C 0 0 0 0 0 0 0 0 1 S4C 0 0 0 0 1 1 1 1 X S2C 0 0 1 1 0 0 1 1 X S1C 0 1 0 1 0 1 0 1 X Number of Conversions per Sequence 8 1 2 3 4 5 6 7 8
Table 8-9. ATD Behavior in Freeze Mode (Breakpoint)
FRZ1 0 0 1 1 FRZ0 0 1 0 1 Behavior in Freeze Mode Continue conversion Reserved Finish current conversion, then freeze Freeze Immediately
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 225
Chapter 8 Analog-to-Digital Converter (ATD10B8CV3)
8.3.2.5
ATD Control Register 4 (ATDCTL4)
This register selects the conversion clock frequency, the length of the second phase of the sample time and the resolution of the A/D conversion (i.e.: 8-bits or 10-bits). Writes to this register will abort current conversion sequence but will not start a new sequence.
Module Base + 0x0004
7 6 5 4 3 2 1 0
R W Reset
SRES8 0
SMP1 0
SMP0 0
PRS4 0
PRS3 0
PRS2 1
PRS1 0
PRS0 1
Figure 8-7. ATD Control Register 4 (ATDCTL4)
Read: Anytime Write: Anytime
Table 8-10. ATDCTL4 Field Descriptions
Field 7 SRES8 Description A/D Resolution Select -- This bit selects the resolution of A/D conversion results as either 8 or 10 bits. The A/D converter has an accuracy of 10 bits; however, if low resolution is required, the conversion can be speeded up by selecting 8-bit resolution. 0 10-bit resolution 8-bit resolution Sample Time Select -- These two bits select the length of the second phase of the sample time in units of ATD conversion clock cycles. Note that the ATD conversion clock period is itself a function of the prescaler value (bits PRS4-0). The sample time consists of two phases. The first phase is two ATD conversion clock cycles long and transfers the sample quickly (via the buffer amplifier) onto the A/D machine's storage node. The second phase attaches the external analog signal directly to the storage node for final charging and high accuracy. Table 8-11 lists the lengths available for the second sample phase. ATD Clock Prescaler -- These 5 bits are the binary value prescaler value PRS. The ATD conversion clock frequency is calculated as follows:
[ BusClock ] ATDclock = -------------------------------- x 0.5 [ PRS + 1 ]
6-5 SMP[1:0]
4-0 PRS[4:0]
Note: The maximum ATD conversion clock frequency is half the bus clock. The default (after reset) prescaler value is 5 which results in a default ATD conversion clock frequency that is bus clock divided by 12. Table 8-12 illustrates the divide-by operation and the appropriate range of the bus clock.
Table 8-11. Sample Time Select
SMP1 0 0 1 1 SMP0 0 1 0 1 Length of 2nd Phase of Sample Time 2 A/D conversion clock periods 4 A/D conversion clock periods 8 A/D conversion clock periods 16 A/D conversion clock periods
MC3S12RG128 Data Sheet, Rev. 1.05 226 Freescale Semiconductor
Chapter 8 Analog-to-Digital Converter (ATD10B8CV3)
Table 8-12. Clock Prescaler Values
Prescale Value 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111
1
Total Divisor Value Divide by 2 Divide by 4 Divide by 6 Divide by 8 Divide by 10 Divide by 12 Divide by 14 Divide by 16 Divide by 18 Divide by 20 Divide by 22 Divide by 24 Divide by 26 Divide by 28 Divide by 30 Divide by 32 Divide by 34 Divide by 36 Divide by 38 Divide by 40 Divide by 42 Divide by 44 Divide by 46 Divide by 48 Divide by 50 Divide by 52 Divide by 54 Divide by 56 Divide by 58 Divide by 60 Divide by 62 Divide by 64
Max. Bus Clock1 4 MHz 8 MHz 12 MHz 16 MHz 20 MHz 24 MHz 28 MHz 32 MHz 36 MHz 40 MHz 44 MHz 48 MHz 52 MHz 56 MHz 60 MHz 64 MHz 68 MHz 72 MHz 76 MHz 80 MHz 84 MHz 88 MHz 92 MHz 96 MHz 100 MHz 104 MHz 108 MHz 112 MHz 116 MHz 120 MHz 124 MHz 128 MHz
Min. Bus Clock2 1 MHz 2 MHz 3 MHz 4 MHz 5 MHz 6 MHz 7 MHz 8 MHz 9 MHz 10 MHz 11 MHz 12 MHz 13 MHz 14 MHz 15 MHz 16 MHz 17 MHz 18 MHz 19 MHz 20 MHz 21 MHz 22 MHz 23 MHz 24 MHz 25 MHz 26 MHz 27 MHz 28 MHz 29 MHz 30 MHz 31 MHz 32 MHz
Maximum ATD conversion clock frequency is 2 MHz. The maximum allowed bus clock frequency is shown in this column. 2 Minimum ATD conversion clock frequency is 500 kHz. The minimum allowed bus clock frequency is shown in this column.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 227
Chapter 8 Analog-to-Digital Converter (ATD10B8CV3)
8.3.2.6
ATD Control Register 5 (ATDCTL5)
This register selects the type of conversion sequence and the analog input channels sampled. Writes to this register will abort current conversion sequence and start a new conversion sequence.
Module Base + 0x0005
7 6 5 4 3 2 1 0
R W Reset
DJM 0
DSGN 0
SCAN 0
MULT 0
0 0
CC 0
CB 0
CA 0
= Unimplemented or Reserved
Figure 8-8. ATD Control Register 5 (ATDCTL5)
Read: Anytime Write: Anytime
Table 8-13. ATDCTL5 Field Descriptions
Field 7 DJM Description Result Register Data Justification -- This bit controls justification of conversion data in the result registers. See Section 8.3.2.13, "ATD Conversion Result Registers (ATDDRx)," for details. 0 Left justified data in the result registers 1 Right justified data in the result registers Result Register Data Signed or Unsigned Representation -- This bit selects between signed and unsigned conversion data representation in the result registers. Signed data is represented as 2's complement. Signed data is not available in right justification. See Section 8.3.2.13, "ATD Conversion Result Registers (ATDDRx)," for details. 0 Unsigned data representation in the result registers 1 Signed data representation in the result registers Table 8-14 summarizes the result data formats available and how they are set up using the control bits. Table 8-15 illustrates the difference between the signed and unsigned, left justified output codes for an input signal range between 0 and 5.12 Volts. Continuous Conversion Sequence Mode -- This bit selects whether conversion sequences are performed continuously or only once. 0 Single conversion sequence 1 Continuous conversion sequences (scan mode) Multi-Channel Sample Mode -- When MULT is 0, the ATD sequence controller samples only from the specified analog input channel for an entire conversion sequence. The analog channel is selected by channel selection code (control bits CC/CB/CA located in ATDCTL5). When MULT is 1, the ATD sequence controller samples across channels. The number of channels sampled is determined by the sequence length value (S8C, S4C, S2C, S1C). The first analog channel examined is determined by channel selection code (CC, CB, CA control bits); subsequent channels sampled in the sequence are determined by incrementing the channel selection code. 0 Sample only one channel 1 Sample across several channels Analog Input Channel Select Code -- These bits select the analog input channel(s) whose signals are sampled and converted to digital codes. Table 8-16 lists the coding used to select the various analog input channels. In the case of single channel scans (MULT = 0), this selection code specified the channel examined. In the case of multi-channel scans (MULT = 1), this selection code represents the first channel to be examined in the conversion sequence. Subsequent channels are determined by incrementing channel selection code; selection codes that reach the maximum value wrap around to the minimum value.
6 DSGN
5 SCAN
4 MULT
2-0 CC, CB, CA
MC3S12RG128 Data Sheet, Rev. 1.05 228 Freescale Semiconductor
Chapter 8 Analog-to-Digital Converter (ATD10B8CV3)
Table 8-14. Available Result Data Formats
SRES8 1 1 1 0 0 0 DJM 0 0 1 0 0 1 DSGN 0 1 X 0 1 X Result Data Formats Description and Bus Bit Mapping 8-bit / left justified / unsigned -- bits 8-15 8-bit / left justified / signed -- bits 8-15 8-bit / right justified / unsigned -- bits 0-7 10-bit / left justified / unsigned -- bits 6-15 10-bit / left justified / signed -- bits 6-15 10-bit / right justified / unsigned -- bits 0-9
Table 8-15. Left Justified, Signed, and Unsigned ATD Output Codes
Input Signal VRL = 0 Volts VRH = 5.12 Volts 5.120 Volts 5.100 5.080 2.580 2.560 2.540 0.020 0.000 Signed 8-Bit Codes 7F 7F 7E 01 00 FF 81 80 Unsigned 8-Bit Codes FF FF FE 81 80 7F 01 00 Signed 10-Bit Codes 7FC0 7F00 7E00 0100 0000 FF00 8100 8000 Unsigned 10-Bit Codes FFC0 FF00 FE00 8100 8000 7F00 0100 0000
Table 8-16. Analog Input Channel Select Coding
CC 0 0 0 0 1 1 1 1 CB 0 0 1 1 0 0 1 1 CA 0 1 0 1 0 1 0 1 Analog Input Channel AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 229
Chapter 8 Analog-to-Digital Converter (ATD10B8CV3)
8.3.2.7
ATD Status Register 0 (ATDSTAT0)
This read-only register contains the sequence complete flag, overrun flags for external trigger and FIFO mode, and the conversion counter.
Module Base + 0x0006
7 6 5 4 3 2 1 0
R W Reset
SCF 0
0 0
ETORF 0
FIFOR 0
0 0
CC2 0
CC1 0
CC0 0
= Unimplemented or Reserved
Figure 8-9. ATD Status Register 0 (ATDSTAT0)
Read: Anytime Write: Anytime (No effect on (CC2, CC1, CC0))
Table 8-17. ATDSTAT0 Field Descriptions
Field 7 SCF Description Sequence Complete Flag -- This flag is set upon completion of a conversion sequence. If conversion sequences are continuously performed (SCAN = 1), the flag is set after each one is completed. This flag can be cleared when ADPU=1 and one of the following occurs: A) Write "1" to SCF B) Write to ATDCTL5 (a new conversion sequence is started) C) If AFFC=1 and read of a result register 0 Conversion sequence not completed 1 Conversion sequence has completed External Trigger Overrun Flag -- While in edge trigger mode (ETRIGLE = 0), if additional active edges are detected while a conversion sequence is in process the overrun flag is set. This flag can be cleared when ADPU=1 and one of the following occurs: A) Write "1" to ETORF B) Write to ATDCTL2, ATDCTL3 or ATDCTL4 (a conversion sequence is aborted) C) Write to ATDCTL5 (a new conversion sequence is started) 0 No External trigger over run error has occurred 1 External trigger over run error has occurred FIFO Over Run Flag -- This bit indicates that a result register has been written to before its associated conversion complete flag (CCF) has been cleared. This flag is most useful when using the FIFO mode because the flag potentially indicates that result registers are out of sync with the input channels. However, it is also practical for non-FIFO modes, and indicates that a result register has been over written before it has been read (i.e., the old data has been lost). This flag can be cleared when ADPU=1 and one of the following occurs: A) Write "1" to FIFOR B) Start a new conversion sequence (write to ATDCTL5 or external trigger) 0 No over run has occurred 1 An over run condition exists Conversion Counter -- These 3 read-only bits are the binary value of the conversion counter. The conversion counter points to the result register that will receive the result of the current conversion. E.g. CC2 = 1, CC1 = 1, CC0 = 0 indicates that the result of the current conversion will be in ATD result register 6. If in non-FIFO mode (FIFO = 0) the conversion counter is initialized to zero at the begin and end of the conversion sequence. If in FIFO mode (FIFO = 1) the register counter is not initialized. The conversion counters wraps around when its maximum value is reached. Aborting a conversion or starting a new conversion by write to an ATDCTL register (ATDCTL5-0) clears the conversion counter even if FIFO=1. MC3S12RG128 Data Sheet, Rev. 1.05 230 Freescale Semiconductor
5 ETORF
4 FIFOR
2-0 CC[2:0]
Chapter 8 Analog-to-Digital Converter (ATD10B8CV3)
8.3.2.8
Reserved Register (ATDTEST0)
Module Base + 0x0008
7 6 5 4 3 2 1 0
R W Reset
U 1
U 0
U 0
U 0
U 0
U 0
U 0
U 0
= Unimplemented or Reserved
Figure 8-10. Reserved Register (ATDTEST0)
Read: Anytime, returns unpredictable values Write: Anytime in special modes, unimplemented in normal modes NOTE Writing to this register when in special modes can alter functionality.
8.3.2.9
ATD Test Register 1 (ATDTEST1)
This register contains the SC bit used to enable special channel conversions.
Module Base + 0x0009
7 6 5 4 3 2 1 0
R W Reset
U 0
U 0
0 0
0 0
0 0
0 0
0 0
SC 0
= Unimplemented or Reserved
Figure 8-11. ATD Test Register 1 (ATDTEST1)
Read: Anytime, returns unpredictable values for Bit7 and Bit6 Write: Anytime
Table 8-18. ATDTEST1 Field Descriptions
Field 0 SC Description Special Channel Conversion Bit -- If this bit is set, then special channel conversion can be selected using CC, CB and CA of ATDCTL5. Table 8-19 lists the coding. 0 Special channel conversions disabled 1 Special channel conversions enabled Note: Always write remaining bits of ATDTEST1 (Bit7 to Bit1) zero when writing SC bit. Not doing so might result in unpredictable ATD behavior.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 231
Chapter 8 Analog-to-Digital Converter (ATD10B8CV3)
Table 8-19. Special Channel Select Coding
SC 1 1 1 1 1 CC 0 1 1 1 1 CB X 0 0 1 1 CA X 0 1 0 1 Analog Input Channel Reserved VRH VRL (VRH+VRL) / 2 Reserved
8.3.2.10
ATD Status Register 1 (ATDSTAT1)
This read-only register contains the conversion complete flags.
Module Base + 0x000B
7 6 5 4 3 2 1 0
R W Reset
CCF7 0
CCF6 0
CCF5 0
CCF4 0
CCF3 0
CCF2 0
CCF1 0
CCF0 0
= Unimplemented or Reserved
Figure 8-12. ATD Status Register 1 (ATDSTAT1)
Read: Anytime Write: Anytime, no effect
Table 8-20. ATDSTAT1 Field Descriptions
Field 7-0 CCF[7:0] Description Conversion Complete Flag x (x = 7, 6, 5, 4, 3, 2, 1, 0) -- A conversion complete flag is set at the end of each conversion in a conversion sequence. The flags are associated with the conversion position in a sequence (and also the result register number). Therefore, CCF0 is set when the first conversion in a sequence is complete and the result is available in result register ATDDR0; CCF1 is set when the second conversion in a sequence is complete and the result is available in ATDDR1, and so forth. A flag CCFx (x = 7, 6, 5, 4, 3, 2,1, 70) is cleared when ADPU=1 and one of the following occurs: A) Write to ATDCTL5 (a new conversion sequence is started) B) If AFFC=0 and read of ATDSTAT1 followed by read of result register ATDDRx C) If AFFC=1 and read of result register ATDDRx In case of a concurrent set and clear on CCFx: The clearing by method A) will overwrite the set. The clearing by methods B) or C) will be overwritten by the set. 0 Conversion number x not completed 1 Conversion number x has completed, result ready in ATDDRx
MC3S12RG128 Data Sheet, Rev. 1.05 232 Freescale Semiconductor
Chapter 8 Analog-to-Digital Converter (ATD10B8CV3)
8.3.2.11
ATD Input Enable Register (ATDDIEN)
Module Base + 0x000D
7 6 5 4 3 2 1 0
R W Reset
IEN7 0
IEN6 0
IEN5 0
IEN4 0
IEN3 0
IEN2 0
IEN1 0
IEN0 0
Figure 8-13. ATD Input Enable Register (ATDDIEN)
Read: Anytime Write: Anytime
Table 8-21. ATDDIEN Field Descriptions
Field 7-0 IEN[7:0] Description ATD Digital Input Enable on channel x (x = 7, 6, 5, 4, 3, 2, 1, 0) -- This bit controls the digital input buffer from the analog input pin (ANx) to PTADx data register. 0 Disable digital input buffer to PTADx 1 Enable digital input buffer to PTADx. Note: Setting this bit will enable the corresponding digital input buffer continuously. If this bit is set while simultaneously using it as an analog port, there is potentially increased power consumption because the digital input buffer maybe in the linear region.
8.3.2.12
Port Data Register (PORTAD)
The data port associated with the ATD can be configured as general-purpose I/O or input only, as specified in the device overview. The port pins are shared with the analog A/D inputs AN7-0.
Module Base + 0x000F
7 6 5 4 3 2 1 0
R W Reset Pin Function
PTAD7 1 AN7
PTAD6 1 AN6
PTAD5 1 AN5
PTAD4 1 AN4
PTAD3 1 AN3
PTAD2 1 AN2
PTAD1 1 AN1
PTAD0 1 AN0
= Unimplemented or Reserved
Figure 8-14. Port Data Register (PORTAD)
Read: Anytime Write: Anytime, no effect The A/D input channels may be used for general purpose digital input.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 233
Chapter 8 Analog-to-Digital Converter (ATD10B8CV3)
Table 8-22. PORTAD Field Descriptions
Field 7-0 PTAD[7:0] Description A/D Channel x (ANx) Digital Input (x = 7, 6, 5, 4, 3, 2, 1, 0) -- If the digital input buffer on the ANx pin is enabled (IENx = 1) or channel x is enabled as external trigger (ETRIGE = 1,ETRIGCH[2-0] = x,ETRIGSEL = 0) read returns the logic level on ANx pin (signal potentials not meeting VIL or VIH specifications will have an indeterminate value). If the digital input buffers are disabled (IENx = 0) and channel x is not enabled as external trigger, read returns a "1". Reset sets all PORTAD0 bits to "1".
8.3.2.13
ATD Conversion Result Registers (ATDDRx)
The A/D conversion results are stored in 8 read-only result registers. The result data is formatted in the result registers based on two criteria. First there is left and right justification; this selection is made using the DJM control bit in ATDCTL5. Second there is signed and unsigned data; this selection is made using the DSGN control bit in ATDCTL5. Signed data is stored in 2's complement format and only exists in left justified format. Signed data selected for right justified format is ignored. Read: Anytime Write: Anytime in special mode, unimplemented in normal modes 8.3.2.13.1 Left Justified Result Data
Module Base + 0x0010 = ATDDR0H, 0x0012 = ATDDR1H, 0x0014 = ATDDR2H, 0x0016 = ATDDR3H Module Base + 0x0018 = ATDDR4H, 0x001A = ATDDR5H, 0x001C = ATDDR6H, 0x001E = ATDDR7H
7 6 5 4 3 2 1 0
R BIT 9 MSB R BIT 7 MSB W Reset 0
BIT 8 BIT 6 0
BIT 7 BIT 5 0
BIT 6 BIT 4 0
BIT 5 BIT 3 0
BIT 4 BIT 2 0
BIT 3 BIT 1 0
BIT 2 BIT 0 0
10-bit data 8-bit data
= Unimplemented or Reserved
Figure 8-15. Left Justified, ATD Conversion Result Register, High Byte (ATDDRxH)
Module Base + 0x0011 = ATDDR0L, 0x0013 = ATDDR1L, 0x0015 = ATDDR2L, 0x0017 = ATDDR3L Module Base + 0x0019 = ATDDR4L, 0x001B = ATDDR5L, 0x001D = ATDDR6L, 0x001F = ATDDR7L
7 6 5 4 3 2 1 0
R R W Reset
BIT 1 U 0
BIT 0 U 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
= Unimplemented or Reserved
Figure 8-16. Left Justified, ATD Conversion Result Register, Low Byte (ATDDRxL)
MC3S12RG128 Data Sheet, Rev. 1.05 234 Freescale Semiconductor
Chapter 8 Analog-to-Digital Converter (ATD10B8CV3)
8.3.2.13.2
Right Justified Result Data
Module Base + 0x0010 = ATDDR0H, 0x0012 = ATDDR1H, 0x0014 = ATDDR2H, 0x0016 = ATDDR3H Module Base + 0x0018 = ATDDR4H, 0x001A = ATDDR5H, 0x001C = ATDDR6H, 0x001E = ATDDR7H
7 6 5 4 3 2 1 0
R R W Reset
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
BIT 9 MSB 0 0
BIT 8 0 0
10-bit data 8-bit data
= Unimplemented or Reserved
Figure 8-17. Right Justified, ATD Conversion Result Register, High Byte (ATDDRxH)
Module Base + 0x0011 = ATDDR0L, 0x0013 = ATDDR1L, 0x0015 = ATDDR2L, 0x0017 = ATDDR3L Module Base + 0x0019 = ATDDR4L, 0x001B = ATDDR5L, 0x001D = ATDDR6L, 0x001F = ATDDR7L
7 6 5 4 3 2 1 0
R BIT 7 R BIT 7 MSB W Reset 0
BIT 6 BIT 6 0
BIT 5 BIT 5 0
BIT 4 BIT 4 0
BIT 3 BIT 3 0
BIT 2 BIT 2 0
BIT 1 BIT 1 0
BIT 0 BIT 0 0
10-bit data 8-bit data
= Unimplemented or Reserved
Figure 8-18. Right Justified, ATD Conversion Result Register, Low Byte (ATDDRxL)
8.4
Functional Description
The ATD is structured in an analog and a digital sub-block.
8.4.1
Analog Sub-Block
The analog sub-block contains all analog electronics required to perform a single conversion. Separate power supplies VDDA and VSSA allow to isolate noise of other MCU circuitry from the analog sub-block.
8.4.1.1
Sample and Hold Machine
The sample and hold (S/H) machine accepts analog signals from the external surroundings and stores them as capacitor charge on a storage node. The sample process uses a two stage approach. During the first stage, the sample amplifier is used to quickly charge the storage node.The second stage connects the input directly to the storage node to complete the sample for high accuracy. When not sampling, the sample and hold machine disables its own clocks. The analog electronics still draw their quiescent current. The power down (ADPU) bit must be set to disable both the digital clocks and the analog power consumption. The input analog signals are unipolar and must fall within the potential range of VSSA to VDDA.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 235
Chapter 8 Analog-to-Digital Converter (ATD10B8CV3)
8.4.1.2
Analog Input Multiplexer
The analog input multiplexer connects one of the 8 external analog input channels to the sample and hold machine.
8.4.1.3
Sample Buffer Amplifier
The sample amplifier is used to buffer the input analog signal so that the storage node can be quickly charged to the sample potential.
8.4.1.4
Analog-to-Digital (A/D) Machine
The A/D Machine performs analog to digital conversions. The resolution is program selectable at either 8 or 10 bits. The A/D machine uses a successive approximation architecture. It functions by comparing the stored analog sample potential with a series of digitally generated analog potentials. By following a binary search algorithm, the A/D machine locates the approximating potential that is nearest to the sampled potential. When not converting the A/D machine disables its own clocks. The analog electronics still draws quiescent current. The power down (ADPU) bit must be set to disable both the digital clocks and the analog power consumption. Only analog input signals within the potential range of VRL to VRH (A/D reference potentials) will result in a non-railed digital output codes.
8.4.2
Digital Sub-Block
This subsection explains some of the digital features in more detail. See register descriptions for all details.
8.4.2.1
External Trigger Input
The external trigger feature allows the user to synchronize ATD conversions to the external environment events rather than relying on software to signal the ATD module when ATD conversions are to take place. The external trigger signal (out of reset ATD channel 7, configurable in ATDCTL1) is programmable to be edge or level sensitive with polarity control. Table 8-23 gives a brief description of the different combinations of control bits and their effect on the external trigger function.
MC3S12RG128 Data Sheet, Rev. 1.05 236 Freescale Semiconductor
Chapter 8 Analog-to-Digital Converter (ATD10B8CV3)
Table 8-23. External Trigger Control Bits
ETRIGLE X X 0 0 1 ETRIGP X X 0 1 0 ETRIGE 0 0 1 1 1 SCAN 0 1 X X X Description Ignores external trigger. Performs one conversion sequence and stops. Ignores external trigger. Performs continuous conversion sequences. Falling edge triggered. Performs one conversion sequence per trigger. Rising edge triggered. Performs one conversion sequence per trigger. Trigger active low. Performs continuous conversions while trigger is active. Trigger active high. Performs continuous conversions while trigger is active.
1
1
1
X
During a conversion, if additional active edges are detected the overrun error flag ETORF is set. In either level or edge triggered modes, the first conversion begins when the trigger is received. In both cases, the maximum latency time is one bus clock cycle plus any skew or delay introduced by the trigger circuitry. NOTE The conversion results for the external trigger ATD channel 7 have no meaning while external trigger mode is enabled. Once ETRIGE is enabled, conversions cannot be started by a write to ATDCTL5, but rather must be triggered externally. If the level mode is active and the external trigger both de-asserts and re-asserts itself during a conversion sequence, this does not constitute an overrun; therefore, the flag is not set. If the trigger is left asserted in level mode while a sequence is completing, another sequence will be triggered immediately.
8.4.2.2
General Purpose Digital Input Port Operation
The input channel pins can be multiplexed between analog and digital data. As analog inputs, they are multiplexed and sampled to supply signals to the A/D converter. As digital inputs, they supply external input data that can be accessed through the digital port register PORTAD (input-only). The analog/digital multiplex operation is performed in the input pads. The input pad is always connected to the analog inputs of the ATD. The input pad signal is buffered to the digital port registers. This buffer can be turned on or off with the ATDDIEN register. This is important so that the buffer does not draw excess current when analog potentials are presented at its input.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 237
Chapter 8 Analog-to-Digital Converter (ATD10B8CV3)
8.4.2.3
Low Power Modes
The ATD can be configured for lower MCU power consumption in 3 different ways: 1. Stop mode: This halts A/D conversion. Exit from stop mode will resume A/D conversion, but due to the recovery time the result of this conversion should be ignored. 2. Wait mode with AWAI = 1: This halts A/D conversion. Exit from wait mode will resume A/D conversion, but due to the recovery time the result of this conversion should be ignored. 3. Writing ADPU = 0 (Note that all ATD registers remain accessible.): This aborts any A/D conversion in progress. Note that the reset value for the ADPU bit is zero. Therefore, when this module is reset, it is reset into the power down state.
8.5
8.5.1
Initialization/Application Information
Setting up and starting an A/D conversion
The following describes a typical setup procedure for starting A/D conversions. It is highly recommended to follow this procedure to avoid common mistakes. Each step of the procedure will have a general remark and a typical example
8.5.1.1
Step 1
Power up the ATD and concurrently define other settings in ATDCTL2 Example: Write to ATDCTL2: ADPU=1 -> powers up the ATD, ASCIE=1 enable interrupt on finish of a conversion sequence.
8.5.1.2
Step 2
Wait for the ATD Recovery Time tREC before you proceed with Step 3. Example: Use the CPU in a branch loop to wait for a defined number of bus clocks.
8.5.1.3
Step 3
Configure how many conversions you want to perform in one sequence and define other settings in ATDCTL3. Example: Write S4C=1 to do 4 conversions per sequence.
8.5.1.4
Step 4
Configure resolution, sampling time and ATD clock speed in ATDCTL4. Example: Use default for resolution and sampling time by leaving SRES8, SMP1 and SMP0 clear. For a bus clock of 40MHz write 9 to PR4-0, this gives an ATD clock of 0.5*40MHz/(9+1) = 2MHz which is within the allowed range for fATDCLK.
MC3S12RG128 Data Sheet, Rev. 1.05 238 Freescale Semiconductor
Chapter 8 Analog-to-Digital Converter (ATD10B8CV3)
8.5.1.5
Step 5
Configure starting channel, single/multiple channel, continuous or single sequence and result data format in ATDCTL5. Writing ATDCTL5 will start the conversion, so make sure your write ATDCTL5 in the last step. Example: Leave CC,CB,CA clear to start on channel AN0. Write MULT=1 to convert channel AN0 to AN3 in a sequence (4 conversion per sequence selected in ATDCTL3).
8.5.2
8.5.2.1
Aborting an A/D conversion
Step 1
Write to ATDCTL4. This will abort any ongoing conversion sequence. (Do not use write to other ATDCTL registers to abort, as this under certain circumstances might not work correctly.)
8.5.2.2
Step 2
Disable the ATD Interrupt by writing ASCIE=0 in ATDCTL2. It is important to clear the interrupt enable at this point, prior to step 3, as depending on the device clock gating it may not always be possible to clear it or the SCF flag once the module is disabled (ADPU=0).
8.5.2.3
Step 3
Clear the SCF flag by writing a 1 in ATDSTAT0. (Remaining flags will be cleared with the next start of a conversions, but SCF flag should be cleared to avoid SCF interrupt.)
8.5.2.4
Step 4
Power down ATD by writing ADPU=0 in ATDCTL2.
8.6
Resets
At reset the ATD is in a power down state. The reset state of each individual bit is listed within the Register Description section (see Section 8.3, "Memory Map and Register Definition"), which details the registers and their bit-field.
8.7
Interrupts
The interrupt requested by the ATD is listed in Table 8-24. Refer to the device overview chapter for related vector address and priority.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 239
Chapter 8 Analog-to-Digital Converter (ATD10B8CV3)
Table 8-24. ATD Interrupt Vectors
Interrupt Source Sequence complete interrupt CCR Mask I bit Local Enable ASCIE in ATDCTL2
See register descriptions for further details.
MC3S12RG128 Data Sheet, Rev. 1.05 240 Freescale Semiconductor
Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
9.1 Introduction
This specification describes the function of the clocks and reset generator (CRG).
9.1.1
Features
The main features of this block are: * Phase-locked loop (PLL) frequency multiplier -- Reference divider -- Automatic bandwidth control mode for low-jitter operation -- Automatic frequency lock detector -- CPU interrupt on entry or exit from locked condition -- Self-clock mode in absence of reference clock * System clock generator -- Clock quality check -- Clock switch for either oscillator- or PLL-based system clocks -- User selectable disabling of clocks during wait mode for reduced power consumption * Computer operating properly (COP) watchdog timer with time-out clear window * System reset generation from the following possible sources: -- Power-on reset -- Low voltage reset Refer to the device overview section for availability of this feature. -- COP reset -- Loss of clock reset -- External pin reset * Real-time interrupt (RTI)
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 241
Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
9.1.2
Modes of Operation
This subsection lists and briefly describes all operating modes supported by the CRG. * Run mode All functional parts of the CRG are running during normal run mode. If RTI or COP functionality is required the individual bits of the associated rate select registers (COPCTL, RTICTL) have to be set to a nonzero value. * Wait mode This mode allows to disable the system and core clocks depending on the configuration of the individual bits in the CLKSEL register. * Stop mode Depending on the setting of the PSTP bit, stop mode can be differentiated between full stop mode (PSTP = 0) and pseudo-stop mode (PSTP = 1). -- Full stop mode The oscillator is disabled and thus all system and core clocks are stopped. The COP and the RTI remain frozen. -- Pseudo-stop mode The oscillator continues to run and most of the system and core clocks are stopped. If the respective enable bits are set the COP and RTI will continue to run, else they remain frozen. * Self-clock mode Self-clock mode will be entered if the clock monitor enable bit (CME) and the self-clock mode enable bit (SCME) are both asserted and the clock monitor in the oscillator block detects a loss of clock. As soon as self-clock mode is entered the CRG starts to perform a clock quality check. Self-clock mode remains active until the clock quality check indicates that the required quality of the incoming clock signal is met (frequency and amplitude). Self-clock mode should be used for safety purposes only. It provides reduced functionality to the MCU in case a loss of clock is causing severe system conditions.
9.1.3
Block Diagram
Figure 9-1 shows a block diagram of the CRG.
MC3S12RG128 Data Sheet, Rev. 1.05 242 Freescale Semiconductor
Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
Voltage Regulator
Power-on Reset Low Voltage Reset 1
CRG
RESET
COP Timeout
XCLKS EXTAL XTAL
Clock Monitor
CM fail
Reset Generator Clock Quality Checker COP RTI
System Reset
OSCCLK
Oscillator
Bus Clock Core Clock Oscillator Clock
Registers
XFC VDDPLL VSSPLL PLLCLK
PLL
Clock and Reset Control
Real-Time Interrupt PLL Lock Interrupt Self-Clock Mode Interrupt
1
Refer to the device overview section for availability of the low-voltage reset feature.
Figure 9-1. CRG Block Diagram
9.2
External Signal Description
This section lists and describes the signals that connect off chip.
9.2.1
VDDPLL, VSSPLL -- PLL Operating Voltage, PLL Ground
These pins provides operating voltage (VDDPLL) and ground (VSSPLL) for the PLL circuitry. This allows the supply voltage to the PLL to be independently bypassed. Even if PLL usage is not required VDDPLL and VSSPLL must be connected properly.
9.2.2
XFC -- PLL Loop Filter Pin
A passive external loop filter must be placed on the XFC pin. The filter is a second-order, low-pass filter to eliminate the VCO input ripple. The value of the external filter network and the reference frequency determines the speed of the corrections and the stability of the PLL. Refer to the device overview chapter for calculation of PLL loop filter (XFC) components. If PLL usage is not required the XFC pin must be tied to VDDPLL.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 243
Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
VDDPLL
CS MCU RS
CP
XFC
Figure 9-2. PLL Loop Filter Connections
9.2.3
RESET -- Reset Pin
RESET is an active low bidirectional reset pin. As an input it initializes the MCU asynchronously to a known start-up state. As an open-drain output it indicates that an system reset (internal to MCU) has been triggered.
9.3
Memory Map and Register Definition
This section provides a detailed description of all registers accessible in the CRG.
9.3.1
Register Descriptions
This section describes in address order all the CRG registers and their individual bits.
Register Name 0x0000 SYNR 0x0001 REFDV 0x0002 CTFLG 0x0003 CRGFLG 0x0004 CRGINT R W R W R W R W R W RTIF PORF 0 LVRF 0 LOCKIF LOCK TRACK SCMIF SCM 0 0 0 0 0 0
Bit 7 0
6 0
5 SYN5 0
4 SYN4 0
3 SYN3
2 SYN2
1 SYN1
Bit 0 SYN0
REFDV3 0
REFDV2 0
REFDV1 0
REFDV0 0
RTIE
LOCKIE
0
0
SCMIE
0
= Unimplemented or Reserved
Figure 9-3. CRG Register Summary
MC3S12RG128 Data Sheet, Rev. 1.05 244 Freescale Semiconductor
Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
Register Name 0x0005 CLKSEL 0x0006 PLLCTL 0x0007 RTICTL 0x0008 COPCTL 0x0009 FORBYP 0x000A CTCTL 0x000B ARMCOP R W R W R W R W R W R W R W
Bit 7 PLLSEL
6 PSTP
5 SYSWAI
4 ROAWAI
3 PLLWAI 0
2 CWAI
1 RTIWAI
Bit 0 COPWAI
CME 0
PLLON
AUTO
ACQ
PRE
PCE
SCME
RTR6
RTR5 0
RTR4 0
RTR3 0
RTR2
RTR1
RTR0
WCOP 0 0
RSBCK 0 0
CR2 0 0
CR1 0 0
CR0 0 0
0 0
0 0
0 0
0 Bit 7
0 Bit 6
0 Bit 5
0 Bit 4
0 Bit 3
0 Bit 2
0 Bit 1
0 Bit 0
= Unimplemented or Reserved
Figure 9-3. CRG Register Summary (continued)
9.3.1.1
CRG Synthesizer Register (SYNR)
The SYNR register controls the multiplication factor of the PLL. If the PLL is on, the count in the loop divider (SYNR) register effectively multiplies up the PLL clock (PLLCLK) from the reference frequency by 2 x (SYNR+1). PLLCLK will not be below the minimum VCO frequency (fSCM).
( SYNR + 1 ) PLLCLK = 2xOSCCLKx --------------------------------( REFDV + 1 )
NOTE If PLL is selected (PLLSEL=1), Bus Clock = PLLCLK / 2 Bus Clock must not exceed the maximum operating system frequency.
Module Base + 0x0000
7 6 5 4 3 2 1 0
R W Reset
0
0 SYN5 SYNR 0 SYN3 0 SYN2 0 SYN1 0 SYN0 0
0
0
0
= Unimplemented or Reserved
Figure 9-4. CRG Synthesizer Register (SYNR)
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 245
Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
Read: anytime Write: anytime except if PLLSEL = 1 NOTE Write to this register initializes the lock detector bit and the track detector bit.
MC3S12RG128 Data Sheet, Rev. 1.05 246 Freescale Semiconductor
Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
9.3.1.2
CRG Reference Divider Register (REFDV)
The REFDV register provides a finer granularity for the PLL multiplier steps. The count in the reference divider divides OSCCLK frequency by REFDV + 1.
Module Base + 0x0001
7 6 5 4 3 2 1 0
R W Reset
0
0
0
0 REFDV3 REFDV2 0 REFDV1 0 REFDV0 0
0
0
0
0
0
= Unimplemented or Reserved
Figure 9-5. CRG Reference Divider Register (REFDV)
Read: anytime Write: anytime except when PLLSEL = 1 NOTE Write to this register initializes the lock detector bit and the track detector bit.
9.3.1.3
Reserved Register (CTFLG)
This register is reserved for factory testing of the CRG module and is not available in normal modes.
Module Base + 0x0002
7 6 5 4 3 2 1 0
R W Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 9-6. CRG Reserved Register (CTFLG)
Read: always reads 0x0000 in normal modes Write: unimplemented in normal modes NOTE Writing to this register when in special mode can alter the CRG functionality.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 247
Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
9.3.1.4
CRG Flags Register (CRGFLG)
This register provides CRG status bits and flags.
Module Base + 0x0003
7 6 5 4 3 2 1 0
R RTIF W Reset 0 Note 1 Note 2 0 PORF LVRF LOCKIF
LOCK
TRACK SCMIF
SCM
0
0
0
0
1. PORF is set to 1 when a power-on reset occurs. Unaffected by system reset. 2. LVRF is set to 1 when a low-voltage reset occurs. Unaffected by system reset. = Unimplemented or Reserved
Figure 9-7. CRG Flag Register (CRGFLG)
Read: anytime Write: refer to each bit for individual write conditions
Table 9-1. CRGFLG Field Descriptions
Field 7 RTIF Description Real-Time Interrupt Flag -- RTIF is set to 1 at the end of the RTI period. This flag can only be cleared by writing a 1. Writing a 0 has no effect. If enabled (RTIE = 1), RTIF causes an interrupt request. 0 RTI time-out has not yet occurred. 1 RTI time-out has occurred. Power-on Reset Flag -- PORF is set to 1 when a power-on reset occurs. This flag can only be cleared by writing a 1. Writing a 0 has no effect. 0 Power-on reset has not occurred. 1 Power-on reset has occurred. Low-Voltage Reset Flag -- If low voltage reset feature is not available (see the device overview chapter), LVRF always reads 0. LVRF is set to 1 when a low voltage reset occurs. This flag can only be cleared by writing a 1. Writing a 0 has no effect. 0 Low voltage reset has not occurred. 1 Low voltage reset has occurred. PLL Lock Interrupt Flag -- LOCKIF is set to 1 when LOCK status bit changes. This flag can only be cleared by writing a 1. Writing a 0 has no effect.If enabled (LOCKIE = 1), LOCKIF causes an interrupt request. 0 No change in LOCK bit. 1 LOCK bit has changed. Lock Status Bit -- LOCK reflects the current state of PLL lock condition. This bit is cleared in self-clock mode. Writes have no effect. 0 PLL VCO is not within the desired tolerance of the target frequency. 1 PLL VCO is within the desired tolerance of the target frequency. Track Status Bit -- TRACK reflects the current state of PLL track condition. This bit is cleared in self-clock mode. Writes have no effect. 0 Acquisition mode status. 1 Tracking mode status.
6 PORF
5 LVRF
4 LOCKIF
3 LOCK
2 TRACK
MC3S12RG128 Data Sheet, Rev. 1.05 248 Freescale Semiconductor
Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
Table 9-1. CRGFLG Field Descriptions (continued)
Field 1 SCMIF Description Self-Clock Mode Interrupt Flag -- SCMIF is set to 1 when SCM status bit changes. This flag can only be cleared by writing a 1. Writing a 0 has no effect. If enabled (SCMIE=1), SCMIF causes an interrupt request. 0 No change in SCM bit. 1 SCM bit has changed. Self-Clock Mode Status Bit -- SCM reflects the current clocking mode. Writes have no effect. 0 MCU is operating normally with OSCCLK available. 1 MCU is operating in self-clock mode with OSCCLK in an unknown state. All clocks are derived from PLLCLK running at its minimum frequency fSCM.
0 SCM
9.3.1.5
CRG Interrupt Enable Register (CRGINT)
This register enables CRG interrupt requests.
Module Base + 0x0004
7 6 5 4 3 2 1 0
R RTIE W Reset 0
0
0 LOCKIE
0
0 SCMIE
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 9-8. CRG Interrupt Enable Register (CRGINT)
Read: anytime Write: anytime
Table 9-2. CRGINT Field Descriptions
Field 7 RTIE 4 LOCKIE 1 SCMIE Description Real-Time Interrupt Enable Bit 0 Interrupt requests from RTI are disabled. 1 Interrupt will be requested whenever RTIF is set. Lock Interrupt Enable Bit 0 LOCK interrupt requests are disabled. 1 Interrupt will be requested whenever LOCKIF is set. Self-Clock Mode Interrupt Enable Bit 0 SCM interrupt requests are disabled. 1 Interrupt will be requested whenever SCMIF is set.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 249
Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
9.3.1.6
CRG Clock Select Register (CLKSEL)
This register controls CRG clock selection. Refer to Figure 9-17 for details on the effect of each bit.
Module Base + 0x0005
7 6 5 4 3 2 1 0
R PLLSEL W Reset 0 0 0 0 0 0 0 0 PSTP SYSWAI ROAWAI PLLWAI CWAI RTIWAI COPWAI
Figure 9-9. CRG Clock Select Register (CLKSEL)
Read: anytime Write: refer to each bit for individual write conditions
Table 9-3. CLKSEL Field Descriptions
Field 7 PLLSEL Description PLL Select Bit -- Write anytime. Writing a 1 when LOCK = 0 and AUTO = 1, or TRACK = 0 and AUTO = 0 has no effect. This prevents the selection of an unstable PLLCLK as SYSCLK. PLLSEL bit is cleared when the MCU enters self-clock mode, stop mode or wait mode with PLLWAI bit set. 0 System clocks are derived from OSCCLK (Bus Clock = OSCCLK / 2). 1 System clocks are derived from PLLCLK (Bus Clock = PLLCLK / 2). Pseudo-Stop Bit -- Write: anytime -- This bit controls the functionality of the oscillator during stop mode. 0 Oscillator is disabled in stop mode. 1 Oscillator continues to run in stop mode (pseudo-stop). The oscillator amplitude is reduced. Refer to oscillator block description for availability of a reduced oscillator amplitude. Note: Pseudo-stop allows for faster stop recovery and reduces the mechanical stress and aging of the resonator in case of frequent stop conditions at the expense of a slightly increased power consumption. Note: Lower oscillator amplitude exhibits lower power consumption but could have adverse effects during any electro-magnetic susceptibility (EMS) tests. System Clocks Stop in Wait Mode Bit -- Write: anytime 0 In wait mode, the system clocks continue to run. 1 In wait mode, the system clocks stop. Note: RTI and COP are not affected by SYSWAI bit. Reduced Oscillator Amplitude in Wait Mode Bit -- Write: anytime -- Refer to oscillator block description chapter for availability of a reduced oscillator amplitude. If no such feature exists in the oscillator block then setting this bit to 1 will not have any effect on power consumption. 0 Normal oscillator amplitude in wait mode. 1 Reduced oscillator amplitude in wait mode. Note: Lower oscillator amplitude exhibits lower power consumption but could have adverse effects during any electro-magnetic susceptibility (EMS) tests. PLL Stops in Wait Mode Bit -- Write: anytime -- If PLLWAI is set, the CRG will clear the PLLSEL bit before entering wait mode. The PLLON bit remains set during wait mode but the PLL is powered down. Upon exiting wait mode, the PLLSEL bit has to be set manually if PLL clock is required. While the PLLWAI bit is set the AUTO bit is set to 1 in order to allow the PLL to automatically lock on the selected target frequency after exiting wait mode. 0 PLL keeps running in wait mode. 1 PLL stops in wait mode.
6 PSTP
5 SYSWAI
4 ROAWAI
3 PLLWAI
MC3S12RG128 Data Sheet, Rev. 1.05 250 Freescale Semiconductor
Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
Table 9-3. CLKSEL Field Descriptions (continued)
Field 2 CWAI 1 RTIWAI 0 COPWAI Core Stops in Wait Mode Bit -- Write: anytime 0 Core clock keeps running in wait mode. 1 Core clock stops in wait mode. RTI Stops in Wait Mode Bit -- Write: anytime 0 RTI keeps running in wait mode. 1 RTI stops and initializes the RTI dividers whenever the part goes into wait mode. COP Stops in Wait Mode Bit -- Normal modes: Write once --Special modes: Write anytime 0 COP keeps running in wait mode. 1 COP stops and initializes the COP dividers whenever the part goes into wait mode. Description
9.3.1.7
CRG PLL Control Register (PLLCTL)
This register controls the PLL functionality.
Module Base + 0x0006
7 6 5 4 3 2 1 0
R CME W Reset 1 1 1 1 PLLON AUTO ACQ
0 PRE 0 0 PCE 0 SCME 1
= Unimplemented or Reserved
Figure 9-10. CRG PLL Control Register (PLLCTL)
Read: anytime Write: refer to each bit for individual write conditions
Table 9-4. PLLCTL Field Descriptions
Field 7 CME Description Clock Monitor Enable Bit -- CME enables the clock monitor. Write anytime except when SCM = 1. 0 Clock monitor is disabled. 1 Clock monitor is enabled. Slow or stopped clocks will cause a clock monitor reset sequence or self-clock mode. Note: Operating with CME = 0 will not detect any loss of clock. In case of poor clock quality this could cause unpredictable operation of the MCU. Note: In Stop Mode (PSTP = 0) the clock monitor is disabled independently of the CME bit setting and any loss of clock will not be detected. Phase Lock Loop On Bit -- PLLON turns on the PLL circuitry. In self-clock mode, the PLL is turned on, but the PLLON bit reads the last latched value. Write anytime except when PLLSEL = 1. 0 PLL is turned off. 1 PLL is turned on. If AUTO bit is set, the PLL will lock automatically.
6 PLLON
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 251
Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
Table 9-4. PLLCTL Field Descriptions (continued)
Field 5 AUTO Description Automatic Bandwidth Control Bit -- AUTO selects either the high bandwidth (acquisition) mode or the low bandwidth (tracking) mode depending on how close to the desired frequency the VCO is running. Write anytime except when PLLWAI=1, because PLLWAI sets the AUTO bit to 1. 0 Automatic mode control is disabled and the PLL is under software control, using ACQ bit. 1 Automatic mode control is enabled and ACQ bit has no effect. Acquisition Bit -- Write anytime. If AUTO=1 this bit has no effect. 0 Low bandwidth filter is selected. 1 High bandwidth filter is selected. RTI Enable during Pseudo-Stop Bit -- PRE enables the RTI during pseudo-stop mode. Write anytime. 0 RTI stops running during pseudo-stop mode. 1 RTI continues running during pseudo-stop mode. Note: If the PRE bit is cleared the RTI dividers will go static while pseudo-stop mode is active. The RTI dividers will not initialize like in wait mode with RTIWAI bit set. COP Enable during Pseudo-Stop Bit -- PCE enables the COP during pseudo-stop mode. Write anytime. 0 COP stops running during pseudo-stop mode 1 COP continues running during pseudo-stop mode Note: If the PCE bit is cleared the COP dividers will go static while pseudo-stop mode is active. The COP dividers will not initialize like in wait mode with COPWAI bit set. Self-Clock Mode Enable Bit -- Normal modes: Write once --Special modes: Write anytime -- SCME can not be cleared while operating in self-clock mode (SCM=1). 0 Detection of crystal clock failure causes clock monitor reset (see Section 9.5.1, "Clock Monitor Reset"). 1 Detection of crystal clock failure forces the MCU in self-clock mode (see Section 9.4.7.2, "Self-Clock Mode").
4 ACQ 2 PRE
1 PCE
0 SCME
9.3.1.8
CRG RTI Control Register (RTICTL)
This register selects the timeout period for the real-time interrupt.
Module Base + 0x0007
7 6 5 4 3 2 1 0
R W Reset
0 RTR6 0 0 RTR5 0 RTR4 0 RTR3 0 RTR2 0 RTR1 0 RTR0 0
= Unimplemented or Reserved
Figure 9-11. CRG RTI Control Register (RTICTL)
Read: anytime Write: anytime NOTE A write to this register initializes the RTI counter.
MC3S12RG128 Data Sheet, Rev. 1.05 252 Freescale Semiconductor
Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
Table 9-5. RTICTL Field Descriptions
Field 6:4 RTR[6:4] 3:0 RTR[3:0] Description Real-Time Interrupt Prescale Rate Select Bits -- These bits select the prescale rate for the RTI. See Table 9-6. Real-Time Interrupt Modulus Counter Select Bits -- These bits select the modulus counter target value to provide additional granularity. Table 9-6 shows all possible divide values selectable by the RTICTL register. The source clock for the RTI is OSCCLK.
Table 9-6. RTI Frequency Divide Rates
RTR[6:4] = RTR[3:0] 000 (OFF) OFF* OFF* OFF* OFF* OFF* OFF* OFF* OFF* OFF* OFF* OFF* OFF* OFF* OFF* OFF* OFF* 001 (210) 210 2x210 3x210 4x210 5x210 6x210 7x210 8x210 9x210 10x210 11x210 12x210 13x210 14x210 15x210 16x210 010 (211) 211 2x211 3x211 4x211 5x211 6x211 7x211 8x211 9x211 10x211 11x211 12x211 13x211 14x211 15x211 16x211 011 (212) 212 2x212 3x212 4x212 5x212 6x212 7x212 8x212 9x212 10x212 11x212 12x212 13x212 14x212 15x212 16x212 100 (213) 213 2x213 3x213 4x213 5x213 6x213 7x213 8x213 9x213 10x213 11x213 12x213 13x213 14x213 15x213 16x213 101 (214) 214 2x214 3x214 4x214 5x214 6x214 7x214 8x214 9x214 10x214 11x214 12x214 13x214 14x214 15x214 16x214 110 (215) 215 2x215 3x215 4x215 5x215 6x215 7x215 8x215 9x215 10x215 11x215 12x215 13x215 14x215 15x215 16x215 111 (216) 216 2x216 3x216 4x216 5x216 6x216 7x216 8x216 9x216 10x216 11x216 12x216 13x216 14x216 15x216 16x216
0000 (/1) 0001 (/2) 0010 (/3) 0011 (/4) 0100 (/5) 0101 (/6) 0110 (/7) 0111 (/8) 1000 (/9) 1001 (/10) 1010 (/11) 1011 (/12) 1100 (/ 13) 1101 (/14) 1110 (/15) 1111 (/ 16)
* Denotes the default value out of reset.This value should be used to disable the RTI to ensure future backwards compatibility.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 253
Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
9.3.1.9
CRG COP Control Register (COPCTL)
This register controls the COP (computer operating properly) watchdog.
Module Base + 0x0008
7 6 5 4 3 2 1 0
R WCOP W Reset 0 0 RSBCK
0
0
0 CR2 CR1 0 CR0 0
0
0
0
0
= Unimplemented or Reserved
Read: anytime
Figure 9-12. CRG COP Control Register (COPCTL)
Write: WCOP, CR2, CR1, CR0: once in user mode, anytime in special mode Write: RSBCK: once
Table 9-7. COPCTL Field Descriptions
Field 7 WCOP Description Window COP Mode Bit -- When set, a write to the ARMCOP register must occur in the last 25% of the selected period. A write during the first 75% of the selected period will reset the part. As long as all writes occur during this window, 0x0055 can be written as often as desired. As soon as 0x00AA is written after the 0x0055, the time-out logic restarts and the user must wait until the next window before writing to ARMCOP. Table 9-8 shows the exact duration of this window for the seven available COP rates. 0 Normal COP operation 1 Window COP operation COP and RTI Stop in Active BDM Mode Bit 0 Allows the COP and RTI to keep running in active BDM mode. 1 Stops the COP and RTI counters whenever the part is in active BDM mode. COP Watchdog Timer Rate Select -- These bits select the COP time-out rate (see Table 9-8). The COP time-out period is OSCCLK period divided by CR[2:0] value. Writing a nonzero value to CR[2:0] enables the COP counter and starts the time-out period. A COP counter time-out causes a system reset. This can be avoided by periodically (before time-out) reinitializing the COP counter via the ARMCOP register.
6 RSBCK 2:0 CR[2:0]
Table 9-8. COP Watchdog Rates1
CR2 0 0 0 0 1 1 1 1
1
CR1 0 0 1 1 0 0 1 1
CR0 0 1 0 1 0 1 0 1
OSCCLK Cycles to Time Out COP disabled 214 216 218 220 222 223 224
OSCCLK cycles are referenced from the previous COP time-out reset (writing 0x0055/0x00AA to the ARMCOP register)
MC3S12RG128 Data Sheet, Rev. 1.05 254 Freescale Semiconductor
Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
9.3.1.10
Reserved Register (FORBYP)
NOTE This reserved register is designed for factory test purposes only, and is not intended for general user access. Writing to this register when in special modes can alter the CRG's functionality.
Module Base + 0x0009
7 6 5 4 3 2 1 0
R W Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 9-13. Reserved Register (FORBYP)
Read: always read 0x0000 except in special modes Write: only in special modes
9.3.1.11
Reserved Register (CTCTL)
NOTE This reserved register is designed for factory test purposes only, and is not intended for general user access. Writing to this register when in special test modes can alter the CRG's functionality.
Module Base + 0x000A
7 6 5 4 3 2 1 0
R W Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 9-14. Reserved Register (CTCTL)
Read: always read 0x0080 except in special modes Write: only in special modes
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 255
Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
9.3.1.12
CRG COP Timer Arm/Reset Register (ARMCOP)
This register is used to restart the COP time-out period.
Module Base + 0x000B
7 6 5 4 3 2 1 0
R W Reset
0 Bit 7 0
0 Bit 6 0
0 Bit 5 0
0 Bit 4 0
0 Bit 3 0
0 Bit 2 0
0 Bit 1 0
0 Bit 0 0
Figure 9-15. ARMCOP Register Diagram
Read: always reads 0x0000 Write: anytime When the COP is disabled (CR[2:0] = "000") writing to this register has no effect. When the COP is enabled by setting CR[2:0] nonzero, the following applies: Writing any value other than 0x0055 or 0x00AA causes a COP reset. To restart the COP time-out period you must write 0x0055 followed by a write of 0x00AA. Other instructions may be executed between these writes but the sequence (0x0055, 0x00AA) must be completed prior to COP end of time-out period to avoid a COP reset. Sequences of 0x0055 writes or sequences of 0x00AA writes are allowed. When the WCOP bit is set, 0x0055 and 0x00AA writes must be done in the last 25% of the selected time-out period; writing any value in the first 75% of the selected period will cause a COP reset.
9.4
Functional Description
This section gives detailed informations on the internal operation of the design.
9.4.1
Phase Locked Loop (PLL)
The PLL is used to run the MCU from a different time base than the incoming OSCCLK. For increased flexibility, OSCCLK can be divided in a range of 1 to 16 to generate the reference frequency. This offers a finer multiplication granularity. The PLL can multiply this reference clock by a multiple of 2, 4, 6,... 126,128 based on the SYNR register.
[ SYNR + 1 ] PLLCLK = 2 x OSCCLK x --------------------------------[ REFDV + 1 ]
CAUTION Although it is possible to set the two dividers to command a very high clock frequency, do not exceed the specified bus frequency limit for the MCU. If (PLLSEL = 1), Bus Clock = PLLCLK / 2
MC3S12RG128 Data Sheet, Rev. 1.05 256 Freescale Semiconductor
Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
The PLL is a frequency generator that operates in either acquisition mode or tracking mode, depending on the difference between the output frequency and the target frequency. The PLL can change between acquisition and tracking modes either automatically or manually. The VCO has a minimum operating frequency, which corresponds to the self-clock mode frequency fSCM.
REFERENCE EXTAL REDUCED CONSUMPTION OSCILLATOR XTAL OSCCLK REFDV <3:0> FEEDBACK LOCK DETECTOR LOCK
REFERENCE PROGRAMMABLE DIVIDER
VDDPLL/VSSPLL PDET PHASE DETECTOR UP DOWN CPUMP VCO
CRYSTAL MONITOR
LOOP PROGRAMMABLE DIVIDER SYN <5:0>
VDDPLL LOOP FILTER XFC PIN PLLCLK
supplied by:
VDDPLL/VSSPLL VDD/VSS
Figure 9-16. PLL Functional Diagram
9.4.1.1
PLL Operation
The oscillator output clock signal (OSCCLK) is fed through the reference programmable divider and is divided in a range of 1 to 16 (REFDV+1) to output the reference clock. The VCO output clock, (PLLCLK) is fed back through the programmable loop divider and is divided in a range of 2 to 128 in increments of [2 x (SYNR +1)] to output the feedback clock. See Figure 9-16. The phase detector then compares the feedback clock, with the reference clock. Correction pulses are generated based on the phase difference between the two signals. The loop filter then slightly alters the DC voltage on the external filter capacitor connected to XFC pin, based on the width and direction of the correction pulse. The filter can make fast or slow corrections depending on its mode, as described in the next subsection. The values of the external filter network and the reference frequency determine the speed of the corrections and the stability of the PLL.
9.4.1.2
Acquisition and Tracking Modes
The lock detector compares the frequencies of the feedback clock, and the reference clock. Therefore, the speed of the lock detector is directly proportional to the final reference frequency. The circuit determines the mode of the PLL and the lock condition based on this comparison.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 257
Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
The PLL filter can be manually or automatically configured into one of two possible operating modes: * Acquisition mode In acquisition mode, the filter can make large frequency corrections to the VCO. This mode is used at PLL start-up or when the PLL has suffered a severe noise hit and the VCO frequency is far off the desired frequency. When in acquisition mode, the TRACK status bit is cleared in the CRGFLG register. * Tracking mode In tracking mode, the filter makes only small corrections to the frequency of the VCO. PLL jitter is much lower in tracking mode, but the response to noise is also slower. The PLL enters tracking mode when the VCO frequency is nearly correct and the TRACK bit is set in the CRGFLG register. The PLL can change the bandwidth or operational mode of the loop filter manually or automatically. In automatic bandwidth control mode (AUTO = 1), the lock detector automatically switches between acquisition and tracking modes. Automatic bandwidth control mode also is used to determine when the PLL clock (PLLCLK) is safe to use as the source for the system and core clocks. If PLL LOCK interrupt requests are enabled, the software can wait for an interrupt request and then check the LOCK bit. If CPU interrupts are disabled, software can poll the LOCK bit continuously (during PLL start-up, usually) or at periodic intervals. In either case, only when the LOCK bit is set, is the PLLCLK clock safe to use as the source for the system and core clocks. If the PLL is selected as the source for the system and core clocks and the LOCK bit is clear, the PLL has suffered a severe noise hit and the software must take appropriate action, depending on the application. The following conditions apply when the PLL is in automatic bandwidth control mode (AUTO = 1): * The TRACK bit is a read-only indicator of the mode of the filter. * The TRACK bit is set when the VCO frequency is within a certain tolerance, trk, and is clear when the VCO frequency is out of a certain tolerance, unt. * The LOCK bit is a read-only indicator of the locked state of the PLL. * The LOCK bit is set when the VCO frequency is within a certain tolerance, Lock, and is cleared when the VCO frequency is out of a certain tolerance, unl. * CPU interrupts can occur if enabled (LOCKIE = 1) when the lock condition changes, toggling the LOCK bit. The PLL can also operate in manual mode (AUTO = 0). Manual mode is used by systems that do not require an indicator of the lock condition for proper operation. Such systems typically operate well below the maximum system frequency (fsys) and require fast start-up. The following conditions apply when in manual mode: * ACQ is a writable control bit that controls the mode of the filter. Before turning on the PLL in manual mode, the ACQ bit should be asserted to configure the filter in acquisition mode. * After turning on the PLL by setting the PLLON bit software must wait a given time (tacq) before entering tracking mode (ACQ = 0). * After entering tracking mode software must wait a given time (tal) before selecting the PLLCLK as the source for system and core clocks (PLLSEL = 1).
MC3S12RG128 Data Sheet, Rev. 1.05 258 Freescale Semiconductor
Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
9.4.2
System Clocks Generator
PLLSEL or SCM WAIT(CWAI,SYSWAI), STOP PHASE LOCK LOOP PLLCLK
1 0
SYSCLK Core Clock WAIT(SYSWAI), STOP SCM WAIT(RTIWAI), STOP(PSTP,PRE), RTI enable /2 CLOCK PHASE GENERATOR Bus Clock
EXTAL OSCILLATOR OSCCLK
1
RTI
0
XTAL
WAIT(COPWAI), STOP(PSTP,PCE), COP enable Clock Monitor WAIT(SYSWAI), STOP Oscillator Clock COP
STOP(PSTP) Gating Condition = Clock Gate Oscillator Clock (running during Pseudo-Stop Mode
Figure 9-17. System Clocks Generator
The clock generator creates the clocks used in the MCU (see Figure 9-17). The gating condition placed on top of the individual clock gates indicates the dependencies of different modes (stop, wait) and the setting of the respective configuration bits. The peripheral modules use the bus clock. Some peripheral modules also use the oscillator clock. The memory blocks use the bus clock. If the MCU enters self-clock mode (see Section 9.4.7.2, "Self-Clock Mode"), oscillator clock source is switched to PLLCLK running at its minimum frequency fSCM. The bus clock is used to generate the clock visible at the ECLK pin. The core clock signal is the clock for the CPU. The core clock is twice the bus clock as shown in Figure 9-18. But note that a CPU cycle corresponds to one bus clock. PLL clock mode is selected with PLLSEL bit in the CLKSEL register. When selected, the PLL output clock drives SYSCLK for the main system including the CPU and peripherals. The PLL cannot be turned off by clearing the PLLON bit, if the PLL clock is selected. When PLLSEL is changed, it takes a maximum
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 259
Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
of 4 OSCCLK plus 4 PLLCLK cycles to make the transition. During the transition, all clocks freeze and CPU activity ceases.
CORE CLOCK:
BUS CLOCK / ECLK
Figure 9-18. Core Clock and Bus Clock Relationship
9.4.3
Clock Monitor (CM)
If no OSCCLK edges are detected within a certain time, the clock monitor within the oscillator block generates a clock monitor fail event. The CRG then asserts self-clock mode or generates a system reset depending on the state of SCME bit. If the clock monitor is disabled or the presence of clocks is detected no failure is indicated by the oscillator block.The clock monitor function is enabled/disabled by the CME control bit.
9.4.4
Clock Quality Checker
The clock monitor performs a coarse check on the incoming clock signal. The clock quality checker provides a more accurate check in addition to the clock monitor. A clock quality check is triggered by any of the following events: * Power-on reset (POR) * Low voltage reset (LVR) * Wake-up from full stop mode (exit full stop) * Clock monitor fail indication (CM fail) A time window of 50000 VCO clock cycles1 is called check window. A number greater equal than 4096 rising OSCCLK edges within a check window is called osc ok. Note that osc ok immediately terminates the current check window. See Figure 9-19 as an example.
1. VCO clock cycles are generated by the PLL when running at minimum frequency fSCM. MC3S12RG128 Data Sheet, Rev. 1.05 260 Freescale Semiconductor
Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
check window 1 2 3 49999 50000
VCO clock OSCCLK
12345
4096 4095 osc ok
Figure 9-19. Check Window Example
The sequence for clock quality check is shown in Figure 9-20.
CM fail Clock OK POR LVR exit full stop Clock Monitor Reset Enter SCM num=0 yes no SCM active? num=50
check window
num=num+1 yes yes no SCME=1 ? no
osc ok ? yes SCM active? no
no
num<50 ?
yes
Switch to OSCCLK
Exit SCM
Figure 9-20. Sequence for Clock Quality Check
NOTE Remember that in parallel to additional actions caused by self-clock mode or clock monitor reset1 handling the clock quality checker continues to check the OSCCLK signal.
1. A Clock Monitor Reset will always set the SCME bit to logical'1'
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 261
Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
NOTE The clock quality checker enables the PLL and the voltage regulator (VREG) anytime a clock check has to be performed. An ongoing clock quality check could also cause a running PLL (fSCM) and an active VREG during pseudo-stop mode or wait mode
9.4.5
Computer Operating Properly Watchdog (COP)
WAIT(COPWAI), STOP(PSTP,PCE), COP enable OSCCLK CR[2:0] 0:0:0 CR[2:0] 0:0:1
/ 16384 /4
/4 /4 /4 /2 /2 Figure 9-21. Clock Chain for COP
0:1:0
0:1:1
1:0:0
1:0:1
1:1:0
gating condition
= Clock Gate
1:1:1
COP TIMEOUT
The COP (free running watchdog timer) enables the user to check that a program is running and sequencing properly. The COP is disabled out of reset. When the COP is being used, software is responsible for keeping the COP from timing out. If the COP times out it is an indication that the software is no longer being executed in the intended sequence; thus a system reset is initiated (see Section 9.5.2, "Computer Operating Properly Watchdog (COP) Reset)." The COP runs with a gated OSCCLK (see Section Figure 9-21., "Clock Chain for COP"). Three control bits in the COPCTL register allow selection of seven COP time-out periods. When COP is enabled, the program must write 0x0055 and 0x00AA (in this order) to the ARMCOP register during the selected time-out period. As soon as this is done, the COP time-out period is restarted. If the program fails to do this and the COP times out, the part will reset. Also, if any value other than 0x0055 or 0x00AA is written, the part is immediately reset. Windowed COP operation is enabled by setting WCOP in the COPCTL register. In this mode, writes to the ARMCOP register to clear the COP timer must occur in the last 25% of the selected time-out period. A premature write will immediately reset the part. If PCE bit is set, the COP will continue to run in pseudo-stop mode.
MC3S12RG128 Data Sheet, Rev. 1.05 262 Freescale Semiconductor
Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
9.4.6
Real-Time Interrupt (RTI)
The RTI can be used to generate a hardware interrupt at a fixed periodic rate. If enabled (by setting RTIE=1), this interrupt will occur at the rate selected by the RTICTL register. The RTI runs with a gated OSCCLK (see Section Figure 9-22., "Clock Chain for RTI"). At the end of the RTI time-out period the RTIF flag is set to 1 and a new RTI time-out period starts immediately. A write to the RTICTL register restarts the RTI time-out period. If the PRE bit is set, the RTI will continue to run in pseudo-stop mode.
.
WAIT(RTIWAI), STOP(PSTP,PRE), RTI enable OSCCLK
/ 1024
RTR[6:4] 0:0:0
0:0:1
/2 /2 /2 /2 /2
gating condition
= Clock Gate
0:1:0
0:1:1
1:0:0
1:0:1
1:1:0
/2
1:1:1 4-BIT MODULUS COUNTER (RTR[3:0])
RTI TIMEOUT
Figure 9-22. Clock Chain for RTI
9.4.7
9.4.7.1
Modes of Operation
Normal Mode
The CRG block behaves as described within this specification in all normal modes.
9.4.7.2
Self-Clock Mode
The VCO has a minimum operating frequency, fSCM. If the external clock frequency is not available due to a failure or due to long crystal start-up time, the bus clock and the core clock are derived from the VCO
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 263
Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
running at minimum operating frequency; this mode of operation is called self-clock mode. This requires CME = 1 and SCME = 1. If the MCU was clocked by the PLL clock prior to entering self-clock mode, the PLLSEL bit will be cleared. If the external clock signal has stabilized again, the CRG will automatically select OSCCLK to be the system clock and return to normal mode. See Section 9.4.4, "Clock Quality Checker" for more information on entering and leaving self-clock mode. NOTE In order to detect a potential clock loss, the CME bit should be always enabled (CME=1). If CME bit is disabled and the MCU is configured to run on PLL clock (PLLCLK), a loss of external clock (OSCCLK) will not be detected and will cause the system clock to drift towards the VCO's minimum frequency fSCM. As soon as the external clock is available again the system clock ramps up to its PLL target frequency. If the MCU is running on external clock any loss of clock will cause the system to go static.
9.4.8
Low-Power Operation in Run Mode
The RTI can be stopped by setting the associated rate select bits to 0. The COP can be stopped by setting the associated rate select bits to 0.
9.4.9
Low-Power Operation in Wait Mode
The WAI instruction puts the MCU in a low power consumption stand-by mode depending on setting of the individual bits in the CLKSEL register. All individual wait mode configuration bits can be superposed. This provides enhanced granularity in reducing the level of power consumption during wait mode. Table 9-9 lists the individual configuration bits and the parts of the MCU that are affected in wait mode.
Table 9-9. MCU Configuration During Wait Mode
PLLWAI PLL Core System RTI COP Oscillator
1
CWAI -- stopped -- -- -- --
SYSWAI -- stopped stopped -- -- --
RTIWAI -- -- -- stopped -- --
COPWAI -- -- -- -- stopped --
ROAWAI -- -- -- -- -- reduced1
stopped -- -- -- -- --
Refer to oscillator block description for availability of a reduced oscillator amplitude.
After executing the WAI instruction the core requests the CRG to switch MCU into wait mode. The CRG then checks whether the PLLWAI, CWAI and SYSWAI bits are asserted (see Figure 9-23). Depending on the configuration the CRG switches the system and core clocks to OSCCLK by clearing the PLLSEL bit, disables the PLL, disables the core clocks and finally disables the remaining system clocks. As soon as all clocks are switched off wait mode is active.
MC3S12RG128 Data Sheet, Rev. 1.05 264 Freescale Semiconductor
Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
Core req's Wait Mode.
PLLWAI=1 ?
no
yes
Clear PLLSEL, Disable PLL CWAI or SYSWAI=1 ?
no
yes
Disable
core clocks
SYSWAI=1 ?
no no
Enter Wait Mode Wait Mode left due to external reset
Exit Wait w. ext.RESET
yes
Disable system clocks CME=1 ?
no
INT ?
yes
CM fail ?
yes no
yes
Exit Wait w. CMRESET
no
SCME=1 ?
yes no
Exit Wait Mode
SCMIE=1 ? Generate SCM Interrupt (Wakeup from Wait)
yes
Exit Wait Mode SCM=1 ?
no
yes
Enter SCM
Enter SCM
Continue w. normal OP
Figure 9-23. Wait Mode Entry/Exit Sequence
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 265
Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
There are five different scenarios for the CRG to restart the MCU from wait mode: * External reset * Clock monitor reset * COP reset * Self-clock mode interrupt * Real-time interrupt (RTI) If the MCU gets an external reset during wait mode active, the CRG asynchronously restores all configuration bits in the register space to its default settings and starts the reset generator. After completing the reset sequence processing begins by fetching the normal reset vector. Wait mode is exited and the MCU is in run mode again. If the clock monitor is enabled (CME=1) the MCU is able to leave wait mode when loss of oscillator/external clock is detected by a clock monitor fail. If the SCME bit is not asserted the CRG generates a clock monitor fail reset (CMRESET). The CRG's behavior for CMRESET is the same compared to external reset, but another reset vector is fetched after completion of the reset sequence. If the SCME bit is asserted the CRG generates a SCM interrupt if enabled (SCMIE=1). After generating the interrupt the CRG enters self-clock mode and starts the clock quality checker (see Section 9.4.4, "Clock Quality Checker"). Then the MCU continues with normal operation.If the SCM interrupt is blocked by SCMIE = 0, the SCMIF flag will be asserted and clock quality checks will be performed but the MCU will not wake-up from wait mode. If any other interrupt source (e.g. RTI) triggers exit from wait mode the MCU immediately continues with normal operation. If the PLL has been powered-down during wait mode the PLLSEL bit is cleared and the MCU runs on OSCCLK after leaving wait mode. The software must manually set the PLLSEL bit again, in order to switch system and core clocks to the PLLCLK. If wait mode is entered from self-clock mode, the CRG will continue to check the clock quality until clock check is successful. The PLL and voltage regulator (VREG) will remain enabled. Table 9-10 summarizes the outcome of a clock loss while in wait mode.
MC3S12RG128 Data Sheet, Rev. 1.05 266 Freescale Semiconductor
Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
Table 9-10. Outcome of Clock Loss in Wait Mode
CME 0 1 1 SCME X 0 1 SCMIE X X 0 Clock failure --> No action, clock loss not detected. Clock failure --> CRG performs Clock Monitor Reset immediately Clock failure --> Scenario 1: OSCCLK recovers prior to exiting Wait Mode. - MCU remains in Wait Mode, - VREG enabled, - PLL enabled, - SCM activated, - Start Clock Quality Check, - Set SCMIF interrupt flag. Some time later OSCCLK recovers. - CM no longer indicates a failure, - 4096 OSCCLK cycles later Clock Quality Check indicates clock o.k., - SCM deactivated, - PLL disabled depending on PLLWAI, - VREG remains enabled (never gets disabled in Wait Mode). - MCU remains in Wait Mode. Some time later either a wakeup interrupt occurs (no SCM interrupt) - Exit Wait Mode using OSCCLK as system clock (SYSCLK), - Continue normal operation. or an External Reset is applied. - Exit Wait Mode using OSCCLK as system clock, - Start reset sequence. Scenario 2: OSCCLK does not recover prior to exiting Wait Mode. - MCU remains in Wait Mode, - VREG enabled, - PLL enabled, - SCM activated, - Start Clock Quality Check, - Set SCMIF interrupt flag, - Keep performing Clock Quality Checks (could continue infinitely) while in Wait Mode. Some time later either a wakeup interrupt occurs (no SCM interrupt) - Exit Wait Mode in SCM using PLL clock (fSCM) as system clock, - Continue to perform additional Clock Quality Checks until OSCCLK is o.k. again. or an External RESET is applied. - Exit Wait Mode in SCM using PLL clock (fSCM) as system clock, - Start reset sequence, - Continue to perform additional Clock Quality Checks until OSCCLK is o.k.again. CRG Actions
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 267
Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
Table 9-10. Outcome of Clock Loss in Wait Mode (continued)
CME 1 SCME 1 SCMIE 1 Clock failure --> - VREG enabled, - PLL enabled, - SCM activated, - Start Clock Quality Check, - SCMIF set. SCMIF generates Self-Clock Mode wakeup interrupt. - Exit Wait Mode in SCM using PLL clock (fSCM) as system clock, - Continue to perform a additional Clock Quality Checks until OSCCLK is o.k. again. CRG Actions
9.4.10
Low-Power Operation in Stop Mode
All clocks are stopped in STOP mode, dependent of the setting of the PCE, PRE and PSTP bit. The oscillator is disabled in STOP mode unless the PSTP bit is set. All counters and dividers remain frozen but do not initialize. If the PRE or PCE bits are set, the RTI or COP continues to run in pseudo-stop mode. In addition to disabling system and core clocks the CRG requests other functional units of the MCU (e.g. voltage-regulator) to enter their individual power-saving modes (if available). This is the main difference between pseudo-stop mode and wait mode. After executing the STOP instruction the core requests the CRG to switch the MCU into stop mode. If the PLLSEL bit remains set when entering stop mode, the CRG will switch the system and core clocks to OSCCLK by clearing the PLLSEL bit. Then the CRG disables the PLL, disables the core clock and finally disables the remaining system clocks. As soon as all clocks are switched off, stop mode is active. If pseudo-stop mode (PSTP = 1) is entered from self-clock mode the CRG will continue to check the clock quality until clock check is successful. The PLL and the voltage regulator (VREG) will remain enabled. If full stop mode (PSTP = 0) is entered from self-clock mode an ongoing clock quality check will be stopped. A complete timeout window check will be started when stop mode is exited again. Wake-up from stop mode also depends on the setting of the PSTP bit.
MC3S12RG128 Data Sheet, Rev. 1.05 268 Freescale Semiconductor
Chapter 9 Clocks and Reset Generator (CRGV4) Block Description Core req's Stop Mode. Clear PLLSEL, Disable PLL
Exit Stop w. ext.RESET
Wait Mode left due to external
Enter Stop Mode
no
INT ?
no
PSTP=1 ?
yes
CME=1 ?
no
INT ?
no
yes
yes
CM fail ?
yes no
no
Clock OK ?
Exit Stop w. CMRESET
no
SCME=1 ?
yes yes
Exit Stop w. CMRESET
yes
no
SCME=1 ?
yes
SCMIE=1 ? Generate SCM Interrupt (Wakeup from Stop)
no
Exit Stop Mode
yes
Exit Stop Mode SCM=1 ?
Exit Stop Mode
Exit Stop Mode
no
yes
Enter SCM
Enter SCM
Enter SCM
Continue w. normal OP
Figure 9-24. Stop Mode Entry/Exit Sequence
9.4.10.1
Wake-Up from Pseudo-Stop (PSTP=1)
Wake-up from pseudo-stop is the same as wake-up from wait mode. There are also three different scenarios for the CRG to restart the MCU from pseudo-stop mode: * * * External reset Clock monitor fail Wake-up interrupt
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 269
Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
If the MCU gets an external reset during pseudo-stop mode active, the CRG asynchronously restores all configuration bits in the register space to its default settings and starts the reset generator. After completing the reset sequence processing begins by fetching the normal reset vector. Pseudo-stop mode is exited and the MCU is in run mode again. If the clock monitor is enabled (CME = 1) the MCU is able to leave pseudo-stop mode when loss of oscillator/external clock is detected by a clock monitor fail. If the SCME bit is not asserted the CRG generates a clock monitor fail reset (CMRESET). The CRG's behavior for CMRESET is the same compared to external reset, but another reset vector is fetched after completion of the reset sequence. If the SCME bit is asserted the CRG generates a SCM interrupt if enabled (SCMIE=1). After generating the interrupt the CRG enters self-clock mode and starts the clock quality checker (see Section 9.4.4, "Clock Quality Checker"). Then the MCU continues with normal operation. If the SCM interrupt is blocked by SCMIE = 0, the SCMIF flag will be asserted but the CRG will not wake-up from pseudo-stop mode. If any other interrupt source (e.g. RTI) triggers exit from pseudo-stop mode the MCU immediately continues with normal operation. Because the PLL has been powered-down during stop mode the PLLSEL bit is cleared and the MCU runs on OSCCLK after leaving stop mode. The software must set the PLLSEL bit again, in order to switch system and core clocks to the PLLCLK. Table 9-11 summarizes the outcome of a clock loss while in pseudo-stop mode.
MC3S12RG128 Data Sheet, Rev. 1.05 270 Freescale Semiconductor
Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
Table 9-11. Outcome of Clock Loss in Pseudo-Stop Mode
CME 0 1 1 SCME X 0 1 SCMIE X X 0 Clock failure --> No action, clock loss not detected. Clock failure --> CRG performs Clock Monitor Reset immediately Clock Monitor failure --> Scenario 1: OSCCLK recovers prior to exiting Pseudo-Stop Mode. - MCU remains in Pseudo-Stop Mode, - VREG enabled, - PLL enabled, - SCM activated, - Start Clock Quality Check, - Set SCMIF interrupt flag. Some time later OSCCLK recovers. - CM no longer indicates a failure, - 4096 OSCCLK cycles later Clock Quality Check indicates clock o.k., - SCM deactivated, - PLL disabled, - VREG disabled. - MCU remains in Pseudo-Stop Mode. Some time later either a wakeup interrupt occurs (no SCM interrupt) - Exit Pseudo-Stop Mode using OSCCLK as system clock (SYSCLK), - Continue normal operation. or an External Reset is applied. - Exit Pseudo-Stop Mode using OSCCLK as system clock, - Start reset sequence. Scenario 2: OSCCLK does not recover prior to exiting Pseudo-Stop Mode. - MCU remains in Pseudo-Stop Mode, - VREG enabled, - PLL enabled, - SCM activated, - Start Clock Quality Check, - Set SCMIF interrupt flag, - Keep performing Clock Quality Checks (could continue infinitely) while in Pseudo-Stop Mode. Some time later either a wakeup interrupt occurs (no SCM interrupt) - Exit Pseudo-Stop Mode in SCM using PLL clock (fSCM) as system clock - Continue to perform additional Clock Quality Checks until OSCCLK is o.k. again. or an External RESET is applied. - Exit Pseudo-Stop Mode in SCM using PLL clock (fSCM) as system clock - Start reset sequence, - Continue to perform additional Clock Quality Checks until OSCCLK is o.k.again. CRG Actions
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 271
Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
Table 9-11. Outcome of Clock Loss in Pseudo-Stop Mode (continued)
CME 1 SCME 1 SCMIE 1 Clock failure --> - VREG enabled, - PLL enabled, - SCM activated, - Start Clock Quality Check, - SCMIF set. SCMIF generates Self-Clock Mode wakeup interrupt. - Exit Pseudo-Stop Mode in SCM using PLL clock (fSCM) as system clock, - Continue to perform a additional Clock Quality Checks until OSCCLK is o.k. again. CRG Actions
9.4.10.2
Wake-up from Full Stop (PSTP=0)
The MCU requires an external interrupt or an external reset in order to wake-up from stop mode. If the MCU gets an external reset during full stop mode active, the CRG asynchronously restores all configuration bits in the register space to its default settings and will perform a maximum of 50 clock check_windows (see Section 9.4.4, "Clock Quality Checker"). After completing the clock quality check the CRG starts the reset generator. After completing the reset sequence processing begins by fetching the normal reset vector. Full stop mode is exited and the MCU is in run mode again. If the MCU is woken-up by an interrupt, the CRG will also perform a maximum of 50 clock check_windows (see Section 9.4.4, "Clock Quality Checker"). If the clock quality check is successful, the CRG will release all system and core clocks and will continue with normal operation. If all clock checks within the timeout-window are failing, the CRG will switch to self-clock mode or generate a clock monitor reset (CMRESET) depending on the setting of the SCME bit. Because the PLL has been powered-down during stop mode the PLLSEL bit is cleared and the MCU runs on OSCCLK after leaving stop mode. The software must manually set the PLLSEL bit again, in order to switch system and core clocks to the PLLCLK. NOTE In full stop mode, the clock monitor is disabled and any loss of clock will not be detected.
9.5
Resets
This section describes how to reset the CRG and how the CRG itself controls the reset of the MCU. It explains all special reset requirements. Because the reset generator for the MCU is part of the CRG, this section also describes all automatic actions that occur during or as a result of individual reset conditions. The reset values of registers and signals are provided in Section 9.3, "Memory Map and Register
MC3S12RG128 Data Sheet, Rev. 1.05 272 Freescale Semiconductor
Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
Definition." All reset sources are listed in Table 9-12. Refer to the device overview chapter for related vector addresses and priorities.
Table 9-12. Reset Summary
Reset Source Power-on Reset Low Voltage Reset External Reset Clock Monitor Reset COP Watchdog Reset Local Enable None None None PLLCTL (CME=1, SCME=0) COPCTL (CR[2:0] nonzero)
The reset sequence is initiated by any of the following events: * * * * * Low level is detected at the RESET pin (external reset). Power on is detected. Low voltage is detected. COP watchdog times out. Clock monitor failure is detected and self-clock mode was disabled (SCME = 0).
Upon detection of any reset event, an internal circuit drives the RESET pin low for 128 SYSCLK cycles (see Figure 9-25). Because entry into reset is asynchronous it does not require a running SYSCLK. However, the internal reset circuit of the CRG cannot sequence out of current reset condition without a running SYSCLK. The number of 128 SYSCLK cycles might be increased by n = 3 to 6 additional SYSCLK cycles depending on the internal synchronization latency. After 128+n SYSCLK cycles the RESET pin is released. The reset generator of the CRG waits for additional 64 SYSCLK cycles and then samples the RESET pin to determine the originating source. Table 9-13 shows which vector will be fetched.
Table 9-13. Reset Vector Selection
Sampled RESET Pin (64 Cycles After Release) 1 1 1 0 Clock Monitor Reset Pending 0 1 0 X COP Reset Pending 0 X 1 X Vector Fetch POR / LVR / External Reset Clock Monitor Reset COP Reset POR / LVR / External Reset with rise of RESET pin
NOTE External circuitry connected to the RESET pin should not include a large capacitance that would interfere with the ability of this signal to rise to a valid logic 1 within 64 SYSCLK cycles after the low drive is released.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 273
Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
The internal reset of the MCU remains asserted while the reset generator completes the 192 SYSCLK long reset sequence. The reset generator circuitry always makes sure the internal reset is deasserted synchronously after completion of the 192 SYSCLK cycles. In case the RESET pin is externally driven low for more than these 192 SYSCLK cycles (external reset), the internal reset remains asserted too.
RESET )( )(
RESET pin released
CRG drives RESET pin low
SYSCLK
) ( 128+n cycles
possibly SYSCLK not running with n being min 3 / max 6 cycles depending on internal synchronization delay
) ( 64 cycles
) (
possibly RESET driven low externally
Figure 9-25. RESET Timing
9.5.1
* * *
Clock Monitor Reset
Clock monitor is enabled (CME=1) Loss of clock is detected Self-clock mode is disabled (SCME=0)
The CRG generates a clock monitor reset in case all of the following conditions are true:
The reset event asynchronously forces the configuration registers to their default settings (see Section 9.3, "Memory Map and Register Definition"). In detail the CME and the SCME are reset to logical `1' (which doesn't change the state of the CME bit, because it has already been set). As a consequence, the CRG immediately enters self-clock mode and starts its internal reset sequence. In parallel the clock quality check starts. As soon as clock quality check indicates a valid oscillator clock the CRG switches to OSCCLK and leaves self-clock mode. Because the clock quality checker is running in parallel to the reset generator, the CRG may leave self-clock mode while completing the internal reset sequence. When the reset sequence is finished the CRG checks the internally latched state of the clock monitor fail circuit. If a clock monitor fail is indicated processing begins by fetching the clock monitor reset vector.
9.5.2
Computer Operating Properly Watchdog (COP) Reset
When COP is enabled, the CRG expects sequential write of 0x0055 and 0x00AA (in this order) to the ARMCOP register during the selected time-out period. As soon as this is done, the COP time-out period restarts. If the program fails to do this the CRG will generate a reset. Also, if any value other than 0x0055 or 0x00AA is written, the CRG immediately generates a reset. In case windowed COP operation is enabled
MC3S12RG128 Data Sheet, Rev. 1.05 274 Freescale Semiconductor
Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
writes (0x0055 or 0x00AA) to the ARMCOP register must occur in the last 25% of the selected time-out period. A premature write the CRG will immediately generate a reset. As soon as the reset sequence is completed the reset generator checks the reset condition. If no clock monitor failure is indicated and the latched state of the COP timeout is true, processing begins by fetching the COP vector.
9.5.3
Power-On Reset, Low Voltage Reset
The on-chip voltage regulator detects when VDD to the MCU has reached a certain level and asserts power-on reset or low voltage reset or both. As soon as a power-on reset or low voltage reset is triggered the CRG performs a quality check on the incoming clock signal. As soon as clock quality check indicates a valid oscillator clock signal the reset sequence starts using the oscillator clock. If after 50 check windows the clock quality check indicated a non-valid oscillator clock the reset sequence starts using self-clock mode. Figure 9-26 and Figure 9-27 show the power-up sequence for cases when the RESET pin is tied to VDD and when the RESET pin is held low.
RESET
Clock Quality Check (no Self-Clock Mode) )(
Internal POR )( 128 SYSCLK Internal RESET )( 64 SYSCLK
Figure 9-26. RESET Pin Tied to VDD (by a Pull-Up Resistor)
RESET
Clock Quality Check (no Self-Clock Mode) )(
Internal POR )( 128 SYSCLK Internal RESET )( 64 SYSCLK
Figure 9-27. RESET Pin Held Low Externally
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 275
Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
9.6
Interrupts
The interrupts/reset vectors requested by the CRG are listed in Table 9-14. Refer to the device overview chapter for related vector addresses and priorities.
Table 9-14. CRG Interrupt Vectors
Interrupt Source Real-time interrupt LOCK interrupt SCM interrupt CCR Mask I bit I bit I bit Local Enable CRGINT (RTIE) CRGINT (LOCKIE) CRGINT (SCMIE)
9.6.1
Real-Time Interrupt
The CRG generates a real-time interrupt when the selected interrupt time period elapses. RTI interrupts are locally disabled by setting the RTIE bit to 0. The real-time interrupt flag (RTIF) is set to 1 when a timeout occurs, and is cleared to 0 by writing a 1 to the RTIF bit. The RTI continues to run during pseudo-stop mode if the PRE bit is set to 1. This feature can be used for periodic wakeup from pseudo-stop if the RTI interrupt is enabled.
9.6.2
PLL Lock Interrupt
The CRG generates a PLL lock interrupt when the LOCK condition of the PLL has changed, either from a locked state to an unlocked state or vice versa. Lock interrupts are locally disabled by setting the LOCKIE bit to 0. The PLL Lock interrupt flag (LOCKIF) is set to1 when the LOCK condition has changed, and is cleared to 0 by writing a 1 to the LOCKIF bit.
9.6.3
Self-Clock Mode Interrupt
The CRG generates a self-clock mode interrupt when the SCM condition of the system has changed, either entered or exited self-clock mode. SCM conditions can only change if the self-clock mode enable bit (SCME) is set to 1. SCM conditions are caused by a failing clock quality check after power-on reset (POR) or low voltage reset (LVR) or recovery from full stop mode (PSTP = 0) or clock monitor failure. For details on the clock quality check refer to Section 9.4.4, "Clock Quality Checker." If the clock monitor is enabled (CME = 1) a loss of external clock will also cause a SCM condition (SCME = 1). SCM interrupts are locally disabled by setting the SCMIE bit to 0. The SCM interrupt flag (SCMIF) is set to 1 when the SCM condition has changed, and is cleared to 0 by writing a 1 to the SCMIF bit.
MC3S12RG128 Data Sheet, Rev. 1.05 276 Freescale Semiconductor
Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
10.1 Introduction
The HCS12 Enhanced Capture Timer module has the features of the HCS12 Standard Timer module enhanced by additional features in order to enlarge the field of applications, in particular for automotive ABS applications. This design specification describes the standard timer as well as the additional features. The basic timer consists of a 16-bit, software-programmable counter driven by a prescaler. This timer can be used for many purposes, including input waveform measurements while simultaneously generating an output waveform. Pulse widths can vary from microseconds to many seconds. A full access for the counter registers or the input capture/output compare registers should take place in one clock cycle. Accessing high byte and low byte separately for all of these registers may not yield the same result as accessing them in one word.
10.1.1
* * * *
Features
16-bit Buffer Register for four Input Capture (IC) channels. Four 8-bit Pulse Accumulators with 8-bit buffer registers associated with the four buffered IC channels. Configurable also as two 16-bit Pulse Accumulators. 16-bit Modulus Down-Counter with 4-bit Prescaler. Four user selectable Delay Counters for input noise immunity increase.
10.1.2
STOP: FREEZE: WAIT:
Modes of Operation
Timer and modulus counter are off since clocks are stopped. Timer and modulus counter keep on running, unless TSFRZ in TSCR (0x0006) is set to one. Counters keep on running, unless TSWAI in TSCR (0x0006) is set to one.
NORMAL: Timer and modulus counter keep on running, unless TEN in TSCR (0x0006) respectively MCEN in MCCTL (0x0026) are cleared.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 277
Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
10.1.3
Block Diagram
CHANNEL 0 INPUT CAPTURE OUTPUT COMPARE 16-BIT COUNTER CHANNEL 1 INPUT CAPTURE IOC0
BUS CLOCK
PRESCALER
MODULUS COUNTER INTERRUPT
16-BIT MODULUS COUNTER
OUTPUT COMPARE CHANNEL 2 INPUT CAPTURE
IOC1
TIMER OVERFLOW INTERRUPT TIMER CHANNEL 0 INTERRUPT
OUTPUT COMPARE CHANNEL 3 INPUT CAPTURE OUTPUT COMPARE REGISTERS CHANNEL 4 INPUT CAPTURE OUTPUT COMPARE CHANNEL 5 INPUT CAPTURE OUTPUT COMPARE
IOC2
IOC3
IOC4
IOC5
TIMER CHANNEL 7 INTERRUPT PA OVERFLOW INTERRUPT PA INPUT INTERRUPT PB OVERFLOW INTERRUPT
CHANNEL 6 16-BIT PULSE ACCUMULATOR A INPUT CAPTURE OUTPUT COMPARE CHANNEL 7 16-BIT PULSE ACCUMULATOR B INPUT CAPTURE OUTPUT COMPARE IOC7 IOC6
Figure 10-1. Timer Block Diagram
MC3S12RG128 Data Sheet, Rev. 1.05 278 Freescale Semiconductor
Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
10.2
Signal Description
The ECT16B8C module has a total eight external pins.
10.2.1
IOC7 -- Input Capture and Output Compare Channel 7
This pin serves as input capture or output compare for channel 7.
10.2.2
IOC6 -- Input Capture and Output Compare Channel 6
This pin serves as input capture or output compare for channel 6.
10.2.3
IOC5 -- Input Capture and Output Compare Channel 5
This pin serves as input capture or output compare for channel 7.
10.2.4
IOC4 -- Input Capture and Output Compare Channel 4
This pin serves as input capture or output compare for channel 4.
10.2.5
IOC3 -- Input Capture and Output Compare Channel 3
This pin serves as input capture or output compare for channel 3.
10.2.6
IOC2 -- Input Capture and Output Compare Channel 2
This pin serves as input capture or output compare for channel 2.
10.2.7
IOC1 -- Input Capture and Output Compare Channel 1
This pin serves as input capture or output compare for channel 1.
10.2.8
IOC0 -- Input Capture and Output Compare Channel 0
NOTE For the description of interrupts see Section 10.6, "Interrupts".
This pin serves as input capture or output compare for channel 0.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 279
Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
10.3
Memory Map and Registers
This section provides a detailed description of all memory and registers.
10.3.1
Module Memory Map
A register summary for the ECT module is given below in Figure 10-2. The Address listed for each register is the address offset. The total address for each register is the sum of the base address for the ECT module and the address offset for each register.
Address 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C 0x000D 0x000E 0x000F 0x0010 Name TIOS CFORC OC7M OC7D TCNT TCNT TSCR1 TTOV TCTL1 TCTL2 TCTL3 TCTL4 TIE TSCR2 TFLG1 TFLG2 TC0 Bit 7 R IOS7 W R 0 W FOC7 R OC7M7 W R OC7D7 W R TCNT15 W R TCNT7 W R TEN W R TOV7 W R OM7 W R OM3 W R EDG7B W R EDG3B W R C7I W R TOI W R C7F W R TOF W R TC015 W 6 IOS6 0 FOC6 OC7M6 OC7D6 TCNT14 TCNT6 TSWAI TOV6 OL7 OL3 EDG7A EDG3A C6I 0 5 IOS5 0 FOC5 OC7M5 OC7D5 TCNT13 TCNT5 TSFRZ TOV5 OM6 OM2 EDG6B EDG2B C5I 0 4 IOS4 0 FOC4 OC7M4 OC7D4 TCNT12 TCNT4 TFFCA TOV4 OL6 OL2 EDG6A EDG2A C4I 0 3 IOS3 0 FOC3 OC7M3 OC7D3 TCNT11 TCNT3 0 2 IOS2 0 FOC2 OC7M2 OC7D2 TCNT10 TCNT2 0 1 IOS1 0 FOC1 OC7M1 OC7D1 TCNT9 TCNT1 0 Bit 0 IOS0 0 FOC0 OC7M0 OC7D0 TCNT8 TCNT0 0
TOV3 OM5 OM1 EDG5B EDG1B C3I TCRE C3F 0
TOV2 OL5 OL1 EDG5A EDG1A C2I PR2 C2F 0
TOV1 OM4 OM0 EDG4B EDG0B C1I PR1 C1F 0
TOV0 OL4 OL0 EDG4A EDG0A C0I PR0 C0F 0
C6F 0
C5F 0
C4F 0
TC014
TC013
TC012
TC011
TC010
TC09
TC08
= Unimplemented or Reserved
Figure 10-2. ECT Register Summary (Sheet 1 of 4)
MC3S12RG128 Data Sheet, Rev. 1.05 280 Freescale Semiconductor
Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
Address 0x0011 0x0012 0x0013 0x0014 0x0015 0x0016 0x0017 0x0018 0x0019 0x001A 0x001B 0x001C 0x001D 0x001E 0x001F 0x0020 0x0021 0x0022 0x0023 0x0024 0x0025 0x0026
Name TCO TC1 TC1 TC2 TC2 TC3 TC3 TC4 TC4 TC5 TC5 TC6 TC6 TC7 TC7 PACTL PAFLG PACN3 PACN2 PACN1 PACN0 MCCTL R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W
Bit 7 TC07 TC115 TC17 TC215 TC27 TC315 TC37 TC415 TC47 TC515 TC57 TC615 TC67 TC715 TC77 0 0 PACNT7 (15) PACNT7 PACNT7 (15) PACNT7 MCZI
6 TC06 TC114 TC16 TC214 TC26 TC314 TC36 TC414 TC46 TC514 TC56 TC614 TC66 TC714 TC76 PAEN 0 PACNT6 (14) PACNT6 PACNT6 (14) PACNT6 MODMC
5 TC05 TC113 TC15 TC213 TC25 TC313 TC35 TC413 TC45 TC513 TC55 TC613 TC65 TC713 TC75 PAMOD 0 PACNT5 (13) PACNT5 PACNT5 (13) PACNT5 RDMCL
4 TC04 TC112 TC14 TC212 TC24 TC312 TC34 TC412 TC44 TC512 TC54 TC612 TC64 TC712 TC74 PEDGE 0 PACNT4 (12) PACNT4 PACNT4 (12) PACNT4 0 ICLAT
3 TC03 TC111 TC13 TC211 TC23 TC311 TC33 TC411 TC43 TC511 TC53 TC611 TC63 TC711 TC73 CLK1 0 PACNT3 (11) PACNT3 PACNT3( 11) PACNT3 0 FLMC
2 TC02 TC110 TC12 TC210 TC22 TC310 TC32 TC410 TC42 TC510 TC52 TC610 TC62 TC710 TC72 CLK0 0 PACNT2 (10) PACNT2 PACNT2 (10) PACNT2 MCEN
1 TC01 TC19 TC11 TC29 TC21 TC39 TC31 TC49 TC41 TC59 TC51 TC69 TC61 TC79 TC71 PAOVI PAOVF PACNT1 (9) PACNT1 PACNT1 (9) PACNT1 MCPR1
Bit 0 TC00 TC18 TC10 TC28 TC20 TC38 TC30 TC48 TC40 TC58 TC50 TC68 TC60 TC78 TC70 PAI PAIF PACNT0 (8) PACNT0 PACNT0 (8) PACNT0 MCPR0
= Unimplemented or Reserved
Figure 10-2. ECT Register Summary (Sheet 2 of 4)
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 281
Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
Address 0x0027 0x0028 0x0029 0x002A 0x002B 0x002C 0x002D 0x002E 0x002F 0x0030 0x0031 0x0032 0x0033 0x0034 0x0035 0x0036 0x0037 0x0038 0x0039 0x003A 0x003B 0x003C
Name MCFLG ICPAR DLYCT ICOVW ICSYS Reserved TIMTST Reserved Reserved PBCTL PAFLG PA3H PA2H PA1H PA0H MCCNT MCCNT TC0H TC0H TC1H TC1H TC2H
Bit 7 R MCZF W R 0 W R 0 W R NOVW7 W R SH37 W R W R W R W R W R 0 W R 0 W R PA3H7 W R PA2H7 W R PA1H7 W R PA0H7 W R MCCNT 15 W R MCCNT7 W R TC15 W R TC7 W R TC15 W R TC7 W R TC15 W
6 0 0 0
5 0 0 0
4 0 0 0
3 POLF3
2 POLF2
1 POLF1
Bit 0 POLF0
PA3EN 0
PA2EN 0
PA1EN DLY1 NOVW1 BUFEN
PA0EN DLY0 NOVW0 LATQ
NOVW6 SH26
NOVW5 SH15
NOVW4 SH04
NOVW3 TFMOD
NOVW2 PACMX
Timer Test Register
PBEN 0 PA3H6 PA2H6 PA1H6 PA0H6 MCCNT 14 MCCNT6 TC14 TC6 TC14 TC6 TC14
0 0 PA3H5 PA2H5 PA1H5 PA0H5 MCCNT 13 MCCNT5 TC13 TC5 TC13 TC5 TC13
0 0 PA3H4 PA2H4 PA1H4 PA0H4 MCCNT 12 MCCNT4 TC12 TC4 TC12 TC4 TC12
0 0 PA3H3 PA2H3 PA1H3 PA0H3 MCCNT 11 MCCNT3 TC11 TC3 TC11 TC3 TC11
0 0 PA3H2 PA2H2 PA1H2 PA0H2 MCCNT 10 MCCNT2 TC10 TC2 TC10 TC2 TC10
PBOVI PBOVF PA3H1 PA2H1 PA1H1 PA0H1
0 0 PA3H0 PA2H0 PA1H0 PA0H0
MCCNT9 MCCNT1 TC9 TC1 TC9 TC1 TC9
MCCNT8 MCCNT0 TC8 TC0 TC8 TC0 TC8
= Unimplemented or Reserved
Figure 10-2. ECT Register Summary (Sheet 3 of 4)
MC3S12RG128 Data Sheet, Rev. 1.05 282 Freescale Semiconductor
Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
Address 0x003D 0x003E 0x003F
Name TC2H TC3H TC3H R W R W R W
Bit 7 TC7 TC15 TC7
6 TC6 TC14 TC6
5 TC5 TC13 TC5
4 TC4 TC12 TC4
3 TC3 TC11 TC3
2 TC2 TC10 TC2
1 TC1 TC9 TC1
Bit 0 TC0 TC8 TC0
= Unimplemented or Reserved
Figure 10-2. ECT Register Summary (Sheet 4 of 4)
10.3.2
Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order.
10.3.2.1
Timer Input Capture/Output Compare Select Register (TIOS)
Module Base + 0x0000
7 6 5 4 3 2 1 0
R IOS7 W Reset 0 0 0 0 0 0 0 0 IOS6 IOS5 IOS4 IOS3 IOS2 IOS1 IOS0
Figure 10-3. Timer Input Capture/Output Compare Register (TIOS)
Read or write anytime.
Table 10-1. TIOS Field Descriptions
Field 7-0 IOS[7:0] Description Input Capture or Output Compare Channel Configuration Bits 0 The corresponding channel acts as an input capture 1 The corresponding channel acts as an output compare.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 283
Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
10.3.2.2
Timer Compare Force Register (CFORC)
Module Base + 0x0001
7 6 5 4 3 2 1 0
R W Reset
0 FOC7 0
0 FOC6 0
0 FOC5 0
0 FOC4 0
0 FOC3 0
0 FOC2 0
0 FOC1 0
0 FOC0 0
Figure 10-4. Timer Compare Force Register (CFORC)
Read anytime but will always return 0x0000 (1 state is transient). Write anytime.
Table 10-2. CFORC Field Descriptions
Field 7-0 FOC[7:0] Description Force Output Compare Action for Channel 7-0 -- A write to this register with the corresponding data bit(s) set causes the action which is programmed for output compare "n" to occur immediately. The action taken is the same as if a successful comparison had just taken place with the TCn register except the interrupt flag does not get set. Note: A successful channel 7 output compare overrides any channel 6:0 compares.If forced output compare on any channel occurs at the same time as the successful output compare then forced output compare action will take precedence and interrupt flag won't get set.
10.3.2.3
Output Compare 7 Mask Register (OC7M)
Module Base + 0x0002
7 6 5 4 3 2 1 0
R OC7M7 W Reset 0 0 0 0 0 0 0 0 OC7M6 OC7M5 OC7M4 OC7M3 OC7M2 OC7M1 OC7M0
Figure 10-5. Output Compare 7 Mask Register (OC7M)
Read or write anytime. Setting the OC7Mn (n ranges from 0 to 6) bit of OC7M register configures the corresponding port to be an output port when the IOS7 bit and the corresponding IOSn (n ranges from 0 to 6) bit of TIOS register are set to be an output compare. Refer to the note on Section 10.4.1.4, "Channel Configurations" for more insight. NOTE A successful channel 7 output compare overrides any channel 6:0 compares. For each OC7M bit that is set, the output compare action reflects the corresponding OC7D bit.
MC3S12RG128 Data Sheet, Rev. 1.05 284 Freescale Semiconductor
Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
10.3.2.4
Output Compare 7 Data Register (OC7D)
Module Base + 0x0003
7 6 5 4 3 2 1 0
R OC7D7 W Reset 0 0 0 0 0 0 0 0 OC7D6 OC7D5 OC7D4 OC7D3 OC7D2 OC7D1 OC7D0
Figure 10-6. Output Compare 7 Data Register (OC7D)
Read or write anytime. A channel 7 output compare can cause bits in the output compare 7 data register to transfer to the timer port data register depending on the output compare 7 mask register.
10.3.2.5
Timer Count Register (TCNT)
Module Base + 0x0004-0x0005
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset
tcnt 15 0
tcnt 14 0
tcnt 13 0
tcnt 12 0
tcnt 11 0
tcnt 10 0
tcnt 9 0
tcnt 8 0
tcnt 7 0
tcnt 6 0
tcnt 5 0
tcnt 4 0
tcnt 3 0
tcnt 2 0
tcnt 1 0
tcnt 0 0
= Unimplemented or Reserved
Figure 10-7. Timer Count Register (TCNT)
The 16-bit main timer is an up counter. A full access for the counter register should take place in one clock cycle. A separate read (any mode)/ write (test mode) for high byte and low byte will give a different result than accessing them as a word. Read anytime. Write has no meaning or effect in the normal mode; only writable in special modes (test_mode = 1). The period of the first count after a write to the TCNT registers may be a different size because the write is not synchronized with the prescaler clock.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 285
Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
10.3.2.6
Timer System Control Register 1 (TSCR1)
Module Base + 0x0006
7 6 5 4 3 2 1 0
R TEN W Reset 0 0 0 0 TSWAI TSFRZ TFFCA
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 10-8. Timer System Control Register 1 (TSCR1)
Read or write anytime.
Table 10-3. TSCR1 Field Descriptions
Field 7 TEN Description Timer Enable 0 Disables the main timer, including the counter. Can be used for reducing power consumption. 1 Allows the timer to function normally. Note: If for any reason the timer is not active, there is no /64 clock for the pulse accumulator since the /64 is generated by the timer prescaler. Timer Module Stops While in Wait 0 Allows the timer module to continue running during wait. 1 Disables the timer module when the MCU is in the wait mode. Timer interrupts cannot be used to get the MCU out of wait. Note: TSWAI also affects pulse accumulators and modulus down counters. Timer and Modulus Counter Stop While in Freeze Mode 0 Allows the timer and modulus counter to continue running while in freeze mode. 1 Disables the timer and modulus counter whenever the MCU is in freeze mode. This is useful for emulation. Note: TSFRZ does not stop the pulse accumulator. Timer Fast Flag Clear All 0 Allows the timer flag clearing to function normally. 1 For TFLG1(0x000E), a read from an input capture or a write to the output compare channel (0x0010-0x001F) causes the corresponding channel flag, CnF, to be cleared. For TFLG2 (0x000F), any access to the TCNT register (0x0004, 0x0005) clears the TOF flag. Any access to the PACN3 and PACN2 registers (0x0022, 0x0023) clears the PAOVF and PAIF flags in the PAFLG register (0x0021). Any access to the PACN1 and PACN0 registers (0x0024, 0x0025) clears the PBOVF flag in the PBFLG register (0x0031). This has the advantage of eliminating software overhead in a separate clear sequence. Extra care is required to avoid accidental flag clearing due to unintended accesses.
6 TSWAI
5 TSFRZ
4 TFFCA
MC3S12RG128 Data Sheet, Rev. 1.05 286 Freescale Semiconductor
Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
10.3.2.7
Timer Toggle On Overflow Register 1 (TTOV)
Module Base + 0x0007
7 6 5 4 3 2 1 0
R TOV7 W Reset 0 0 0 0 0 0 0 0 TOV6 TOV5 TOV4 TOV3 TOV2 TOV1 TOV0
Figure 10-9. Timer Toggle On Overflow Register 1 (TTOV)
Read or write anytime.
Table 10-4. TTOV Field Descriptions
Field 7-0 TOV[7:0] Description Toggle On Overflow Bits -- TOVn toggles output compare pin on overflow. This feature only takes effect when in output compare mode. When set, it takes precedence over forced output compare but not channel 7 override events. 0 Toggle output compare pin on overflow feature disabled 1 Toggle output compare pin on overflow feature enabled
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 287
Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
10.3.2.8
Timer Control Register 1/Timer Control Register 2 (TCTL1/TCTL2)
Module Base + 0x0008
7 6 5 4 3 2 1 0
R OM7 W Reset 0 0 0 0 0 0 0 0 OL7 OM6 OL6 OM5 OL5 OM4 OL4
Module Base + 0x0009
7 6 5 4 3 2 1 0
R OM3 W Reset 0 0 0 0 0 0 0 0 OL3 OM2 OL2 OM1 OL1 OM0 OL0
Figure 10-10. Timer Control Register 1/Timer Control Register 2 (TCTL1/TCTL2))
Read or write anytime.
Table 10-5. TCTL1/TCTL2 Field Descriptions
Field 7-0 OM[7:0] OL[7:0] Description OMn -- Output Mode OLn -- Output Level These eight pairs of control bits are encoded to specify the output action to be taken as a result of a successful OCn(n varies from 0 to 7) compare. When either OMn or OLn is one, the port associated with OCn becomes an output tied to OCn when the corresponding IOSn bit of TIOS register is set and TEN bit of TSCR1 register is set. Refer to the note on Section 10.4.1.4, "Channel Configurations" for more insight. See Table 10-6. Note: To enable output action by OMn and OLn bits on timer port, the corresponding bit in OC7M should be cleared. To operate the 16-bit pulse accumulators A and B (PACA and PACB) independently of input capture or output compare 7 and 0 respectively the user must set the corresponding bits IOSn = 1, OMn = 0 and OLn = 0. OC7M7 or OC7M0 in the OC7M register must also be cleared.
.
Table 10-6. Compare Result Output Action
OMn 0 0 1 1 OLn 0 1 0 1 Action Timer disconnected from output pin logic Toggle OCn output line Clear OCn output line to zero Set OCn output line to one
MC3S12RG128 Data Sheet, Rev. 1.05 288 Freescale Semiconductor
Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
10.3.2.9
Timer Control Register 3/Timer Control Register 4 (TCTL3/TCTL4)
Module Base + 0x000A
7 6 5 4 3 2 1 0
R EDG7B W Reset 0 0 0 0 0 0 0 0 EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A
Module Base + 0x000B
7 6 5 4 3 2 1 0
R EDG3B W Reset 0 0 0 0 0 0 0 0 EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A
Figure 10-11. Timer Control Register 3/Timer Control Register 4 (TCTL3/TCTL4)
Read or write anytime.
Table 10-7. TCTL3/TCTL4 Field Descriptions
Field 7-0 EDG[7:0]B EDG[7:0]A Description Input Capture Edge Control -- These eight pairs of control bits configure the input capture edge detector circuits. The four pairs of control bits of TCTL4 also configure the 8 bit pulse accumulators PAC0-PAC3. For 16-bit pulse accumulator PACB, EDGE0B, and EDGE0A, control bits of TCTL4 will decide the active edge. See Table 10-8.
.
Table 10-8. Edge Detector Circuit Configuration
EDGnB 0 0 1 1 EDGnA 0 1 0 1 Configuration Capture disabled Capture on rising edges only Capture on falling edges only Capture on any edge (rising or falling)
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 289
Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
10.3.2.10 Timer Interrupt Enable Register (TIE)
Module Base + 0x000C
7 6 5 4 3 2 1 0
R C7I W Reset 0 0 0 0 0 0 0 0 C6I C5I C4I C3I C2I C1I C0I
Figure 10-12. Timer Interrupt Enable Register (TIE)
Read or write anytime.
Table 10-9. TIE Field Descriptions
Field 7-0 C[7:0]I Description Input Capture/Output Compare "n" Interrupt Enable -- The bits in TIE correspond bit-for-bit with the bits in the TFLG1 status register. If cleared, the corresponding flag is disabled from causing a hardware interrupt. If set, the corresponding flag is enabled to cause a interrupt.
MC3S12RG128 Data Sheet, Rev. 1.05 290 Freescale Semiconductor
Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
10.3.2.11 Timer System Control Register 2 (TSCR2)
Module Base + 0x000D
7 6 5 4 3 2 1 0
R TOI W Reset 0
0
0
0 TCRE PR2 0 PR1 0 PR0 0
0
0
0
0
= Unimplemented or Reserved
Figure 10-13. Timer System Control Register 2 (TSCR2)
Read or write anytime.
Table 10-10. TSCR2 Field Descriptions
Field 7 TOI 3 TCRE Description Timer Overflow Interrupt Enable 0 Interrupt inhibited 1 Hardware interrupt requested when TOF flag set Timer Counter Reset Enable -- This bit allows the timer counter to be reset by a successful output compare 7 event. This mode of operation is similar to an up-counting modulus counter. 0 Counter reset inhibited and counter free runs 1 Counter reset by a successful output compare 7 Note: If TC7 = 0x0000 and TCRE = 1, TCNT will stay at 0x0000 continuously. If TC7 = 0xFFFF and TCRE = 1, TOF will never be set when TCNT is reset from 0xFFFF to 0x0000. Timer Prescaler Select -- These three bits specify the number of /2 stages that are to be inserted between the bus clock and the main timer counter. See Table 10-11. Note: The newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter stages equal zero.
2-0 PR[2:0]
Table 10-11. Prescaler Selection
PR2 0 0 0 0 1 1 1 1 PR1 0 0 1 1 0 0 1 1 PR0 0 1 0 1 0 1 0 1 Prescale Factor 1 2 4 8 16 32 64 128
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 291
Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
10.3.2.12 Main Timer Interrupt Flag 1 (TFLG1)
Module Base + 0x000E
7 6 5 4 3 2 1 0
R W Reset
C7F 0
C6F 0
C5F 0
C4F 0
C3F 0
C2F 0
C1F 0
C0F 0
Figure 10-14. Main Timer Interrupt Flag 1 (TFLG1)
TFLG1 indicates when interrupt conditions have occurred. To clear a bit in the flag register, write a one to the bit. Use of the TFMOD bit in the ICSYS register (0x002B) in conjunction with the use of the ICOVW register (0x002A) allows a timer interrupt to be generated after capturing two values in the capture and holding registers instead of generating an interrupt for every capture. Read anytime. Write used in the clearing mechanism (set bits cause corresponding bits to be cleared). Writing a zero will not affect current status of the bit. When TFFCA bit in TSCR register is set, a read from an input capture or a write into an output compare channel (0x0010-0x001F) will cause the corresponding channel flag CnF to be cleared.
Table 10-12. TFLG1 Field Descriptions
Field 7-0 C[7:0]F Description Input Capture/Output Compare Channel "n" Flag -- C0F can also be set by 16-bit Pulse Accumulator B (PACB). C3F-C0F can also be set by 8 - bit pulse accumulators PAC3-PAC0.
10.3.2.13 Main Timer Interrupt Flag 2 (TFLG2)
Module Base + 0x000F
7 6 5 4 3 2 1 0
R W Reset
TOF 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
= Unimplemented or Reserved
Figure 10-15. Main Timer Interrupt Flag 2 (TFLG2)
TFLG2 indicates when interrupt conditions have occurred. To clear a bit in the flag register, write the bit to one. Read anytime. Write used in clearing mechanism (set bits cause corresponding bits to be cleared). Any access to TCNT will clear TFLG2 register if the TFFCA bit in TSCR register is set.
Table 10-13. TFLG2 Field Descriptions
Field 7 TOF Description Timer Overflow Flag -- Set when 16-bit free-running timer overflows from 0xFFFF to 0x0000. This bit is cleared automatically by a write to the TFLG2 register with bit 7 set. See also TCRE control bit explanation found in Section 10.3.2.11, "Timer System Control Register 2 (TSCR2)".
MC3S12RG128 Data Sheet, Rev. 1.05 292 Freescale Semiconductor
Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
10.3.2.14 Timer Input Capture/Output Compare Registers (TC0-TC7)
Module Base + 0x0010-0x0011
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset
tc0 15 0
tc0 14 0
tc0 13 0
tc0 12 0
tc0 11 0
tc0 10 0
tc0 9 0
tc0 8 0
tc0 7 0
tc0 6 0
tc0 5 0
tc0 4 0
tc0 3 0
tc0 2 0
tc0 1 0
tc0 0 0
Module Base + 0x0012-0x0013
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset
tc1 15 0
tc1 14 0
tc1 13 0
tc1 12 0
tc1 11 0
tc1 10 0
tc1 9 0
tc1 8 0
tc1 7 0
tc1 6 0
tc1 5 0
tc1 4 0
tc1 3 0
tc1 2 0
tc1 1 0
tc1 0 0
Module Base + 0x0014-0x0015
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset
tc2 15 0
tc2 14 0
tc2 13 0
tc2 12 0
tc2 11 0
tc2 10 0
tc2 9 0
tc2 8 0
tc2 7 0
tc2 6 0
tc2 5 0
tc2 4 0
tc2 3 0
tc2 2 0
tc2 1 0
tc2 0 0
Module Base + 0x0016-0x0017
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset
tc3 15 0
tc3 14 0
tc3 13 0
tc3 12 0
tc3 11 0
tc3 10 0
tc3 9 0
tc3 8 0
tc3 7 0
tc3 6 0
tc3 5 0
tc3 4 0
tc3 3 0
tc3 2 0
tc3 1 0
tc3 0 0
Module Base + 0x0018-0x0019
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset
tc4 15 0
tc4 14 0
tc4 13 0
tc4 12 0
tc4 11 0
tc4 10 0
tc4 9 0
tc4 8 0
tc4 7 0
tc4 6 0
tc4 5 0
tc4 4 0
tc4 3 0
tc4 2 0
tc4 1 0
tc4 0 0
Module Base + 0x001A-0x001B
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset
tc5 15 0
tc5 14 0
tc5 13 0
tc5 12 0
tc5 11 0
tc5 10 0
tc5 9 0
tc5 8 0
tc5 7 0
tc5 6 0
tc5 5 0
tc5 4 0
tc5 3 0
tc5 2 0
tc5 1 0
tc5 0 0
Module Base + 0x001C-0x001D
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset
tc6 15 0
tc6 14 0
tc6 13 0
tc6 12 0
tc6 11 0
tc6 10 0
tc6 9 0
tc6 8 0
tc6 7 0
tc6 6 0
tc6 5 0
tc6 4 0
tc6 3 0
tc6 2 0
tc6 1 0
tc6 0 0
Module Base + 0x001E-0x001F
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset
tc7 15 0
tc7 14 0
tc7 13 0
tc7 12 0
tc7 11 0
tc7 10 0
tc7 9 0
tc7 8 0
tc7 7 0
tc7 6 0
tc7 5 0
tc7 4 0
tc7 3 0
tc7 2 0
tc7 1 0
tc7 0 0
Figure 10-16. Timer Input Capture/Output Compare Registers (TC0-TC7)
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 293
Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
Depending on the TIOS bit for the corresponding channel, these registers are used to latch the value of the free-running counter when a defined transition is sensed by the corresponding input capture edge detector or to trigger an output action for output compare. Read anytime. Write anytime for output compare function. Writes to these registers have no meaning or effect during input capture. All timer input capture/output compare registers are reset to 0x0000.
10.3.2.15 16-Bit Pulse Accumulator A Control Register (PACTL)
Module Base + 0x0020
7 6 5 4 3 2 1 0
R W Reset
0 PAEN 0 0 PAMOD 0 PEDGE 0 CLK1 0 CLK0 0 PAOVI 0 PAI 0
= Unimplemented or Reserved
Figure 10-17. 16-Bit Pulse Accumulator Control Register (PACTL)
16-Bit Pulse Accumulator A (PACA) is formed by cascading the 8-bit pulse accumulators PAC3 and PAC2. When PAEN is set, the PACA is enabled. The PACA shares the input pin with IC7. Read: Anytime Write: Anytime
Table 10-14. PACTL Field Descriptions
Field 6 PAEN Description Pulse Accumulator A System Enable -- PAEN is independent from TEN. With timer disabled, the pulse accumulator can still function unless pulse accumulator is disabled. 0 16-Bit Pulse Accumulator A system disabled. 8-bit PAC3 and PAC2 can be enabled when their related enable bits in ICPAR (0x0028) are set. Pulse Accumulator Input Edge Flag (PAIF) function is disabled. 1 16-Bit Pulse Accumulator A system enabled. The two 8-bit pulse accumulators PAC3 and PAC2 are cascaded to form the PACA 16-bit pulse accumulator. When PACA in enabled, the PACN3 and PACN2 registers contents are respectively the high and low byte of the PACA. PA3EN and PA2EN control bits in ICPAR (0x0028) have no effect. Pulse Accumulator Input Edge Flag (PAIF) function is enabled. Pulse Accumulator Mode -- This bit is active only when the Pulse Accumulator A is enabled (PAEN = 1). 0 Event counter mode 1 Gated time accumulation mode
5 PAMOD
MC3S12RG128 Data Sheet, Rev. 1.05 294 Freescale Semiconductor
Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
Table 10-14. PACTL Field Descriptions (continued)
Field 4 PEDGE Description Pulse Accumulator Edge Control -- This bit is active only when the Pulse Accumulator A is enabled (PAEN = 1). See Table 10-15. For PAMOD bit = 0 (event counter mode). 0 Falling edges on PT7 pin cause the count to be incremented 1 Rising edges on PT7 pin cause the count to be incremented For PAMOD bit = 1 (gated time accumulation mode). 0 PT7 input pin high enables bus clock divided by 64 to Pulse Accumulator and the trailing falling edge on PT7 sets the PAIF flag. 1 PT7 input pin low enables bus clock divided by 64 to Pulse Accumulator and the trailing rising edge on PT7 sets the PAIF flag Note: If the timer is not active (TEN = 0 in TSCR), there is no divide-by-64 since the /64 clock is generated by the timer prescaler. Clock Select Bits -- If the pulse accumulator is disabled (PAEN = 0), the prescaler clock from the timer is always used as an input clock to the timer counter. The change from one selected clock to the other happens immediately after these bits are written. Refer to Table 10-16 and for the description of PACLK please refer Figure 10-17. Pulse Accumulator A Overflow Interrupt Enable 0 Interrupt inhibited 1nterrupt requested if PAOVF is set Pulse Accumulator Input Interrupt Enable 0 Interrupt inhibited 1 Interrupt requested if PAIF is set
3-2 CLK[1:0]
1 PAOVI
0 PAI
Table 10-15. Pin Action
PAMOD 0 0 1 1 PEDGE 0 1 0 1 Pin Action Falling edge Rising edge Divide by 64 clock enabled with pin high level Divide by 64 clock enabled with pin low level
Table 10-16. Clock Selection
CLK1 0 0 1 1 CLK0 0 1 0 1 Clock Source Use timer prescaler clock as timer counter clock Use PACLK as input to timer counter clock Use PACLK/256 as timer counter clock frequency Use PACLK/65536 as timer counter clock frequency
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 295
Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
10.3.2.16 Pulse Accumulator A Flag Register (PAFLG)
Module Base + 0x0021
7 6 5 4 3 2 1 0
R W Reset
0
0
0
0
0
0 PAOVF PAIF 0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 10-18. Pulse Accumulator A Flag Register (PAFLG)
Read or write anytime. When the TFFCA bit in the TSCR register is set, any access to the PACNT register will clear all the flags in the PAFLG register.
Table 10-17. PAFLG Field Descriptions
Field 1 PAOVF Description Pulse Accumulator A Overflow Flag -- Set when the 16-bit pulse accumulator A overflows from 0xFFFF to 0x0000,or when 8-bit pulse accumulator 3 (PAC3) overflows from 0x00FF to 0x0000. When PACMX = 1, PAOVF bit can also be set if 8 - bit pulse accumulator 3 (PAC3) reaches 0x00FF followed by an active edge on PT3. This bit is cleared automatically by a write to the PAFLG register with bit 1 set. Pulse Accumulator Input edge Flag -- Set when the selected edge is detected at the PT7 input pin. In event mode the event edge triggers PAIF and in gated time accumulation mode the trailing edge of the gate signal at the PT7 input pin triggers PAIF. This bit is cleared by a write to the PAFLG register with bit 0 set. Any access to the PACN3, PACN2 registers will clear all the flags in this register when TFFCA bit in register TSCR(0x0006) is set.
0 PAIF
MC3S12RG128 Data Sheet, Rev. 1.05 296 Freescale Semiconductor
Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
10.3.2.17 Pulse Accumulators Count Registers (PACN3/PACN2)
Module Base + 0x0022
7 6 5 4 3 2 1 0
R PACNT7(15) PACNT6(14) PACNT5(13) PACNT4(12) PACNT3(11) PACNT2(10) W Reset 0 0 0 0 0 0 0 0 PACNT1(9) PACNT0(8)
Figure 10-19. Pulse Accumulators Count Register 3 (PACN3)
Module Base + 0x0023
7 6 5 4 3 2 1 0
R PACNT7 W Reset 0 0 0 0 0 0 0 0 PACNT6 PACNT5 PACNT4 PACNT3 PACNT2 PACNT1 PACNT0
Figure 10-20. Pulse Accumulators Count Register 2 (PACN2)
Read or write anytime. The two 8-bit pulse accumulators PAC3 and PAC2 are cascaded to form the PACA 16-bit pulse accumulator. When PACA in enabled (PAEN = 1 in PACTL, 0x0020) the PACN3 and PACN2 registers contents are respectively the high and low byte of the PACA. When PACN3 overflows from 0x00FF to 0x0000, the Interrupt flag PAOVF in PAFLG (0x0021) is set. Full count register access should take place in one clock cycle. A separate read/write for high byte and low byte will give a different result than accessing them as a word. NOTE When clocking pulse and write to the registers occurs simultaneously, write takes priority and the register is not incremented.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 297
Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
10.3.2.18 Pulse Accumulators Count Registers (PACN1/PACN0)
Module Base + 0x0024
7 6 5 4 3 2 1 0
R PACNT7(15) PACNT6(14) PACNT5(13) PACNT4(12) PACNT3(11) PACNT2(10) W Reset 0 0 0 0 0 0 0 0 PACNT1(9) PACNT0(8)
Figure 10-21. Pulse Accumulators Count Register 1 (PACN1)
Module Base + 0x0025
7 6 5 4 3 2 1 0
R PACNT7 W Reset 0 0 0 0 0 0 0 0 PACNT6 PACNT5 PACNT4 PACNT3 PACNT2 PACNT1 PACNT0
Figure 10-22. Pulse Accumulators Count Register 0 (PACN0)
Read or write anytime. The two 8-bit pulse accumulators PAC1 and PAC0 are cascaded to form the PACB 16-bit pulse accumulator. When PACB in enabled, (PBEN = 1 in PBCTL, 0x0030) the PACN1 and PACN0 registers contents are respectively the high and low byte of the PACB. When PACN1 overflows from 0x00FF to 0x0000, the Interrupt flag PBOVF in PBFLG (0x0031) is set. Full count register access should take place in one clock cycle. A separate read/write for high byte and low byte will give a different result than accessing them as a word NOTE When clocking pulse and write to the registers occurs simultaneously, write takes priority and the register is not incremented.
10.3.2.19 16-Bit Modulus Down-Counter Control Register (MCCTL)
Module Base + 0x0026
7 6 5 4 3 2 1 0
R MCZI W Reset 0 0 0 MODMC RDMCL
0 ICLAT 0
0 MCEN FLMC 0 0 0 0 MCPR1 MCPR0
Figure 10-23. 16-Bit Modulus Down-Counter Control Register (MCCTL)
Read or write anytime.
MC3S12RG128 Data Sheet, Rev. 1.05 298 Freescale Semiconductor
Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
Table 10-18. Field Descriptions
Field 7 MCZI 6 MODMC Modulus Counter Underflow Interrupt Enable 0 Modulus counter interrupt is disabled. 1 Modulus counter interrupt is enabled. Modulus Mode Enable 0 The counter counts once from the value written to it and will stop at 0x0000. 1 Modulus mode is enabled. When the counter reaches 0x0000, the counter is loaded with the latest value written to the modulus count register. Note: For proper operation, the MCEN bit should be cleared before modifying the MODMC bit in order to reset the modulus counter to 0xFFFF. Read Modulus Down-Counter Load 0 Reads of the modulus count register will return the present value of the count register. 1 Reads of the modulus count register will return the contents of the load register. Input Capture Force Latch Action -- When input capture latch mode is enabled (LATQ and BUFEN bit in ICSYS (0x002B) are set, a write one to this bit immediately forces the contents of the input capture registers TC0 to TC3 and their corresponding 8-bit pulse accumulators to be latched into the associated holding registers. The pulse accumulators will be automatically cleared when the latch action occurs. Writing zero to this bit has no effect. Read of this bit will return always zero. Force Load Register into the Modulus Counter Count Register -- This bit is active only when the modulus down-counter is enabled (MCEN = 1). A write one into this bit loads the load register into the modulus counter count register. This also resets the modulus counter prescaler. Write zero to this bit has no effect. When MODMC = 0, counter starts counting and stops at 0x0000. Read of this bit will return always zero. Modulus Down-Counter Enable -- When MCEN = 0, the counter is preset to 0xFFFF. This will prevent an early interrupt flag when the modulus down-counter is enabled. 0 Modulus counter disabled. 1 Modulus counter is enabled. Modulus Counter Prescaler Select -- These two bits specify the division rate of the modulus counter prescaler. The newly selected prescaler division rate will not be effective until a load of the load register into the modulus counter count register occurs. See Table 10-19. Description
5 RDMCL 4 ICLAT
3 FLMC
2 MCEN
1-0 MCPR[1:0]
Table 10-19. Modulus Counter Prescaler Select
MCPR1 0 0 1 1 MCPR0 0 1 0 1 Prescaler Division Rate 1 4 8 16
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 299
Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
10.3.2.20 16-Bit Modulus Down-Counter Flag Register (MCFLG)
Module Base + 0x0027
7 6 5 4 3 2 1 0
R MCZF W Reset 0
0
0
0
POLF3
POLF2
POLF1
POLF0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 10-24. 16-Bit Modulus Down-Counter FLAG Register (MCFLG)
Read: Anytime Write: Only for clearing bit 7
Table 10-20. MCFLG Field Descriptions
Field 7 MCZF 3-0 POLF[3:0] Description Modulus Counter Underflow Flag -- The flag is set when the modulus down-counter reaches 0x0000. A write one to this bit clears the flag. Write zero has no effect. Any access to the MCCNT register will clear the MCZF flag in this register when TFFCA bit in register TSCR(0x0006) is set. First Input Capture Polarity Status -- This are read only bits. Write to these bits has no effect. Each status bit gives the polarity of the first edge which has caused an input capture to occur after capture latch has been read. Each POLFn corresponds to a timer PORTn input. 0 The first input capture has been caused by a falling edge. 1 The first input capture has been caused by a rising edge.
MC3S12RG128 Data Sheet, Rev. 1.05 300 Freescale Semiconductor
Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
10.3.2.21 Input Control Pulse Accumulators Register (ICPAR)
Module Base + 0x0028
7 6 5 4 3 2 1 0
R W Reset
0
0
0
0 PA3EN PA2EN 0 PA1EN 0 PA0EN 0
0
0
0
0
0
= Unimplemented or Reserved
Figure 10-25. Input Control Pulse Accumulators Register (ICPAR)
The 8-bit pulse accumulators PAC3 and PAC2 can be enabled only if PAEN in PATCL (0x0020) is cleared. If PAEN is set, PA3EN and PA2EN have no effect. The 8-bit pulse accumulators PAC1 and PAC0 can be enabled only if PBEN in PBTCL (0x0030) is cleared. If PBEN is set, PA1EN and PA0EN have no effect. Read or write anytime.
Table 10-21. ICPAR Field Descriptions
Field 3-0 PA[3:0]EN 8-Bit Pulse Accumulator Enable 0 8-Bit Pulse Accumulator is disabled. 1 8-Bit Pulse Accumulator is enabled. Description
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 301
Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
10.3.2.22 Delay Counter Control Register (DLYCT)
Module Base + 0x0029
7 6 5 4 3 2 1 0
R W Reset
0
0
0
0
0
0 DLY1 DLY0 0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 10-26. Delay Counter Control Register (DLYCT)
Read or write anytime. If enabled, after detection of a valid edge on input capture pin, the delay counter counts the pre-selected number of bus clock cycles, then it will generate a pulse on its output. The pulse is generated only if the level of input signal, after the preset delay, is the opposite of the level before the transition.This will avoid reaction to narrow input pulses. After counting, the counter will be cleared automatically. Delay between two active edges of the input signal period should be longer than the selected counter delay.
Table 10-22. DLYCT Field Descriptions
Field 1-0 DLY[1:0] Delay Counter Select -- See Table 10-23. Description
Table 10-23. Delay Counter Select
DLY1 0 0 1 1 DLY0 0 1 0 1 Delay Disabled (bypassed) 256 bus clock cycles 512 bus clock cycles 1024 bus clock cycles
MC3S12RG128 Data Sheet, Rev. 1.05 302 Freescale Semiconductor
Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
10.3.2.23 Input Control Overwrite Register (ICOVW)
Module Base + 0x002A
7 6 5 4 3 2 1 0
R NOVW7 W Reset 0 0 0 0 0 0 0 0 NOVW6 NOVW5 NOVW4 NOVW3 NOVW2 NOVW1 NOVW0
Figure 10-27. Input Control Overwrite Register (ICOVW))
Read or write anytime. An IC register is empty when it has been read or latched into the holding register. A holding register is empty when it has been read.
Table 10-24. ICOVW Field Descriptions
Field 7-0 NOVW[7:0] Description No Input Capture Overwrite 0 The contents of the related capture register or holding register can be overwritten when a new input capture or latch occurs. 1 The related capture register or holding register cannot be written by an event unless they are empty (see Section 10.4.1.1, "IC Channels"). This will prevent the captured value to be overwritten until it is read or latched in the holding register.
10.3.2.24 Input Control System Control Register (ICSYS)
Module Base + 0x002B
7 6 5 4 3 2 1 0
R SH37 W Reset 0 0 0 0 0 0 0 0 SH26 SH15 SH04 TFMOD PACMX BUFEN LATQ
Figure 10-28. Input Control System Register (ICSYS)
Read: Anytime Write: Can be written once (test_mode = 0). Writes are always permitted when test_mode = 1.
Table 10-25. ICSYS Field Descriptions
Field Description
7-4 Share Input action of Input Capture Channels x and y SH37, SH26, 0 Normal operation SH15, SH04 1 The channel input `x' causes the same action on the channel `y'. The port pin `x' and the corresponding edge detector is used to be active on the channel `y'.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 303
Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
Table 10-25. ICSYS Field Descriptions (continued)
Field 3 TFMOD Description Timer Flag-setting Mode -- Use of the TFMOD bit in the ICSYS register (0x002B) in conjunction with the use of the ICOVW register (0x002A) allows a timer interrupt to be generated after capturing two values in the capture and holding registers instead of generating an interrupt for every capture. By setting TFMOD in queue mode, when NOVW bit is set and the corresponding capture and holding registers are emptied, an input capture event will first update the related input capture register with the main timer contents. At the next event the TCn data is transferred to the TCnH register, The TCn is updated and the CnF interrupt flag is set. In all other input capture cases the interrupt flag is set by a valid external event on PTn. 0 The timer flags C3F-C0F in TFLG1 (0x000E) are set when a valid input capture transition on the corresponding port pin occurs. 1 If in queue mode (BUFEN = 1 and LATQ = 0), the timer flags C3F-C0F in TFLG1 (0x000E) are set only when a latch on the corresponding holding register occurs. If the queue mode is not engaged, the timer flags C3F-C0F are set the same way as for TFMOD = 0. 2 PACMX 8-Bit Pulse Accumulators Maximum Count 0 Normal operation. When the 8-bit pulse accumulator has reached the value 0x00FF, with the next active edge, it will be incremented to 0x0000. 1 When the 8-bit pulse accumulator has reached the value 0x00FF, it will not be incremented further. The value 0x00FF indicates a count of 255 or more. IC Buffer Enable 0 Input Capture and pulse accumulator holding registers are disabled. 1 Input Capture and pulse accumulator holding registers are enabled. The latching mode is defined by LATQ control bit. Write one into ICLAT bit in MCCTL (0x0026), when LATQ is set will produce latching of input capture and pulse accumulators registers into their holding registers. Input Control Latch or Queue Mode Enable -- The BUFEN control bit should be set in order to enable the IC and pulse accumulators holding registers. Otherwise LATQ latching modes are disabled. Write one into ICLAT bit in MCCTL (0x0026), when LATQ and BUFEN are set will produce latching of input capture and pulse accumulators registers into their holding registers. 0 Queue Mode of Input Capture is enabled. The main timer value is memorized in the IC register by a valid input pin transition. With a new occurrence of a capture, the value of the IC register will be transferred to its holding register and the IC register memorizes the new timer value. 1 Latch Mode is enabled. Latching function occurs when modulus down-counter reaches zero or a zero is written into the count register MCCNT (seeSection 10.4.1.1.2, "Buffered IC Channels"). With a latching event the contents of IC registers and 8-bit pulse accumulators are transferred to their holding registers. 8-bit pulse accumulators are cleared.
1 BUFFEN
0 LAT!
MC3S12RG128 Data Sheet, Rev. 1.05 304 Freescale Semiconductor
Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
10.3.2.25 16-Bit Pulse Accumulator B Control Register (PBCTL)
Module Base + 0x0030
7 6 5 4 3 2 1 0
R W Reset
0 PBEN 0 0
0
0
0
0 PBOVI
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 10-29. 16-Bit Pulse Accumulator B Control Register (PBCTL)
Read or write anytime. 16-Bit Pulse Accumulator B (PACB) is formed by cascading the 8-bit pulse accumulators PAC1 and PAC0. When PBEN is set, the PACB is enabled. The PACB shares the input pin with IC0.
Table 10-26. PBCTL Field Descriptions
Field 6 PBEN Description Pulse Accumulator B System Enable -- PBEN is independent from TEN. With timer disabled, the pulse accumulator can still function unless pulse accumulator is disabled. 0 16-bit Pulse Accumulator system disabled. 8-bit PAC1 and PAC0 can be enabled when their related enable bits in ICPAR (0x0028) are set. 1 Pulse Accumulator B system enabled. The two 8-bit pulse accumulators PAC1 and PAC0 are cascaded to form the PACB 16-bit pulse accumulator. When PACB in enabled, the PACN1 and PACN0 registers contents are respectively the high and low byte of the PACB. PA1EN and PA0EN control bits in ICPAR (0x0028) have no effect. Pulse Accumulator B Overflow Interrupt Enable 0 Interrupt inhibited 1 Interrupt requested if PBOVF is set
1 PBOVI
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 305
Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
10.3.2.26 Pulse Accumulator B Flag Register (PBFLG)
Module Base + 0x0000
7 6 5 4 3 2 1 0
R W Reset
0
0
0
0
0
0 PBOVF
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 10-30. Pulse Accumulator B Flag Register (PBFLG)
Read or write anytime.
Table 10-27. PBFLG Field Descriptions
Field 1 PBOVF Description Pulse Accumulator B Overflow Flag -- This bit is set when the 16-bit pulse accumulator B overflows from 0xFFFF to 0x0000, or when 8-bit pulse accumulator 1 (PAC1) overflows from 0x00FF to 0x0000. This bit is cleared by a write to the PBFLG register with bit 1 set. Any access to the PACN1 and PACN0 registers will clear the PBOVF flag in this register when TFFCA bit in register TSCR(0x0006) is set. When PACMX = 1, PBOVF bit can also be set if 8 - bit pulse accumulator 1 (PAC1) reaches 0x00FF and followed an active edge comes on PT1.
MC3S12RG128 Data Sheet, Rev. 1.05 306 Freescale Semiconductor
Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
10.3.2.27 8-Bit Pulse Accumulators Holding Registers (PA3H-PA0H)
Module Base + 0x0032
7 6 5 4 3 2 1 0
R W Reset
PA3H7
PA3H6
PA3H5
PA3H4
PA3H3
PA3H2
PA3H1
PA3H0
0
0
0
0
0
0
0
0
Module Base + 0x0033
7 6 5 4 3 2 1 0
R W Reset
PA2H7
PA2H6
PA2H5
PA2H4
PA2H3
PA2H2
PA2H1
PA2H0
0
0
0
0
0
0
0
0
Module Base + 0x0034
7 6 5 4 3 2 1 0
R W Reset
PA1H7
PA1H6
PA1H5
PA1H4
PA1H3
PA1H2
PA1H1
PA1H0
0
0
0
0
0
0
0
0
Module Base + 0x0035
7 6 5 4 3 2 1 0
R W Reset
PA0H7
PA0H6
PA0H5
PA0H4
PA0H3
PA0H2
PA0H1
PA0H0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 10-31. 8-Bit Pulse Accumulators Holding Registers (PA3H-PA0H)
Read: Anytime Write: Has no effect. These registers are used to latch the value of the corresponding pulse accumulator when the related bits in register ICPAR (0x0028) are enabled (see Section 10.4.1.2, "Pulse Accumulators").
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 307
Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
10.3.2.28 Modulus Down-Counter Count Register (MCCNT)
Module Base + 0x0036-0x0037
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R mccnt mccnt mccnt mccnt mccnt mccnt mccnt mccnt mccnt mccnt mccnt mccnt mccnt mccnt mccnt mccnt W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Figure 10-32. Modulus Down-Counter Count Register (MCCNT)
Read or write anytime. A full access for the counter register should take place in one clock cycle. A separate read/write for high byte and low byte will give different result than accessing them as a word. If the RDMCL bit in MCCTL register is cleared, reads of the MCCNT register will return the present value of the count register. If the RDMCL bit is set, reads of the MCCNT will return the contents of the load register. If a 0x0000 is written into MCCNT and modulus counter while LATQ and BUFEN in ICSYS (0x002B) register are set, the input capture and pulse accumulator registers will be latched. With a 0x0000 write to the MCCNT, the modulus counter will stay at zero and does not set the MCZF flag in MCFLG register. If modulus mode is enabled (MODMC = 1), a write to this address will update the load register with the value written to it. The count register will not be updated with the new value until the next counter underflow. The FLMC bit in MCCTL (0x0026) can be used to immediately update the count register with the new value if an immediate load is desired. If modulus mode is not enabled (MODMC = 0), a write to this address will clear the prescaler and will immediately update the counter register with the value written to it and down-counts once to 0x0000.
MC3S12RG128 Data Sheet, Rev. 1.05 308 Freescale Semiconductor
Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
10.3.2.29 Timer Input Capture Holding Registers (TC0H-TC3H)
Module Base + 0x0038-0x0039
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R TC15 TC14 TC13 TC12 TC11 TC10 W Reset 0 0 0 0 0 0
TC9 0
TC8 0
TC7 0
TC6 0
TC5 0
TC4 0
TC3 0
TC2 0
TC1 0
TC0 0
= Unimplemented or Reserved
Figure 10-33. Timer Input Capture Holding Register 0 (TC0H)
Module Base + 0x003A-0x003B
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R TC15 TC14 TC13 TC12 TC11 TC10 W Reset 0 0 0 0 0 0
TC9 0
TC8 0
TC7 0
TC6 0
TC5 0
TC4 0
TC3 0
TC2 0
TC1 0
TC0 0
= Unimplemented or Reserved
Figure 10-34. Timer Input Capture Holding Register 1 (TC1H)
Module Base + 0x003C-0x003D
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R TC15 TC14 TC13 TC12 TC11 TC10 W Reset 0 0 0 0 0 0
TC9 0
TC8 0
TC7 0
TC6 0
TC5 0
TC4 0
TC3 0
TC2 0
TC1 0
TC0 0
= Unimplemented or Reserved
Figure 10-35. Timer Input Capture Holding Register 2 (TC2H)
Module Base + 0x003E-0x003F
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R TC15 TC14 TC13 TC12 TC11 TC10 W Reset 0 0 0 0 0 0
TC9 0
TC8 0
TC7 0
TC6 0
TC5 0
TC4 0
TC3 0
TC2 0
TC1 0
TC0 0
= Unimplemented or Reserved
Figure 10-36. Timer Input Capture Holding Register 3 (TC3H)
Read: Anytime Write: Has no effect. These registers are used to latch the value of the input capture registers TC0-TC3. The corresponding IOSn bits in TIOS (0x0000) should be cleared (see Section 10.4.1.1, "IC Channels").
10.4
Functional Description
This section provides a complete functional description of the ECT block, detailing the operation of the design from the end user perspective in a number of subsections. Refer to the Timer Block Diagrams from Figure 10-37 to Figure 10-41 as necessary.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 309
Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
TIMCLK 1, 2, ..., 128 BUS CLOCK PRESCALER
16-BIT FREE-RUNNING MAIN TIMER 16 BIT MAIN TIMER BUS CLOCK PCLK
1, 4, 8, 16 PRESCALER
16-BIT LOAD REGISTER 16-BIT MODULUS DOWN COUNTER 0 RESET UNDERFLOW LATCH
P0
PIN LOGIC
DELAY COUNTER EDG0
COMPARATOR TC0 CAPTURE/ COMPARE REGISTER
PAC0
TC0H HOLD REGISTER PIN LOGIC COMPARATOR TC1 CAPTURE/ COMPARE REGISTER
PA0H HOLD REGISTER 0 RESET PAC1
P1
DELAY COUNTER EDG1
TC1H HOLD REGISTER PIN LOGIC COMPARATOR TC2 CAPTURE/ COMPARE REGISTER
PA1H HOLD REGISTER 0 RESET PAC2
P2
DELAY COUNTER EDG2
TC2H HOLD REGISTER P3 PIN LOGIC COMPARATOR TC3 CAPTURE/ COMPARE REGISTER
PA2H HOLD REGISTER 0 PAC3 RESET
DELAY COUNTER EDG3
TC3H HOLD REGISTER P4 PIN LOGIC COMPARATOR EDG4 EDG0 SH04 P5 PIN LOGIC COMPARATOR TC5 CAPTURE/ COMPARE REGISTER MUX TC4 CAPTURE/ COMPARE REGISTER
PA3H HOLD REGISTER
ICLAT, LATQ, BUFEN (FORCE LATCH)
EDG5 EDG1 MUX
WRITE 0X0000 TO MODULUS COUNTER
SH15 P6 PIN LOGIC COMPARATOR TC6 CAPTURE/ COMPARE REGISTER LATQ (MDC LATCH ENABLE)
EDG6 EDG2 SH26 MUX
P7
PIN LOGIC
EDG7 EDG3 MUX
COMPARATOR TC7 CAPTURE/ COMPARE REGISTER
SH37
Figure 10-37. Detailed Timer Block Diagram in Latch Mode
MC3S12RG128 Data Sheet, Rev. 1.05 310 Freescale Semiconductor
Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
TIMCLK 1, 2, ..., 128 BUS CLOCK PRESCALER
16-BIT FREE-RUNNING MAIN TIMER 16 BIT MAIN TIMER BUS CLOCK PCLK
1, 4, 8, 16 PRESCALER
16-BIT LOAD REGISTER 16-BIT MODULUS DOWN COUNTER 0 RESET
P0
PIN LOGIC
DELAY COUNTER EDG0
COMPARATOR TC0 CAPTURE/ COMPARE REGISTER
PAC0 LATCH0 LATCH3 LATCH2 LATCH1
TC0H HOLD REGISTER PIN LOGIC COMPARATOR TC1 CAPTURE/ COMPARE REGISTER
PA0H HOLD REGISTER 0 RESET PAC1
P1
DELAY COUNTER EDG1
TC1H HOLD REGISTER PIN LOGIC COMPARATOR TC2 CAPTURE/ COMPARE REGISTER
PA1H HOLD REGISTER 0 RESET PAC2
P2
DELAY COUNTER EDG2
TC2H HOLD REGISTER P3 PIN LOGIC COMPARATOR TC3 CAPTURE/ COMPARE REGISTER
PAH HOLD REGISTER 0 PAC3 RESET
DELAY COUNTER EDG3
TC3H HOLD REGISTER P4 PIN LOGIC COMPARATOR EDG4 EDG0 SH04 P5 PIN LOGIC COMPARATOR TC5 CAPTURE/ COMPARE REGISTER MUX TC4 CAPTURE/ COMPARE REGISTER
PA3H HOLD REGISTER
LATQ, BUFEN (QUEUE MODE)
READ TC3H HOLD REGISTER
EDG5 EDG1 MUX
READ TC2H HOLD REGISTER COMPARATOR TC6 CAPTURE/ COMPARE REGISTER
SH15 P6 PIN LOGIC
EDG6 EDG2 SH26 MUX
READ TC1H HOLD REGISTER
P7
PIN LOGIC
EDG7 EDG3 MUX
COMPARATOR TC7 CAPTURE/ COMPARE REGISTER
READ TC0H HOLD REGISTER
SH37
Figure 10-38. Detailed Timer Block Diagram in Queue Mode
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 311
Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
LOAD HOLDING REGISTER AND RESET PULSE ACCUMULATOR
0 P0 EDGE DETECTOR EDG0 DELAY COUNTER 8-BIT PAC0 (PACN0)
PA0H HOLDING REGISTER INTERRUPT 0 P1 EDGE DETECTOR EDG1 DELAY COUNTER 8-BIT PAC1 (PACN1)
PA1H HOLDING REGISTER
0 P2 EDGE DETECTOR EDG2 DELAY COUNTER 8-BIT PAC2 (PACN2)
PA2H HOLDING REGISTER INTERRUPT 0 EDG3 P3 EDGE DETECTOR DELAY COUNTER 8-BIT PAC3 (PACN3)
PA3H HOLDING REGISTER
Figure 10-39. 8-Bit Pulse Accumulators Block Diagram
MC3S12RG128 Data Sheet, Rev. 1.05 312 Freescale Semiconductor
Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
TIMCLK (TIMER CLOCK)
CLK1 CLK0
4:1 MUX
PACLK / 256
LK / 65536
PRESCALED CLOCK (PCLK)
CLOCK SELECT (PAMOD) PACLK
EDGE DETECTOR
P7
INTERRUPT
8-BIT PAC3 (PACN3) PACA
8-BIT PAC2 (PACN2)
MUX
DIVIDE BY 64
BUS CLOCK
INTERRUPT
8-BIT PAC3 (PACN1) PACB
8-BIT PAC2 (PACN0)
DELAY COUNTER
EDGE DETECTOR
P0
Figure 10-40. 16-Bit Pulse Accumulators Block Diagram
16-BIT MAIN TIMER
PN
EDGE DETECTOR
DELAY COUNTER TCn INPUT CAPTURE REGISTER SET CnF INTERRUPT
TCnH I.C. HOLDING BUFEN * LATQ * TFMOD HOLDING REGISTER
Figure 10-41. Block Diagram for Port 7 with Output Compare/Pulse Accumulator A
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 313
Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
10.4.1
Enhanced Capture Timer Modes of Operation
The Enhanced Capture Timer has eight Input Capture, Output Compare (IC/OC) channels same as on the HC12 standard timer (timer channels TC0 to TC7). When channels are selected as input capture by selecting the IOSn bit in TIOS register, they are called Input Capture (IC) channels. Four IC channels are the same as on the standard timer with one capture register each which memorizes the timer value captured by an action on the associated input pin. Four other IC channels, in addition to the capture register, have also one buffer each called holding register. This permits to memorize two different timer values without generation of any interrupt. Four 8-bit pulse accumulators are associated with the four buffered IC channels. Each pulse accumulator has a holding register to memorize their value by an action on its external input. Each pair of pulse accumulators can be used as a 16-bit pulse accumulator. The 16-bit modulus down-counter can control the transfer of the IC registers contents and the pulse accumulators to the respective holding registers for a given period, every time the count reaches zero. The modulus down-counter can also be used as a stand-alone time base with periodic interrupt capability.
10.4.1.1
IC Channels
The IC channels are composed of four standard IC registers and four buffered IC channels. An IC register is empty when it has been read or latched into the holding register. A holding register is empty when it has been read. 10.4.1.1.1 Non-Buffered IC Channels
The main timer value is memorized in the IC register by a valid input pin transition. If the corresponding NOVWx bit of the ICOVW register is cleared, with a new occurrence of a capture, the contents of IC register are overwritten by the new value. If the corresponding NOVWx bit of the ICOVW register is set, the capture register cannot be written unless it is empty. This will prevent the captured value to be overwritten until it is read. 10.4.1.1.2 Buffered IC Channels
There are two modes of operations for the buffered IC channels. 1. IC Latch Mode: When enabled (LATQ = 1), the main timer value is memorized in the IC register by a valid input pin transition. See Figure 10-37. The value of the buffered IC register is latched to its holding register by the Modulus counter for a given period when the count reaches zero, by a write 0x0000 to the modulus counter or by a write to ICLAT in the MCCTL register. If the corresponding NOVWn bit of the ICOVW register is cleared, with a new occurrence of a capture, the contents of IC register are overwritten by the new value. In case of latching, the contents of its holding register are overwritten.
MC3S12RG128 Data Sheet, Rev. 1.05 314 Freescale Semiconductor
Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
If the corresponding NOVWn bit of the ICOVW register is set, the capture register or its holding register cannot be written by an event unless they are empty (see Section 10.4.1.1, "IC Channels"). This will prevent the captured value to be overwritten until it is read or latched in the holding register. 2. IC queue mode: When enabled (LATQ = 0), the main timer value is memorized in the IC register by a valid input pin transition. See Figure 10-38. If the corresponding NOVWn bit of the ICOVW register is cleared, with a new occurrence of a capture, the value of the IC register will be transferred to its holding register and the IC register memorizes the new timer value. If the corresponding NOVWn bit of the ICOVW register is set, the capture register or its holding register cannot be written by an event unless they are empty (see Section 10.4.1.1, "IC Channels"). In queue mode, reads of holding register will latch the corresponding pulse accumulator value to its holding register. 10.4.1.1.3 Delayed IC Channels
There are four delay counters in this module associated with IC channels 0-3. The use of this feature is explained in the diagram (Figure 10-42) and notes below.
BUS CLOCK
DLY_CNT
0
1
2
3
253
254
255
256
INPUT ON CH0-CH3
REJECTED 255 CYCLES
INPUT ON CH0-CH3 INPUT ON CH0-CH3
255.5 CYCLES
REJECTED
255.5 CYCLES
ACCEPTED
INPUT ON CH0-CH3
256 CYCLES
ACCEPTED
Figure 10-42. Channel Input Validity with Delay Counter Feature
In the diagram shown in Figure 10-42 a delay counter value of 256 bus cycles is considered. 1. Input pulses with a duration of (DLY_CNT - 1) cycles or shorter are rejected. 2. Input pulses with a duration between (DLY_CNT - 1) and DLY_CNT cycles may be rejected or accepted, depending on their relative alignment with the sample points.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 315
Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
3. Input pulses with a duration between (DLY_CNT - 1) and DLY_CNT cycles may be rejected or accepted, depending on their relative alignment with the sample points. 4. Input pulses with a duration of DLY_CNT or longer are accepted.
10.4.1.2
Pulse Accumulators
There are four 8-bit pulse accumulators with four 8-bit holding registers associated with the four IC buffered channels. A pulse accumulator counts the number of active edges at the input of its channel. The user can prevent 8-bit pulse accumulators counting further than 0x00FF by PACMX control bit in ICSYS (0x002B). In this case a value of 0x00FF means that 255 counts or more have occurred. Each pair of pulse accumulators can be used as a 16-bit pulse accumulator. See Figure 10-40. There are two modes of operation for the pulse accumulators. 10.4.1.2.1 Pulse Accumulator Latch Mode
The value of the pulse accumulator is transferred to its holding register when the modulus down-counter reaches zero, a write 0x0000 to the modulus counter or when the force latch control bit ICLAT is written. At the same time the pulse accumulator is cleared. 10.4.1.2.2 Pulse Accumulator Queue Mode
When queue mode is enabled, reads of an input capture holding register will transfer the contents of the associated pulse accumulator to its holding register. At the same time the pulse accumulator is cleared.
10.4.1.3
Modulus Down-Counter
The modulus down-counter can be used as a time base to generate a periodic interrupt. It can also be used to latch the values of the IC registers and the pulse accumulators to their holding registers. The action of latching can be programmed to be periodic or only once.
10.4.1.4
Channel Configurations
Timer Channels can be configured as input capture channels or output compare channels. Following are the ways a port can be configured as an output for OC. The pin associated with channel 7 becomes output-tied to OC7 when * TEN = 1, IOS7 = 1, and either or both of OM7 and OL7 are set. or * OC7M7 =1 and IOS7 = 1. When masking, the timer does not have to be enabled so that the pin associated with OCn becomes an output tied to OCn.
MC3S12RG128 Data Sheet, Rev. 1.05 316 Freescale Semiconductor
Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
The pins associated with channels 0-6 become output-tied to OCn (n = 0..6) when * TEN = 1, IOSn = 1, and either or both of OMn and OLn are set or * OC7Mn = 1, IOS7 = 1 and IOSn = 1 Once the pin is configured as OC, its initial state is zero and its status is changed (if needed) on consecutive clock cycles following the write which enabled the ECT to drive the pin. In other words after a pin starts to be driven by ECT OC logic, it is forced low for at least one clock cycle.
10.5
Reset
The reset state of each individual bit is listed within Section 10.3, "Memory Map and Registers" which details the registers and their bit-fields.
10.6
Interrupts
This section describes interrupts originated by the ECT16B8C block.The MCU must service the interrupt requests. Table 10-28 lists the interrupts generated by the ECT to communicate with the MCU. The ECT only originates interrupt requests. The following is a description of how the module makes a request and how the MCU should acknowledge that request. The interrupt vector offset and interrupt number are chip dependent.
Table 10-28. ECT Interrupts
Interrupt Source Timer channel 7-0 Modulus counter underflow Pulse accumulator B overflow Pulse accumulator A input Pulse accumulator A overflow Timer overflow Description Active high timer channel interrupts 7-0 Active high modulus counter interrupt Active high pulse accumulator B interrupt Active high pulse accumulator A input interrupt Pulse accumulator overflow interrupt Timer overflow interrupt
10.6.1
Channel [7:0] Interrupt
This active high output will be asserted by the module to request a timer channel 7 - 0 interrupt to be serviced by the system controller.
10.6.2
Modulus Counter Interrupt
This active high output will be asserted by the module to request a modulus counter underflow interrupt to be serviced by the system controller.
10.6.3
Pulse Accumulator B Overflow Interrupt)
This active high output will be asserted by the module to request a timer pulse accumulator B overflow interrupt to be serviced by the system controller.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 317
Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
10.6.4
Pulse Accumulator A Input Interrupt
This active high output will be asserted by the module to request a timer pulse accumulator A input interrupt to be serviced by the system controller.
10.6.5
Pulse Accumulator A Overflow Interrupt
This active high output will be asserted by the module to request a timer pulse accumulator A overflow interrupt to be serviced by the system controller.
10.6.6
Timer Overflow Interrupt
This active high output will be asserted by the module to request a timer overflow interrupt to be serviced by the system controller.
MC3S12RG128 Data Sheet, Rev. 1.05 318 Freescale Semiconductor
Chapter 11 Inter-Integrated Circuit (IICV2) Block Description
Version Number 0.1 2.06 2.07 Revision Date 8-Sep-99 18-Aug-20 02 12-Mar-20 04 Effective Date
Author
Description of Changes Original draft. Distributed only within Freescale Reformated for SRS3.0,and add examples for programing general use and some diagrams to make it more user friendly as suggested by Joachim Changed to Freescale chapter format
11.1
Introduction
The inter-IC bus (IIC) is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange between devices. Being a two-wire device, the IIC bus minimizes the need for large numbers of connections between devices, and eliminates the need for an address decoder. This bus is suitable for applications requiring occasional communications over a short distance between a number of devices. It also provides flexibility, allowing additional devices to be connected to the bus for further expansion and system development. The interface is designed to operate up to 100 kbps with maximum bus loading and timing. The device is capable of operating at higher baud rates, up to a maximum of clock/20, with reduced bus loading. The maximum communication length and the number of devices that can be connected are limited by a maximum bus capacitance of 400 pF.
11.1.1
Features
The IIC module has the following key features: * Compatible with I2C bus standard * Multi-master operation * Software programmable for one of 256 different serial clock frequencies * Software selectable acknowledge bit * Interrupt driven byte-by-byte data transfer * Arbitration lost interrupt with automatic mode switching from master to slave
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 319
Chapter 11 Inter-Integrated Circuit (IICV2) Block Description
* * * * *
Calling address identification interrupt Start and stop signal generation/detection Repeated start signal generation Acknowledge bit generation/detection Bus busy detection
MC3S12RG128 Data Sheet, Rev. 1.05 320 Freescale Semiconductor
Chapter 11 Inter-Integrated Circuit (IICV2) Block Description
11.1.2
Modes of Operation
The IIC functions the same in normal, special, and emulation modes. It has two low power modes: wait and stop modes.
11.1.3
Block Diagram
The block diagram of the IIC module is shown in Figure 11-1.
IIC Start Stop Arbitration Control
Registers
Interrupt Clock Control In/Out Data Shift Register SCL
bus_clock
SDA
Address Compare
Figure 11-1. IIC Block Diagram
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 321
Chapter 11 Inter-Integrated Circuit (IICV2) Block Description
11.2
External Signal Description
The IICV2 module has two external pins.
11.2.1
IIC_SCL -- Serial Clock Line Pin
This is the bidirectional serial clock line (SCL) of the module, compatible to the IIC bus specification.
11.2.2
IIC_SDA -- Serial Data Line Pin
This is the bidirectional serial data line (SDA) of the module, compatible to the IIC bus specification.
11.3
Memory Map and Register Definition
This section provides a detailed description of all memory and registers for the IIC module.
11.3.1
Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order.
Register Name 0x0000 IBAD 0x0001 IBFD 0x0002 IBCR 0x0003 IBSR 0x0004 IBDR R W R W R W R W R W D7 D6 D5 Bit 7 ADR7 6 ADR6 5 ADR5 4 ADR4 3 ADR3 2 ADR2 1 ADR1 Bit 0 0
IBC7
IBC6
IBC5
IBC4
IBC3
IBC2 0
IBC1 0
IBC0
IBEN TCF
IBIE IAAS
MS/SL IBB
Tx/Rx
TXAK 0
RSTA
SRW IBIF
IBSWAI RXAK
IBAL
D4
D3
D2
D1
D0
= Unimplemented or Reserved
Figure 11-2. IIC Register Summary
MC3S12RG128 Data Sheet, Rev. 1.05 322 Freescale Semiconductor
Chapter 11 Inter-Integrated Circuit (IICV2) Block Description
11.3.1.1
IIC Address Register (IBAD)
Offset Module Base +0x0000
7 6 5 4 3 2 1 0
R ADR7 W Reset 0 0 0 0 0 0 0 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1
0
0
= Unimplemented or Reserved
Figure 11-3. IIC Bus Address Register (IBAD)
Read and write anytime This register contains the address the IIC bus will respond to when addressed as a slave; note that it is not the address sent on the bus during the address transfer.
Table 11-1. IBAD Field Descriptions
Field 7:1 ADR[7:1] 0 Reserved Description Slave Address -- Bit 1 to bit 7 contain the specific slave address to be used by the IIC bus module.The default mode of IIC bus is slave mode for an address match on the bus. Reserved -- Bit 0 of the IBAD is reserved for future compatibility. This bit will always read 0.
11.3.1.2
IIC Frequency Divider Register (IBFD)
Offset Module Base + 0x0001
7 6 5 4 3 2 1 0
R IBC7 W Reset 0 0 0 0 0 0 0 0 IBC6 IBC5 IBC4 IBC3 IBC2 IBC1 IBC0
= Unimplemented or Reserved
Figure 11-4. IIC Bus Frequency Divider Register (IBFD)
Read and write anytime
Table 11-2. IBFD Field Descriptions
Field 7:0 IBC[7:0] Description I Bus Clock Rate 7:0 -- This field is used to prescale the clock for bit rate selection. The bit clock generator is implemented as a prescale divider -- IBC7:6, prescaled shift register -- IBC5:3 select the prescaler divider and IBC2-0 select the shift register tap point. The IBC bits are decoded to give the tap and prescale values as shown in Table 11-3.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 323
Chapter 11 Inter-Integrated Circuit (IICV2) Block Description
Table 11-3. I-Bus Tap and Prescale Values
IBC2-0 (bin) 000 001 010 011 100 101 110 111 IBC5-3 (bin) 000 001 010 011 100 101 110 111 scl2start (clocks) 2 2 2 6 14 30 62 126 SCL Tap (clocks) 5 6 7 8 9 10 12 15 scl2stop (clocks) 7 7 9 9 17 33 65 129 SDA Tap (clocks) 1 1 2 2 3 3 4 4 scl2tap (clocks) 4 4 6 6 14 30 62 126 tap2tap (clocks) 1 2 4 8 16 32 64 128
Table 11-4. Multiplier Factor
IBC7-6 00 01 10 11 MUL 01 02 04 RESERVED
The number of clocks from the falling edge of SCL to the first tap (Tap[1]) is defined by the values shown in the scl2tap column of Table 11-3, all subsequent tap points are separated by 2IBC5-3 as shown in the tap2tap column in Table 11-3. The SCL Tap is used to generated the SCL period and the SDA Tap is used to determine the delay from the falling edge of SCL to SDA changing, the SDA hold time. IBC7-6 defines the multiplier factor MUL. The values of MUL are shown in the Table 11-4.
MC3S12RG128 Data Sheet, Rev. 1.05 324 Freescale Semiconductor
Chapter 11 Inter-Integrated Circuit (IICV2) Block Description
SCL Divider
SCL
SDA
SDA Hold
SDA
SCL Hold(start)
SCL Hold(stop)
SCL
START condition
STOP condition
Figure 11-5. SCL Divider and SDA Hold
The equation used to generate the divider values from the IBFD bits is: SCL Divider = MUL x {2 x (scl2tap + [(SCL_Tap -1) x tap2tap] + 2)} The SDA hold delay is equal to the CPU clock period multiplied by the SDA Hold value shown in Table 11-5. The equation used to generate the SDA Hold value from the IBFD bits is: SDA Hold = MUL x {scl2tap + [(SDA_Tap - 1) x tap2tap] + 3} The equation for SCL Hold values to generate the start and stop conditions from the IBFD bits is: SCL Hold(start) = MUL x [scl2start + (SCL_Tap - 1) x tap2tap] SCL Hold(stop) = MUL x [scl2stop + (SCL_Tap - 1) x tap2tap]
Table 11-5. IIC Divider and Hold Values (Sheet 1 of 6)
IBC[7:0] (hex) SCL Divider (clocks) SDA Hold (clocks) SCL Hold (start) SCL Hold (stop)
MUL=1
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 325
Chapter 11 Inter-Integrated Circuit (IICV2) Block Description
Table 11-5. IIC Divider and Hold Values (Sheet 2 of 6)
IBC[7:0] (hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C SCL Divider (clocks) 20 22 24 26 28 30 34 40 28 32 36 40 44 48 56 68 48 56 64 72 80 88 104 128 80 96 112 128 144 160 192 240 160 192 224 256 288 320 384 480 320 384 448 512 576 SDA Hold (clocks) 7 7 8 8 9 9 10 10 7 7 9 9 11 11 13 13 9 9 13 13 17 17 21 21 9 9 17 17 25 25 33 33 17 17 33 33 49 49 65 65 33 33 65 65 97 SCL Hold (start) 6 7 8 9 10 11 13 16 10 12 14 16 18 20 24 30 18 22 26 30 34 38 46 58 38 46 54 62 70 78 94 118 78 94 110 126 142 158 190 238 158 190 222 254 286 SCL Hold (stop) 11 12 13 14 15 16 18 21 15 17 19 21 23 25 29 35 25 29 33 37 41 45 53 65 41 49 57 65 73 81 97 121 81 97 113 129 145 161 193 241 161 193 225 257 289
MC3S12RG128 Data Sheet, Rev. 1.05 326 Freescale Semiconductor
Chapter 11 Inter-Integrated Circuit (IICV2) Block Description
Table 11-5. IIC Divider and Hold Values (Sheet 3 of 6)
IBC[7:0] (hex) 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F SCL Divider (clocks) 640 768 960 640 768 896 1024 1152 1280 1536 1920 1280 1536 1792 2048 2304 2560 3072 3840 40 44 48 52 56 60 68 80 56 64 72 80 88 96 112 136 96 112 128 144 160 176 208 256 160 SDA Hold (clocks) 97 129 129 65 65 129 129 193 193 257 257 129 129 257 257 385 385 513 513 14 14 16 16 18 18 20 20 14 14 18 18 22 22 26 26 18 18 26 26 34 34 42 42 18 SCL Hold (start) 318 382 478 318 382 446 510 574 638 766 958 638 766 894 1022 1150 1278 1534 1918 12 14 16 18 20 22 26 32 20 24 28 32 36 40 48 60 36 44 52 60 68 76 92 116 76 SCL Hold (stop) 321 385 481 321 385 449 513 577 641 769 961 641 769 897 1025 1153 1281 1537 1921 22 24 26 28 30 32 36 42 30 34 38 42 46 50 58 70 50 58 66 74 82 90 106 130 82
MUL=2
40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 327
Chapter 11 Inter-Integrated Circuit (IICV2) Block Description
Table 11-5. IIC Divider and Hold Values (Sheet 4 of 6)
IBC[7:0] (hex) 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F SCL Divider (clocks) 192 224 256 288 320 384 480 320 384 448 512 576 640 768 960 640 768 896 1024 1152 1280 1536 1920 1280 1536 1792 2048 2304 2560 3072 3840 2560 3072 3584 4096 4608 5120 6144 7680 80 88 96 104 112 SDA Hold (clocks) 18 34 34 50 50 66 66 34 34 66 66 98 98 130 130 66 66 130 130 194 194 258 258 130 130 258 258 386 386 514 514 258 258 514 514 770 770 1026 1026 28 28 32 32 36 SCL Hold (start) 92 108 124 140 156 188 236 156 188 220 252 284 316 380 476 316 380 444 508 572 636 764 956 636 764 892 1020 1148 1276 1532 1916 1276 1532 1788 2044 2300 2556 3068 3836 24 28 32 36 40 SCL Hold (stop) 98 114 130 146 162 194 242 162 194 226 258 290 322 386 482 322 386 450 514 578 642 770 962 642 770 898 1026 1154 1282 1538 1922 1282 1538 1794 2050 2306 2562 3074 3842 44 48 52 56 60
MUL=4
80 81 82 83 84
MC3S12RG128 Data Sheet, Rev. 1.05 328 Freescale Semiconductor
Chapter 11 Inter-Integrated Circuit (IICV2) Block Description
Table 11-5. IIC Divider and Hold Values (Sheet 5 of 6)
IBC[7:0] (hex) 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 SCL Divider (clocks) 120 136 160 112 128 144 160 176 192 224 272 192 224 256 288 320 352 416 512 320 384 448 512 576 640 768 960 640 768 896 1024 1152 1280 1536 1920 1280 1536 1792 2048 2304 2560 3072 3840 2560 3072 SDA Hold (clocks) 36 40 40 28 28 36 36 44 44 52 52 36 36 52 52 68 68 84 84 36 36 68 68 100 100 132 132 68 68 132 132 196 196 260 260 132 132 260 260 388 388 516 516 260 260 SCL Hold (start) 44 52 64 40 48 56 64 72 80 96 120 72 88 104 120 136 152 184 232 152 184 216 248 280 312 376 472 312 376 440 504 568 632 760 952 632 760 888 1016 1144 1272 1528 1912 1272 1528 SCL Hold (stop) 64 72 84 60 68 76 84 92 100 116 140 100 116 132 148 164 180 212 260 164 196 228 260 292 324 388 484 324 388 452 516 580 644 772 964 644 772 900 1028 1156 1284 1540 1924 1284 1540
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 329
Chapter 11 Inter-Integrated Circuit (IICV2) Block Description
Table 11-5. IIC Divider and Hold Values (Sheet 6 of 6)
IBC[7:0] (hex) B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF SCL Divider (clocks) 3584 4096 4608 5120 6144 7680 5120 6144 7168 8192 9216 10240 12288 15360 SDA Hold (clocks) 516 516 772 772 1028 1028 516 516 1028 1028 1540 1540 2052 2052 SCL Hold (start) 1784 2040 2296 2552 3064 3832 2552 3064 3576 4088 4600 5112 6136 7672 SCL Hold (stop) 1796 2052 2308 2564 3076 3844 2564 3076 3588 4100 4612 5124 6148 7684
11.3.1.3
IIC Control Register (IBCR)
Offset Module Base + 0x0002
7 6 5 4 3 2 1 0
R IBEN W Reset 0 0 0 0 0 IBIE MS/SL Tx/Rx TXAK
0
0 IBSWAI
RSTA
0 0 0
= Unimplemented or Reserved
Figure 11-6. IIC Bus Control Register (IBCR)
Read and write anytime
MC3S12RG128 Data Sheet, Rev. 1.05 330 Freescale Semiconductor
Chapter 11 Inter-Integrated Circuit (IICV2) Block Description
Table 11-6. IBCR Field Descriptions
Field 7 IBEN Description I-Bus Enable -- This bit controls the software reset of the entire IIC bus module. 0 The module is reset and disabled. This is the power-on reset situation. When low the interface is held in reset but registers can be accessed 1 The IIC bus module is enabled.This bit must be set before any other IBCR bits have any effect If the IIC bus module is enabled in the middle of a byte transfer the interface behaves as follows: slave mode ignores the current transfer on the bus and starts operating whenever a subsequent start condition is detected. Master mode will not be aware that the bus is busy, hence if a start cycle is initiated then the current bus cycle may become corrupt. This would ultimately result in either the current bus master or the IIC bus module losing arbitration, after which bus operation would return to normal. I-Bus Interrupt Enable 0 Interrupts from the IIC bus module are disabled. Note that this does not clear any currently pending interrupt condition 1 Interrupts from the IIC bus module are enabled. An IIC bus interrupt occurs provided the IBIF bit in the status register is also set. Master/Slave Mode Select Bit -- Upon reset, this bit is cleared. When this bit is changed from 0 to 1, a START signal is generated on the bus, and the master mode is selected. When this bit is changed from 1 to 0, a STOP signal is generated and the operation mode changes from master to slave.A STOP signal should only be generated if the IBIF flag is set. MS/SL is cleared without generating a STOP signal when the master loses arbitration. 0 Slave Mode 1 Master Mode Transmit/Receive Mode Select Bit -- This bit selects the direction of master and slave transfers. When addressed as a slave this bit should be set by software according to the SRW bit in the status register. In master mode this bit should be set according to the type of transfer required. Therefore, for address cycles, this bit will always be high. 0 Receive 1 Transmit Transmit Acknowledge Enable -- This bit specifies the value driven onto SDA during data acknowledge cycles for both master and slave receivers. The IIC module will always acknowledge address matches, provided it is enabled, regardless of the value of TXAK. Note that values written to this bit are only used when the IIC bus is a receiver, not a transmitter. 0 An acknowledge signal will be sent out to the bus at the 9th clock bit after receiving one byte data 1 No acknowledge signal response is sent (i.e., acknowledge bit = 1) Repeat Start -- Writing a 1 to this bit will generate a repeated START condition on the bus, provided it is the current bus master. This bit will always be read as a low. Attempting a repeated start at the wrong time, if the bus is owned by another master, will result in loss of arbitration. 1 Generate repeat start cycle
6 IBIE
5 MS/SL
4 Tx/Rx
3 TXAK
2 RSTA
1 Reserved -- Bit 1 of the IBCR is reserved for future compatibility. This bit will always read 0. RESERVED 0 IBSWAI I Bus Interface Stop in Wait Mode 0 IIC bus module clock operates normally 1 Halt IIC bus module clock generation in wait mode
Wait mode is entered via execution of a CPU WAI instruction. In the event that the IBSWAI bit is set, all clocks internal to the IIC will be stopped and any transmission currently in progress will halt.If the CPU were woken up by a source other than the IIC module, then clocks would restart and the IIC would resume
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 331
Chapter 11 Inter-Integrated Circuit (IICV2) Block Description
from where was during the previous transmission. It is not possible for the IIC to wake up the CPU when its internal clocks are stopped. If it were the case that the IBSWAI bit was cleared when the WAI instruction was executed, the IIC internal clocks and interface would remain alive, continuing the operation which was currently underway. It is also possible to configure the IIC such that it will wake up the CPU via an interrupt at the conclusion of the current operation. See the discussion on the IBIF and IBIE bits in the IBSR and IBCR, respectively.
11.3.1.4
IIC Status Register (IBSR)
Offset Module Base + 0x0003
7 6 5 4 3 2 1 0
R W Reset
TCF
IAAS
IBB IBAL
0
SRW IBIF
RXAK
1
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 11-7. IIC Bus Status Register (IBSR)
This status register is read-only with exception of bit 1 (IBIF) and bit 4 (IBAL), which are software clearable.
Table 11-7. IBSR Field Descriptions
Field 7 TCF Description Data Transferring Bit -- While one byte of data is being transferred, this bit is cleared. It is set by the falling edge of the 9th clock of a byte transfer. Note that this bit is only valid during or immediately following a transfer to the IIC module or from the IIC module. 0 Transfer in progress 1 Transfer complete Addressed as a Slave Bit -- When its own specific address (I-bus address register) is matched with the calling address, this bit is set.The CPU is interrupted provided the IBIE is set.Then the CPU needs to check the SRW bit and set its Tx/Rx mode accordingly.Writing to the I-bus control register clears this bit. 0 Not addressed 1 Addressed as a slave Bus Busy Bit 0 This bit indicates the status of the bus. When a START signal is detected, the IBB is set. If a STOP signal is detected, IBB is cleared and the bus enters idle state. 1 Bus is busy Arbitration Lost -- The arbitration lost bit (IBAL) is set by hardware when the arbitration procedure is lost. Arbitration is lost in the following circumstances: 1. SDA sampled low when the master drives a high during an address or data transmit cycle. 2. SDA sampled low when the master drives a high during the acknowledge bit of a data receive cycle. 3. A start cycle is attempted when the bus is busy. 4. A repeated start cycle is requested in slave mode. 5. A stop condition is detected when the master did not request it. This bit must be cleared by software, by writing a one to it. A write of 0 has no effect on this bit.
6 IAAS
5 IBB
4 IBAL
3 Reserved -- Bit 3 of IBSR is reserved for future use. A read operation on this bit will return 0. RESERVED
MC3S12RG128 Data Sheet, Rev. 1.05 332 Freescale Semiconductor
Chapter 11 Inter-Integrated Circuit (IICV2) Block Description
Table 11-7. IBSR Field Descriptions (continued)
Field 2 SRW Description Slave Read/Write -- When IAAS is set this bit indicates the value of the R/W command bit of the calling address sent from the master This bit is only valid when the I-bus is in slave mode, a complete address transfer has occurred with an address match and no other transfers have been initiated. Checking this bit, the CPU can select slave transmit/receive mode according to the command of the master. 0 Slave receive, master writing to slave 1 Slave transmit, master reading from slave I-Bus Interrupt -- The IBIF bit is set when one of the following conditions occurs: -- Arbitration lost (IBAL bit set) -- Byte transfer complete (TCF bit set) -- Addressed as slave (IAAS bit set) It will cause a processor interrupt request if the IBIE bit is set. This bit must be cleared by software, writing a one to it. A write of 0 has no effect on this bit. Received Acknowledge -- The value of SDA during the acknowledge bit of a bus cycle. If the received acknowledge bit (RXAK) is low, it indicates an acknowledge signal has been received after the completion of 8 bits data transmission on the bus. If RXAK is high, it means no acknowledge signal is detected at the 9th clock. 0 Acknowledge received 1 No acknowledge received
1 IBIF
0 RXAK
11.3.1.5
IIC Data I/O Register (IBDR)
Offset Module Base + 0x0004
7 6 5 4 3 2 1 0
R D7 W Reset 0 0 0 0 0 0 0 0 D6 D5 D4 D3 D2 D1 D0
Figure 11-8. IIC Bus Data I/O Register (IBDR)
In master transmit mode, when data is written to the IBDR a data transfer is initiated. The most significant bit is sent first. In master receive mode, reading this register initiates next byte data receiving. In slave mode, the same functions are available after an address match has occurred.Note that the Tx/Rx bit in the IBCR must correctly reflect the desired direction of transfer in master and slave modes for the transmission to begin. For instance, if the IIC is configured for master transmit but a master receive is desired, then reading the IBDR will not initiate the receive. Reading the IBDR will return the last byte received while the IIC is configured in either master receive or slave receive modes. The IBDR does not reflect every byte that is transmitted on the IIC bus, nor can software verify that a byte has been written to the IBDR correctly by reading it back. In master transmit mode, the first byte of data written to IBDR following assertion of MS/SL is used for the address transfer and should com.prise of the calling address (in position D7:D1) concatenated with the required R/W bit (in position D0).
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 333
Chapter 11 Inter-Integrated Circuit (IICV2) Block Description
11.4
Functional Description
This section provides a complete functional description of the IICV2.
11.4.1
I-Bus Protocol
The IIC bus system uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. All devices connected to it must have open drain or open collector outputs. Logic AND function is exercised on both lines with external pull-up resistors. The value of these resistors is system dependent. Normally, a standard communication is composed of four parts: START signal, slave address transmission, data transfer and STOP signal. They are described briefly in the following sections and illustrated in Figure 11-9.
MSB SCL 1 2 3 4 5 6 7 LSB 8 9 MSB 1 2 3 4 5 6 7 LSB 8 9
SDA
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
XXX
D7
D6
D5
D4
D3
D2
D1
D0
Start Signal
Calling Address
Read/ Write
Ack Bit
Data Byte
No Stop Ack Signal Bit LSB
MSB SCL 1 2 3 4 5 6 7
LSB 8 9
MSB 1 2 3 4 5 6 7
8
9
SDA
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
XX
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
Start Signal
Calling Address
Read/ Write
Ack Bit
Repeated Start Signal
New Calling Address
Read/ Write
No Stop Ack Signal Bit
Figure 11-9. IIC-Bus Transmission Signals
11.4.1.1
START Signal
When the bus is free, i.e. no master device is engaging the bus (both SCL and SDA lines are at logical high), a master may initiate communication by sending a START signal.As shown in Figure 11-9, a START signal is defined as a high-to-low transition of SDA while SCL is high. This signal denotes the beginning of a new data transfer (each data transfer may contain several bytes of data) and brings all slaves out of their idle states.
MC3S12RG128 Data Sheet, Rev. 1.05 334 Freescale Semiconductor
Chapter 11 Inter-Integrated Circuit (IICV2) Block Description
SDA
SCL
START Condition
STOP Condition
Figure 11-10. Start and Stop Conditions
11.4.1.2
Slave Address Transmission
The first byte of data transfer immediately after the START signal is the slave address transmitted by the master. This is a seven-bit calling address followed by a R/W bit. The R/W bit tells the slave the desired direction of data transfer. 1 = Read transfer, the slave transmits data to the master. 0 = Write transfer, the master transmits data to the slave. Only the slave with a calling address that matches the one transmitted by the master will respond by sending back an acknowledge bit. This is done by pulling the SDA low at the 9th clock (see Figure 11-9). No two slaves in the system may have the same address. If the IIC bus is master, it must not transmit an address that is equal to its own slave address. The IIC bus cannot be master and slave at the same time.However, if arbitration is lost during an address cycle the IIC bus will revert to slave mode and operate correctly even if it is being addressed by another master.
11.4.1.3
Data Transfer
As soon as successful slave addressing is achieved, the data transfer can proceed byte-by-byte in a direction specified by the R/W bit sent by the calling master All transfers that come after an address cycle are referred to as data transfers, even if they carry sub-address information for the slave device. Each data byte is 8 bits long. Data may be changed only while SCL is low and must be held stable while SCL is high as shown in Figure 11-9. There is one clock pulse on SCL for each data bit, the MSB being transferred first. Each data byte has to be followed by an acknowledge bit, which is signalled from the receiving device by pulling the SDA low at the ninth clock. So one complete data byte transfer needs nine clock pulses. If the slave receiver does not acknowledge the master, the SDA line must be left high by the slave. The master can then generate a stop signal to abort the data transfer or a start signal (repeated start) to commence a new calling.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 335
Chapter 11 Inter-Integrated Circuit (IICV2) Block Description
If the master receiver does not acknowledge the slave transmitter after a byte transmission, it means 'end of data' to the slave, so the slave releases the SDA line for the master to generate STOP or START signal.
11.4.1.4
STOP Signal
The master can terminate the communication by generating a STOP signal to free the bus. However, the master may generate a START signal followed by a calling command without generating a STOP signal first. This is called repeated START. A STOP signal is defined as a low-to-high transition of SDA while SCL at logical 1 (see Figure 11-9). The master can generate a STOP even if the slave has generated an acknowledge at which point the slave must release the bus.
11.4.1.5
Repeated START Signal
As shown in Figure 11-9, a repeated START signal is a START signal generated without first generating a STOP signal to terminate the communication. This is used by the master to communicate with another slave or with the same slave in different mode (transmit/receive mode) without releasing the bus.
11.4.1.6
Arbitration Procedure
The Inter-IC bus is a true multi-master bus that allows more than one master to be connected on it. If two or more masters try to control the bus at the same time, a clock synchronization procedure determines the bus clock, for which the low period is equal to the longest clock low period and the high is equal to the shortest one among the masters. The relative priority of the contending masters is determined by a data arbitration procedure, a bus master loses arbitration if it transmits logic 1 while another master transmits logic 0. The losing masters immediately switch over to slave receive mode and stop driving SDA output. In this case the transition from master to slave mode does not generate a STOP condition. Meanwhile, a status bit is set by hardware to indicate loss of arbitration.
11.4.1.7
Clock Synchronization
Because wire-AND logic is performed on SCL line, a high-to-low transition on SCL line affects all the devices connected on the bus. The devices start counting their low period and as soon as a device's clock has gone low, it holds the SCL line low until the clock high state is reached.However, the change of low to high in this device clock may not change the state of the SCL line if another device clock is within its low period. Therefore, synchronized clock SCL is held low by the device with the longest low period. Devices with shorter low periods enter a high wait state during this time (see Figure 11-10). When all devices concerned have counted off their low period, the synchronized clock SCL line is released and pulled high. There is then no difference between the device clocks and the state of the SCL line and all the devices start counting their high periods.The first device to complete its high period pulls the SCL line low again.
MC3S12RG128 Data Sheet, Rev. 1.05 336 Freescale Semiconductor
Chapter 11 Inter-Integrated Circuit (IICV2) Block Description Start Counting High Period
WAIT SCL1
SCL2
SCL
Internal Counter Reset
Figure 11-11. IIC-Bus Clock Synchronization
11.4.1.8
Handshaking
The clock synchronization mechanism can be used as a handshake in data transfer. Slave devices may hold the SCL low after completion of one byte transfer (9 bits). In such case, it halts the bus clock and forces the master clock into wait states until the slave releases the SCL line.
11.4.1.9
Clock Stretching
The clock synchronization mechanism can be used by slaves to slow down the bit rate of a transfer. After the master has driven SCL low the slave can drive SCL low for the required period and then release it.If the slave SCL low period is greater than the master SCL low period then the resulting SCL bus signal low period is stretched.
11.4.2
Operation in Run Mode
This is the basic mode of operation.
11.4.3
Operation in Wait Mode
IIC operation in wait mode can be configured. Depending on the state of internal bits, the IIC can operate normally when the CPU is in wait mode or the IIC clock generation can be turned off and the IIC module enters a power conservation state during wait mode. In the later case, any transmission or reception in progress stops at wait mode entry.
11.4.4
Operation in Stop Mode
The IIC is inactive in stop mode for reduced power consumption. The STOP instruction does not affect IIC register states.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 337
Chapter 11 Inter-Integrated Circuit (IICV2) Block Description
11.5
Resets
The reset state of each individual bit is listed in Section 11.3, "Memory Map and Register Definition," which details the registers and their bit-fields.
11.6
Interrupts
Table 11-8. Interrupt Summary
Interrupt IIC Interrupt Offset -- Vector -- Priority -- Source Description
IICV2 uses only one interrupt vector.
IBAL, TCF, IAAS When either of IBAL, TCF or IAAS bits is set bits in IBSR may cause an interrupt based on arbitration register lost, transfer complete or address detect conditions
Internally there are three types of interrupts in IIC. The interrupt service routine can determine the interrupt type by reading the status register. IIC Interrupt can be generated on 1. Arbitration lost condition (IBAL bit set) 2. Byte transfer condition (TCF bit set) 3. Address detect condition (IAAS bit set) The IIC interrupt is enabled by the IBIE bit in the IIC control register. It must be cleared by writing 0 to the IBF bit in the interrupt service routine.
11.7
11.7.1
Initialization/Application Information
IIC Programming Examples
Initialization Sequence
11.7.1.1
Reset will put the IIC bus control register to its default status. Before the interface can be used to transfer serial data, an initialization procedure must be carried out, as follows: 1. Update the frequency divider register (IBFD) and select the required division ratio to obtain SCL frequency from system clock. 2. Update the IIC bus address register (IBAD) to define its slave address. 3. Set the IBEN bit of the IIC bus control register (IBCR) to enable the IIC interface system. 4. Modify the bits of the IIC bus control register (IBCR) to select master/slave mode, transmit/receive mode and interrupt enable or not.
MC3S12RG128 Data Sheet, Rev. 1.05 338 Freescale Semiconductor
Chapter 11 Inter-Integrated Circuit (IICV2) Block Description
11.7.1.2
Generation of START
After completion of the initialization procedure, serial data can be transmitted by selecting the 'master transmitter' mode. If the device is connected to a multi-master bus system, the state of the IIC bus busy bit (IBB) must be tested to check whether the serial bus is free. If the bus is free (IBB=0), the start condition and the first byte (the slave address) can be sent. The data written to the data register comprises the slave calling address and the LSB set to indicate the direction of transfer required from the slave. The bus free time (i.e., the time between a STOP condition and the following START condition) is built into the hardware that generates the START cycle. Depending on the relative frequencies of the system clock and the SCL period it may be necessary to wait until the IIC is busy after writing the calling address to the IBDR before proceeding with the following instructions. This is illustrated in the following example. An example of a program which generates the START signal and transmits the first byte of data (slave address) is shown below:
CHFLAG TXSTART IBFREE BRSET BSET MOVB BRCLR IBSR,#$20,* IBCR,#$30 CALLING,IBDR IBSR,#$20,* ;WAIT FOR IBB FLAG TO CLEAR ;SET TRANSMIT AND MASTER MODE;i.e. GENERATE START CONDITION ;TRANSMIT THE CALLING ADDRESS, D0=R/W ;WAIT FOR IBB FLAG TO SET
11.7.1.3
Post-Transfer Software Response
Transmission or reception of a byte will set the data transferring bit (TCF) to 1, which indicates one byte communication is finished. The IIC bus interrupt bit (IBIF) is set also; an interrupt will be generated if the interrupt function is enabled during initialization by setting the IBIE bit. Software must clear the IBIF bit in the interrupt routine first. The TCF bit will be cleared by reading from the IIC bus data I/O register (IBDR) in receive mode or writing to IBDR in transmit mode. Software may service the IIC I/O in the main program by monitoring the IBIF bit if the interrupt function is disabled. Note that polling should monitor the IBIF bit rather than the TCF bit because their operation is different when arbitration is lost. Note that when an interrupt occurs at the end of the address cycle the master will always be in transmit mode, i.e. the address is transmitted. If master receive mode is required, indicated by R/W bit in IBDR, then the Tx/Rx bit should be toggled at this stage. During slave mode address cycles (IAAS=1), the SRW bit in the status register is read to determine the direction of the subsequent transfer and the Tx/Rx bit is programmed accordingly. For slave mode data cycles (IAAS=0) the SRW bit is not valid, the Tx/Rx bit in the control register should be read to determine the direction of the current transfer. The following is an example of a software response by a 'master transmitter' in the interrupt routine.
ISR BCLR BRCLR BRCLR BRSET MOVB IBSR,#$02 IBCR,#$20,SLAVE IBCR,#$10,RECEIVE IBSR,#$01,END DATABUF,IBDR ;CLEAR THE IBIF FLAG ;BRANCH IF IN SLAVE MODE ;BRANCH IF IN RECEIVE MODE ;IF NO ACK, END OF TRANSMISSION ;TRANSMIT NEXT BYTE OF DATA
TRANSMIT
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 339
Chapter 11 Inter-Integrated Circuit (IICV2) Block Description
11.7.1.4
Generation of STOP
A data transfer ends with a STOP signal generated by the 'master' device. A master transmitter can simply generate a STOP signal after all the data has been transmitted. The following is an example showing how a stop condition is generated by a master transmitter.
MASTX TST BEQ BRSET MOVB DEC BRA BCLR RTI TXCNT END IBSR,#$01,END DATABUF,IBDR TXCNT EMASTX IBCR,#$20 ;GET VALUE FROM THE TRANSMITING COUNTER ;END IF NO MORE DATA ;END IF NO ACK ;TRANSMIT NEXT BYTE OF DATA ;DECREASE THE TXCNT ;EXIT ;GENERATE A STOP CONDITION ;RETURN FROM INTERRUPT
END EMASTX
If a master receiver wants to terminate a data transfer, it must inform the slave transmitter by not acknowledging the last byte of data which can be done by setting the transmit acknowledge bit (TXAK) before reading the 2nd last byte of data. Before reading the last byte of data, a STOP signal must be generated first. The following is an example showing how a STOP signal is generated by a master receiver.
MASR DEC BEQ MOVB DEC BNE BSET BRA BCLR MOVB RTI RXCNT ENMASR RXCNT,D1 D1 NXMAR IBCR,#$08 NXMAR IBCR,#$20 IBDR,RXBUF ;DECREASE THE RXCNT ;LAST BYTE TO BE READ ;CHECK SECOND LAST BYTE ;TO BE READ ;NOT LAST OR SECOND LAST ;SECOND LAST, DISABLE ACK ;TRANSMITTING ;LAST ONE, GENERATE `STOP' SIGNAL ;READ DATA AND STORE
LAMAR
ENMASR NXMAR
11.7.1.5
Generation of Repeated START
At the end of data transfer, if the master continues to want to communicate on the bus, it can generate another START signal followed by another slave address without first generating a STOP signal. A program example is as shown.
RESTART BSET MOVB IBCR,#$04 CALLING,IBDR ;ANOTHER START (RESTART) ;TRANSMIT THE CALLING ADDRESS;D0=R/W
11.7.1.6
Slave Mode
In the slave interrupt service routine, the module addressed as slave bit (IAAS) should be tested to check if a calling of its own address has just been received. If IAAS is set, software should set the transmit/receive mode select bit (Tx/Rx bit of IBCR) according to the R/W command bit (SRW). Writing to the IBCR clears the IAAS automatically. Note that the only time IAAS is read as set is from the interrupt at the end of the address cycle where an address match occurred, interrupts resulting from subsequent data transfers will have IAAS cleared. A data transfer may now be initiated by writing information to IBDR, for slave transmits, or dummy reading from IBDR, in slave receive mode. The slave will drive SCL low in-between byte transfers, SCL is released when the IBDR is accessed in the required mode.
MC3S12RG128 Data Sheet, Rev. 1.05 340 Freescale Semiconductor
Chapter 11 Inter-Integrated Circuit (IICV2) Block Description
In slave transmitter routine, the received acknowledge bit (RXAK) must be tested before transmitting the next byte of data. Setting RXAK means an 'end of data' signal from the master receiver, after which it must be switched from transmitter mode to receiver mode by software. A dummy read then releases the SCL line so that the master can generate a STOP signal.
11.7.1.7
Arbitration Lost
If several masters try to engage the bus simultaneously, only one master wins and the others lose arbitration. The devices which lost arbitration are immediately switched to slave receive mode by the hardware. Their data output to the SDA line is stopped, but SCL continues to be generated until the end of the byte during which arbitration was lost. An interrupt occurs at the falling edge of the ninth clock of this transfer with IBAL=1 and MS/SL=0. If one master attempts to start transmission while the bus is being engaged by another master, the hardware will inhibit the transmission; switch the MS/SL bit from 1 to 0 without generating STOP condition; generate an interrupt to CPU and set the IBAL to indicate that the attempt to engage the bus is failed. When considering these cases, the slave service routine should test the IBAL first and the software should clear the IBAL bit if it is set.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 341
Chapter 11 Inter-Integrated Circuit (IICV2) Block Description
Clear IBIF
Y
Master Mode ?
N
TX
Tx/Rx ?
RX
Y
Arbitration Lost ? N
Last Byte Transmitted ? N
Y
Clear IBAL
RXAK=0 ? Y End Of Addr Cycle (Master Rx) ? N
N
Last Byte To Be Read ? N
Y
N
IAAS=1 ? Y
Y
IAAS=1 ? N
Address Transfer Y Y 2nd Last Byte To Be Read ? N Y (Read) SRW=1 ? N (Write) Y
Data Transfer TX/RX ? TX ACK From Receiver ? N Read Data From IBDR And Store RX
Write Next Byte To IBDR
Set TXAK =1
Generate Stop Signal
Set TX Mode
Write Data To IBDR
Tx Next Byte
Switch To Rx Mode
Set RX Mode
Switch To Rx Mode
Dummy Read From IBDR
Generate Stop Signal
Read Data From IBDR And Store
Dummy Read From IBDR
Dummy Read From IBDR
RTI
Figure 11-12. Flow-Chart of Typical IIC Interrupt Routine
MC3S12RG128 Data Sheet, Rev. 1.05 342 Freescale Semiconductor
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
12.1 Introduction
Freescale's scalable controller area network (MSCANV2) definition is based on the MSCAN12 definition, which is the specific implementation of the MSCAN concept targeted for the M68HC12 microcontroller family. The module is a communication controller implementing the CAN 2.0A/B protocol as defined in the Bosch specification dated September 1991. For users to fully understand the MSCAN specification, it is recommended that the Bosch specification be read first to familiarize the reader with the terms and concepts contained within this document. Though not exclusively intended for automotive applications, CAN protocol is designed to meet the specific requirements of a vehicle serial data bus: real-time processing, reliable operation in the EMI environment of a vehicle, cost-effectiveness, and required bandwidth. MSCAN uses an advanced buffer arrangement resulting in predictable real-time behavior and simplified application software.
12.1.1
Glossary
ACK: Acknowledge of CAN message CAN: Controller Area Network CRC: Cyclic Redundancy Code EOF: End of Frame FIFO: First-In-First-Out Memory IFS: Inter-Frame Sequence SOF: Start of Frame CPU bus: CPU related read/write data bus CAN bus: CAN protocol related serial bus oscillator clock: Direct clock from external oscillator bus clock: CPU bus realated clock CAN clock: CAN protocol related clock
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 343
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
12.1.2
Block Diagram MSCAN
Oscillator Clock Bus Clock
CANCLK
MUX
Presc.
Tq Clk
Receive/ Transmit Engine
RXCAN TXCAN
Transmit Interrupt Req. Receive Interrupt Req. Errors Interrupt Req. Wake-Up Interrupt Req.
Control and Status
Message Filtering and Buffering
Configuration Registers
Wake-Up
Low Pass Filter
Figure 12-1. MSCAN Block Diagram
12.1.3
Features
The basic features of the MSCAN are as follows: * Implementation of the CAN protocol -- Version 2.0A/B -- Standard and extended data frames -- Zero to eight bytes data length -- Programmable bit rate up to 1 Mbps1 -- Support for remote frames * Five receive buffers with FIFO storage scheme * Three transmit buffers with internal prioritization using a "local priority" concept * Flexible maskable identifier filter supports two full-size (32-bit) extended identifier filters, or four 16-bit filters, or eight 8-bit filters * Programmable wakeup functionality with integrated low-pass filter * Programmable loopback mode supports self-test operation * Programmable listen-only mode for monitoring of CAN bus * Separate signalling and interrupt capabilities for all CAN receiver and transmitter error states (warning, error passive, bus-off) * Programmable MSCAN clock source either bus clock or oscillator clock * Internal timer for time-stamping of received and transmitted messages * Three low-power modes: sleep, power down, and MSCAN enable
1. Depending on the actual bit timing and the clock jitter of the PLL. MC3S12RG128 Data Sheet, Rev. 1.05 344 Freescale Semiconductor
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
*
Global initialization of configuration registers
12.1.4
Modes of Operation
The following modes of operation are specific to the MSCAN. See Section 12.4, "Functional Description," for details. * Listen-Only Mode * MSCAN Sleep Mode * MSCAN Initialization Mode * MSCAN Power Down Mode
12.2
External Signal Description
The MSCAN uses two external pins:
12.2.1
RXCAN -- CAN Receiver Input Pin
RXCAN is the MSCAN receiver input pin.
12.2.2
TXCAN -- CAN Transmitter Output Pin
TXCAN is the MSCAN transmitter output pin. The TXCAN output pin represents the logic level on the CAN bus: 0 = Dominant state 1 = Recessive state
12.2.3
CAN System
A typical CAN system with MSCAN is shown in Figure 12-2. Each CAN station is connected physically to the CAN bus lines through a transceiver device. The transceiver is capable of driving the large current needed for the CAN bus and has current protection against defective CAN or defective stations.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 345
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
CAN node 1 MCU CAN Controller (MSCAN)
CAN node 2
CAN node n
TXCAN
RXCAN
Transceiver CAN_H CAN_L CAN Bus
Figure 12-2. CAN System
12.3
Memory Map and Register Definition
This section provides a detailed description of all registers accessible in the MSCAN.
12.3.1
Module Memory Map
Figure 12-3 gives an overview on all registers and their individual bits in the MSCAN memory map. The register address results from the addition of base address and address offset. The base address is determined at the MCU level and can be found in the MCU memory map description. The address offset is defined at the module level. The MSCAN occupies 64 bytes in the memory space. The base address of the MSCAN module is determined at the MCU level when the MCU is defined. The register decode map is fixed and begins at the first address of the module address offset. The detailed register descriptions follow in the order they appear in the register map.
MC3S12RG128 Data Sheet, Rev. 1.05 346 Freescale Semiconductor
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
Register Name 0x0000 CANCTL0 0x0001 CANCTL1 0x0002 CANBTR0 0x0003 CANBTR1 0x0004 CANRFLG 0x0005 CANRIER 0x0006 CANTFLG 0x0007 CANTIER 0x0008 CANTARQ 0x0009 CANTAAK 0x000A CANTBSEL 0x000B CANIDAC 0x000C-0x000D Reserved 0x000E CANRXERR 0x000F CANTXERR R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W
Bit 7
6 RXACT
5
4 SYNCH
3
2
1
Bit 0
RXFRM
CSWAI
TIME
WUPE
SLPRQ SLPAK
INITRQ INITAK
CANE
CLKSRC
LOOPB
LISTEN
WUPM
SJW1
SJW0
BRP5
BRP4
BRP3
BRP2
BRP1
BRP0
SAMP
TSEG22
TSEG21 RSTAT1
TSEG20 RSTAT0
TSEG13 TSTAT1
TSEG12 TSTAT0
TSEG11
TSEG10
WUPIF
CSCIF
OVRIF
RXF
WUPIE 0
CSCIE 0
RSTATE1 0
RSTATE0 0
TSTATE1 0
TSTATE0
OVRIE
RXFIE
TXE2
TXE1
TXE0
0
0
0
0
0
TXEIE2
TXEIE1
TXEIE0
0
0
0
0
0
ABTRQ2 ABTAK2
ABTRQ1 ABTAK1
ABTRQ0 ABTAK0
0
0
0
0
0
0
0
0
0
0
TX2 IDHIT2
TX1 IDHIT1
TX0 IDHIT0
0
0
IDAM1 0
IDAM0 0
0
0
0
0
0
0
0
RXERR7
RXERR6
RXERR5
RXERR4
RXERR3
RXERR2
RXERR1
RXERR0
TXERR7
TXERR6
TXERR5
TXERR4
TXERR3
TXERR2
TXERR1
TXERR0
= Unimplemented or Reserved
u = Unaffected
Figure 12-3. MSCAN Register Summary
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 347
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
Register Name 0x0010-0x0013 CANIDAR0-3 0x0014-0x0017 CANIDMRx 0x0018-0x001B CANIDAR4-7 0x001C-0x001F CANIDMR4-7 0x0020-0x002F CANRXFG 0x0030-0x003F CANTXFG R W R W R W R W R W R W
Bit 7
6
5
4
3
2
1
Bit 0
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
See Section 12.3.3, "Programmer's Model of Message Storage"
See Section 12.3.3, "Programmer's Model of Message Storage" = Unimplemented or Reserved u = Unaffected
Figure 12-3. MSCAN Register Summary (continued)
12.3.2
Register Descriptions
This section describes in detail all the registers and register bits in the MSCAN module. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order. All bits of all registers in this module are completely synchronous to internal clocks during a register read.
12.3.2.1
MSCAN Control Register 0 (CANCTL0)
The CANCTL0 register provides various control bits of the MSCAN module as described below.
Module Base + 0x0000
7 6 5 4 3 2 1 0
R RXFRM W Reset: 0
RXACT CSWAI 0 = Unimplemented 0
SYNCH TIME 0 0 WUPE 0 SLPRQ 0 INITRQ 1
Figure 12-4. MSCAN Control Register 0 (CANCTL0)
MC3S12RG128 Data Sheet, Rev. 1.05 348 Freescale Semiconductor
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
NOTE The CANCTL0 register, except WUPE, INITRQ, and SLPRQ, is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is writable again as soon as the initialization mode is exited (INITRQ = 0 and INITAK = 0). Read: Anytime Write: Anytime when out of initialization mode; exceptions are read-only RXACT and SYNCH, RXFRM (which is set by the module only), and INITRQ (which is also writable in initialization mode).
Table 12-1. CANCTL0 Register Field Descriptions
Field 7 RXFRM1 Description Received Frame Flag -- This bit is read and clear only. It is set when a receiver has received a valid message correctly, independently of the filter configuration. After it is set, it remains set until cleared by software or reset. Clearing is done by writing a 1. Writing a 0 is ignored. This bit is not valid in loopback mode. 0 No valid message was received since last clearing this flag 1 A valid message was received since last clearing of this flag Receiver Active Status -- This read-only flag indicates the MSCAN is receiving a message. The flag is controlled by the receiver front end. This bit is not valid in loopback mode. 0 MSCAN is transmitting or idle2 1 MSCAN is receiving a message (including when arbitration is lost)2 CAN Stops in Wait Mode -- Enabling this bit allows for lower power consumption in wait mode by disabling all the clocks at the CPU bus interface to the MSCAN module. 0 The module is not affected during wait mode 1 The module ceases to be clocked during wait mode Synchronized Status -- This read-only flag indicates whether the MSCAN is synchronized to the CAN bus and able to participate in the communication process. It is set and cleared by the MSCAN. 0 MSCAN is not synchronized to the CAN bus 1 MSCAN is synchronized to the CAN bus Timer Enable -- This bit activates an internal 16-bit wide free running timer which is clocked by the bit clock rate. If the timer is enabled, a 16-bit time stamp will be assigned to each transmitted/received message within the active TX/RX buffer. Right after the EOF of a valid message on the CAN bus, the time stamp is written to the highest bytes (0x000E, 0x000F) in the appropriate buffer (see Section 12.3.3, "Programmer's Model of Message Storage"). The internal timer is reset (all bits set to 0) when disabled. This bit is held low in initialization mode. 0 Disable internal MSCAN timer 1 Enable internal MSCAN timer Wake-Up Enable -- This configuration bit allows the MSCAN to restart from sleep mode when traffic on CAN is detected (see Section 12.4.5.4, "MSCAN Sleep Mode"). 0 Wake-up disabled -- The MSCAN ignores traffic on CAN 1 Wake-up enabled -- The MSCAN is able to restart
6 RXACT
5 CSWAI3
4 SYNCH
3 TIME
2 WUPE4
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 349
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
Table 12-1. CANCTL0 Register Field Descriptions (continued)
Field 1 SLPRQ5 Description Sleep Mode Request -- This bit requests the MSCAN to enter sleep mode, which is an internal power saving mode (see Section 12.4.5.4, "MSCAN Sleep Mode"). The sleep mode request is serviced when the CAN bus is idle, i.e., the module is not receiving a message and all transmit buffers are empty. The module indicates entry to sleep mode by setting SLPAK = 1 (see Section 12.3.2.2, "MSCAN Control Register 1 (CANCTL1)"). SLPRQ cannot be set while the WUPIF flag is set (see Section 12.3.2.5, "MSCAN Receiver Flag Register (CANRFLG)"). Sleep mode will be active until SLPRQ is cleared by the CPU or, depending on the setting of WUPE, the MSCAN detects activity on the CAN bus and clears SLPRQ itself. 0 Running -- The MSCAN functions normally 1 Sleep mode request -- The MSCAN enters sleep mode when CAN bus idle Initialization Mode Request -- When this bit is set by the CPU, the MSCAN skips to initialization mode (see Section 12.4.5.5, "MSCAN Initialization Mode"). Any ongoing transmission or reception is aborted and synchronization to the CAN bus is lost. The module indicates entry to initialization mode by setting INITAK = 1 (Section 12.3.2.2, "MSCAN Control Register 1 (CANCTL1)"). The following registers enter their hard reset state and restore their default values: CANCTL08, CANRFLG9, CANRIER10, CANTFLG, CANTIER, CANTARQ, CANTAAK, and CANTBSEL. The registers CANCTL1, CANBTR0, CANBTR1, CANIDAC, CANIDAR0-7, and CANIDMR0-7 can only be written by the CPU when the MSCAN is in initialization mode (INITRQ = 1 and INITAK = 1). The values of the error counters are not affected by initialization mode. When this bit is cleared by the CPU, the MSCAN restarts and then tries to synchronize to the CAN bus. If the MSCAN is not in bus-off state, it synchronizes after 11 consecutive recessive bits on the CAN bus; if the MSCAN is in bus-off state, it continues to wait for 128 occurrences of 11 consecutive recessive bits. Writing to other bits in CANCTL0, CANRFLG, CANRIER, CANTFLG, or CANTIER must be done only after initialization mode is exited, which is INITRQ = 0 and INITAK = 0. 0 Normal operation 1 MSCAN in initialization mode
0 INITRQ6,7
1 2
The MSCAN must be in normal mode for this bit to become set. See the Bosch CAN 2.0A/B specification for a detailed definition of transmitter and receiver states. 3 In order to protect from accidentally violating the CAN protocol, the TXCAN pin is immediately forced to a recessive state when the CPU enters wait (CSWAI = 1) or stop mode (see Section 12.4.5.2, "Operation in Wait Mode" and Section 12.4.5.3, "Operation in Stop Mode"). 4 The CPU has to make sure that the WUPE register and the WUPIE wake-up interrupt enable register (see Section 12.3.2.6, "MSCAN Receiver Interrupt Enable Register (CANRIER)) is enabled, if the recovery mechanism from stop or wait is required. 5 The CPU cannot clear SLPRQ before the MSCAN has entered sleep mode (SLPRQ = 1 and SLPAK = 1). 6 The CPU cannot clear INITRQ before the MSCAN has entered initialization mode (INITRQ = 1 and INITAK = 1). 7 In order to protect from accidentally violating the CAN protocol, the TXCAN pin is immediately forced to a recessive state when the initialization mode is requested by the CPU. Thus, the recommended procedure is to bring the MSCAN into sleep mode (SLPRQ = 1 and SLPAK = 1) before requesting initialization mode. 8 Not including WUPE, INITRQ, and SLPRQ. 9 TSTAT1 and TSTAT0 are not affected by initialization mode. 10 RSTAT1 and RSTAT0 are not affected by initialization mode.
12.3.2.2
MSCAN Control Register 1 (CANCTL1)
The CANCTL1 register provides various control bits and handshake status information of the MSCAN module as described below.
MC3S12RG128 Data Sheet, Rev. 1.05 350 Freescale Semiconductor
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
Module Base + 0x0001
7 6 5 4 3 2 1 0
R CANE W Reset: 0 0 0 1 0 0 CLKSRC LOOPB LISTEN WUPM
SLPAK
INITAK
0
1
= Unimplemented
Figure 12-5. MSCAN Control Register 1 (CANCTL1)
Read: Anytime Write: Anytime when INITRQ = 1 and INITAK = 1, except CANE which is write once in normal and anytime in special system operation modes when the MSCAN is in initialization mode (INITRQ = 1 and INITAK = 1).
Table 12-2. CANCTL1 Register Field Descriptions
Field 7 CANE 6 CLKSRC MSCAN Enable 0 MSCAN module is disabled 1 MSCAN module is enabled MSCAN Clock Source -- This bit defines the clock source for the MSCAN module (only for systems with a clock generation module; Section 12.4.3.2, "Clock System," and Section Figure 12-42., "MSCAN Clocking Scheme,"). 0 MSCAN clock source is the oscillator clock 1 MSCAN clock source is the bus clock Loopback Self Test Mode -- When this bit is set, the MSCAN performs an internal loopback which can be used for self test operation. The bit stream output of the transmitter is fed back to the receiver internally. The RXCAN input pin is ignored and the TXCAN output goes to the recessive state (logic 1). The MSCAN behaves as it does normally when transmitting and treats its own transmitted message as a message received from a remote node. In this state, the MSCAN ignores the bit sent during the ACK slot in the CAN frame acknowledge field to ensure proper reception of its own message. Both transmit and receive interrupts are generated. 0 Loopback self test disabled 1 Loopback self test enabled Listen Only Mode -- This bit configures the MSCAN as a CAN bus monitor. When LISTEN is set, all valid CAN messages with matching ID are received, but no acknowledgement or error frames are sent out (see Section 12.4.4.4, "Listen-Only Mode"). In addition, the error counters are frozen. Listen only mode supports applications which require "hot plugging" or throughput analysis. The MSCAN is unable to transmit any messages when listen only mode is active. 0 Normal operation 1 Listen only mode activated Wake-Up Mode -- If WUPE in CANCTL0 is enabled, this bit defines whether the integrated low-pass filter is applied to protect the MSCAN from spurious wake-up (see Section 12.4.5.4, "MSCAN Sleep Mode"). 0 MSCAN wakes up on any dominant level on the CAN bus 1 MSCAN wakes up only in case of a dominant pulse on the CAN bus that has a length of Twup Description
5 LOOPB
4 LISTEN
2 WUPM
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 351
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
Table 12-2. CANCTL1 Register Field Descriptions (continued)
Field 1 SLPAK Description Sleep Mode Acknowledge -- This flag indicates whether the MSCAN module has entered sleep mode (see Section 12.4.5.4, "MSCAN Sleep Mode"). It is used as a handshake flag for the SLPRQ sleep mode request. Sleep mode is active when SLPRQ = 1 and SLPAK = 1. Depending on the setting of WUPE, the MSCAN will clear the flag if it detects activity on the CAN bus while in sleep mode. 0 Running -- The MSCAN operates normally 1 Sleep mode active -- The MSCAN has entered sleep mode Initialization Mode Acknowledge -- This flag indicates whether the MSCAN module is in initialization mode (see Section 12.4.5.5, "MSCAN Initialization Mode"). It is used as a handshake flag for the INITRQ initialization mode request. Initialization mode is active when INITRQ = 1 and INITAK = 1. The registers CANCTL1, CANBTR0, CANBTR1, CANIDAC, CANIDAR0-CANIDAR7, and CANIDMR0-CANIDMR7 can be written only by the CPU when the MSCAN is in initialization mode. 0 Running -- The MSCAN operates normally 1 Initialization mode active -- The MSCAN has entered initialization mode
0 INITAK
MC3S12RG128 Data Sheet, Rev. 1.05 352 Freescale Semiconductor
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
12.3.2.3
MSCAN Bus Timing Register 0 (CANBTR0)
The CANBTR0 register configures various CAN bus timing parameters of the MSCAN module.
Module Base + 0x0002
7 6 5 4 3 2 1 0
R SJW1 W Reset: 0 0 0 0 0 0 0 0 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0
Figure 12-6. MSCAN Bus Timing Register 0 (CANBTR0)
Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
Table 12-3. CANBTR0 Register Field Descriptions
Field 7:6 SJW[1:0] 5:0 BRP[5:0] Description Synchronization Jump Width -- The synchronization jump width defines the maximum number of time quanta (Tq) clock cycles a bit can be shortened or lengthened to achieve resynchronization to data transitions on the CAN bus (see Table 12-4). Baud Rate Prescaler -- These bits determine the time quanta (Tq) clock which is used to build up the bit timing (see Table 12-5).
Table 12-4. Synchronization Jump Width
SJW1 0 0 1 1 SJW0 0 1 0 1 Synchronization Jump Width 1 Tq clock cycle 2 Tq clock cycles 3 Tq clock cycles 4 Tq clock cycles
Table 12-5. Baud Rate Prescaler
BRP5 0 0 0 0 : 1 BRP4 0 0 0 0 : 1 BRP3 0 0 0 0 : 1 BRP2 0 0 0 0 : 1 BRP1 0 0 1 1 : 1 BRP0 0 1 0 1 : 1 Prescaler value (P) 1 2 3 4 : 64
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 353
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
12.3.2.4
MSCAN Bus Timing Register 1 (CANBTR1)
The CANBTR1 register configures various CAN bus timing parameters of the MSCAN module.
Module Base + 0x0003
7 6 5 4 3 2 1 0
R SAMP W Reset: 0 0 0 0 0 0 0 0 TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10
Figure 12-7. MSCAN Bus Timing Register 1 (CANBTR1)
Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
Table 12-6. CANBTR1 Register Field Descriptions
Field 7 SAMP Description Sampling -- This bit determines the number of CAN bus samples taken per bit time. 0 One sample per bit. 1 Three samples per bit1. If SAMP = 0, the resulting bit value is equal to the value of the single bit positioned at the sample point. If SAMP = 1, the resulting bit value is determined by using majority rule on the three total samples. For higher bit rates, it is recommended that only one sample is taken per bit time (SAMP = 0).
6:4 Time Segment 2 -- Time segments within the bit time fix the number of clock cycles per bit time and the location TSEG2[2:0] of the sample point (see Figure 12-43). Time segment 2 (TSEG2) values are programmable as shown in Table 12-7. 3:0 Time Segment 1 -- Time segments within the bit time fix the number of clock cycles per bit time and the location TSEG1[3:0] of the sample point (see Figure 12-43). Time segment 1 (TSEG1) values are programmable as shown in Table 12-8.
1
In this case, PHASE_SEG1 must be at least 2 time quanta (Tq).
Table 12-7. Time Segment 2 Values
TSEG22 0 0 : 1 1
1
TSEG21 0 0 : 1 1
TSEG20 0 1 : 0 1
Time Segment 2 1 Tq clock cycle1 2 Tq clock cycles : 7 Tq clock cycles 8 Tq clock cycles
This setting is not valid. Please refer to Table 12-34 for valid settings.
MC3S12RG128 Data Sheet, Rev. 1.05 354 Freescale Semiconductor
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
Table 12-8. Time Segment 1 Values
TSEG13 0 0 0 0 : 1 1
1
TSEG12 0 0 0 0 : 1 1
TSEG11 0 0 1 1 : 1 1
TSEG10 0 1 0 1 : 0 1
Time segment 1 1 Tq clock cycle1 2 Tq clock cycles1 3 Tq clock cycles1 4 Tq clock cycles : 15 Tq clock cycles 16 Tq clock cycles
This setting is not valid. Please refer to Table 12-34 for valid settings.
The bit time is determined by the oscillator frequency, the baud rate prescaler, and the number of time quanta (Tq) clock cycles per bit (as shown in Table 12-7 and Table 12-8).
Eqn. 12-1
( Prescaler value ) Bit Time = ----------------------------------------------------- * ( 1 + TimeSegment1 + TimeSegment2 ) f CANCLK
12.3.2.5
MSCAN Receiver Flag Register (CANRFLG)
A flag can be cleared only by software (writing a 1 to the corresponding bit position) when the condition which caused the setting is no longer valid. Every flag has an associated interrupt enable bit in the CANRIER register.
Module Base + 0x0004
7 6 5 4 3 2 1 0
R WUPIF W Reset: 0 0 CSCIF
RSTAT1
RSTAT0
TSTAT1
TSTAT0 OVRIF RXF 0
0
0
0
0
0
= Unimplemented
Figure 12-8. MSCAN Receiver Flag Register (CANRFLG)
NOTE The CANRFLG register is held in the reset state1 when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is writable again as soon as the initialization mode is exited (INITRQ = 0 and INITAK = 0). Read: Anytime Write: Anytime when out of initialization mode, except RSTAT[1:0] and TSTAT[1:0] flags which are read-only; write of 1 clears flag; write of 0 is ignored.
1. The RSTAT[1:0], TSTAT[1:0] bits are not affected by initialization mode. MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 355
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
Table 12-9. CANRFLG Register Field Descriptions
Field 7 WUPIF Description Wake-Up Interrupt Flag -- If the MSCAN detects CAN bus activity while in sleep mode (see Section 12.4.5.4, "MSCAN Sleep Mode,") and WUPE = 1 in CANTCTL0 (see Section 12.3.2.1, "MSCAN Control Register 0 (CANCTL0)"), the module will set WUPIF. If not masked, a wake-up interrupt is pending while this flag is set. 0 No wake-up activity observed while in sleep mode 1 MSCAN detected activity on the CAN bus and requested wake-up CAN Status Change Interrupt Flag -- This flag is set when the MSCAN changes its current CAN bus status due to the actual value of the transmit error counter (TEC) and the receive error counter (REC). An additional 4-bit (RSTAT[1:0], TSTAT[1:0]) status register, which is split into separate sections for TEC/REC, informs the system on the actual CAN bus status (see Section 12.3.2.6, "MSCAN Receiver Interrupt Enable Register (CANRIER)"). If not masked, an error interrupt is pending while this flag is set. CSCIF provides a blocking interrupt. That guarantees that the receiver/transmitter status bits (RSTAT/TSTAT) are only updated when no CAN status change interrupt is pending. If the TECs/RECs change their current value after the CSCIF is asserted, which would cause an additional state change in the RSTAT/TSTAT bits, these bits keep their status until the current CSCIF interrupt is cleared again. 0 No change in CAN bus status occurred since last interrupt 1 MSCAN changed current CAN bus status
6 CSCIF
5:4 Receiver Status Bits -- The values of the error counters control the actual CAN bus status of the MSCAN. As RSTAT[1:0] soon as the status change interrupt flag (CSCIF) is set, these bits indicate the appropriate receiver related CAN bus status of the MSCAN. The coding for the bits RSTAT1, RSTAT0 is: 00 RxOK: 0 receive error counter 96 01 RxWRN: 96 < receive error counter 127 10 RxERR: 127 < receive error counter 11 Bus-off1: transmit error counter > 255 3:2 Transmitter Status Bits -- The values of the error counters control the actual CAN bus status of the MSCAN. TSTAT[1:0] As soon as the status change interrupt flag (CSCIF) is set, these bits indicate the appropriate transmitter related CAN bus status of the MSCAN. The coding for the bits TSTAT1, TSTAT0 is: 00 TxOK: 0 transmit error counter 96 01 TxWRN: 96 < transmit error counter 127 10 TxERR: 127 < transmit error counter 255 11 Bus-Off: transmit error counter > 255 1 OVRIF Overrun Interrupt Flag -- This flag is set when a data overrun condition occurs. If not masked, an error interrupt is pending while this flag is set. 0 No data overrun condition 1 A data overrun detected Receive Buffer Full Flag -- RXF is set by the MSCAN when a new message is shifted in the receiver FIFO. This flag indicates whether the shifted buffer is loaded with a correctly received message (matching identifier, matching cyclic redundancy code (CRC) and no other errors detected). After the CPU has read that message from the RxFG buffer in the receiver FIFO, the RXF flag must be cleared to release the buffer. A set RXF flag prohibits the shifting of the next FIFO entry into the foreground buffer (RxFG). If not masked, a receive interrupt is pending while this flag is set. 0 No new message available within the RxFG 1 The receiver FIFO is not empty. A new message is available in the RxFG
0 RXF2
1
Redundant Information for the most critical CAN bus status which is "bus-off". This only occurs if the Tx error counter exceeds a number of 255 errors. Bus-off affects the receiver state. As soon as the transmitter leaves its bus-off state the receiver state skips to RxOK too. Refer also to TSTAT[1:0] coding in this register. 2 To ensure data integrity, do not read the receive buffer registers while the RXF flag is cleared. For MCUs with dual CPUs, reading the receive buffer registers while the RXF flag is cleared may result in a CPU fault condition.
MC3S12RG128 Data Sheet, Rev. 1.05 356 Freescale Semiconductor
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
12.3.2.6
MSCAN Receiver Interrupt Enable Register (CANRIER)
This register contains the interrupt enable bits for the interrupt flags described in the CANRFLG register.
Module Base + 0x0005
7 6 5 4 3 2 1 0
R WUPIE W Reset: 0 0 0 0 0 0 0 0 CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE RXFIE
Figure 12-9. MSCAN Receiver Interrupt Enable Register (CANRIER)
NOTE The CANRIER register is held in the reset state when the initialization mode is active (INITRQ=1 and INITAK=1). This register is writable when not in initialization mode (INITRQ=0 and INITAK=0). The RSTATE[1:0], TSTATE[1:0] bits are not affected by initialization mode. Read: Anytime Write: Anytime when not in initialization mode
Table 12-10. CANRIER Register Field Descriptions
Field 7 WUPIE1 6 CSCIE Description Wake-Up Interrupt Enable 0 No interrupt request is generated from this event. 1 A wake-up event causes a Wake-Up interrupt request. CAN Status Change Interrupt Enable 0 No interrupt request is generated from this event. 1 A CAN Status Change event causes an error interrupt request.
5:4 Receiver Status Change Enable -- These RSTAT enable bits control the sensitivity level in which receiver state RSTATE[1:0] changes are causing CSCIF interrupts. Independent of the chosen sensitivity level the RSTAT flags continue to indicate the actual receiver state and are only updated if no CSCIF interrupt is pending. 00 Do not generate any CSCIF interrupt caused by receiver state changes. 01 Generate CSCIF interrupt only if the receiver enters or leaves "bus-off" state. Discard other receiver state changes for generating CSCIF interrupt. 10 Generate CSCIF interrupt only if the receiver enters or leaves "RxErr" or "bus-off"2 state. Discard other receiver state changes for generating CSCIF interrupt. 11 Generate CSCIF interrupt on all state changes. 3:2 Transmitter Status Change Enable -- These TSTAT enable bits control the sensitivity level in which transmitter TSTATE[1:0] state changes are causing CSCIF interrupts. Independent of the chosen sensitivity level, the TSTAT flags continue to indicate the actual transmitter state and are only updated if no CSCIF interrupt is pending. 00 Do not generate any CSCIF interrupt caused by transmitter state changes. 01 Generate CSCIF interrupt only if the transmitter enters or leaves "bus-off" state. Discard other transmitter state changes for generating CSCIF interrupt. 10 Generate CSCIF interrupt only if the transmitter enters or leaves "TxErr" or "bus-off" state. Discard other transmitter state changes for generating CSCIF interrupt. 11 Generate CSCIF interrupt on all state changes.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 357
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
Table 12-10. CANRIER Register Field Descriptions (continued)
Field 1 OVRIE 0 RXFIE
1
Description Overrun Interrupt Enable 0 No interrupt request is generated from this event. 1 An overrun event causes an error interrupt request. Receiver Full Interrupt Enable 0 No interrupt request is generated from this event. 1 A receive buffer full (successful message reception) event causes a receiver interrupt request.
WUPIE and WUPE (see Section 12.3.2.1, "MSCAN Control Register 0 (CANCTL0)") must both be enabled if the recovery mechanism from stop or wait is required. 2 Bus-off state is defined by the CAN standard (see Bosch CAN 2.0A/B protocol specification: for only transmitters. Because the only possible state change for the transmitter from bus-off to TxOK also forces the receiver to skip its current state to RxOK, the coding of the RXSTAT[1:0] flags define an additional bus-off state for the receiver (see Section 12.3.2.5, "MSCAN Receiver Flag Register (CANRFLG)").
12.3.2.7
MSCAN Transmitter Flag Register (CANTFLG)
The transmit buffer empty flags each have an associated interrupt enable bit in the CANTIER register.
Module Base + 0x0006
7 6 5 4 3 2 1 0
R W Reset:
0
0
0
0
0 TXE2 TXE1 1 TXE0 1
0
0
0
0
0
1
= Unimplemented
Figure 12-10. MSCAN Transmitter Flag Register (CANTFLG)
NOTE The CANTFLG register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is writable when not in initialization mode (INITRQ = 0 and INITAK = 0). Read: Anytime Write: Anytime for TXEx flags when not in initialization mode; write of 1 clears flag, write of 0 is ignored
MC3S12RG128 Data Sheet, Rev. 1.05 358 Freescale Semiconductor
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
Table 12-11. CANTFLG Register Field Descriptions
Field 2:0 TXE[2:0] Description Transmitter Buffer Empty -- This flag indicates that the associated transmit message buffer is empty, and thus not scheduled for transmission. The CPU must clear the flag after a message is set up in the transmit buffer and is due for transmission. The MSCAN sets the flag after the message is sent successfully. The flag is also set by the MSCAN when the transmission request is successfully aborted due to a pending abort request (see Section 12.3.2.9, "MSCAN Transmitter Message Abort Request Register (CANTARQ)"). If not masked, a transmit interrupt is pending while this flag is set. Clearing a TXEx flag also clears the corresponding ABTAKx (see Section 12.3.2.10, "MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK)"). When a TXEx flag is set, the corresponding ABTRQx bit is cleared (see Section 12.3.2.9, "MSCAN Transmitter Message Abort Request Register (CANTARQ)"). When listen-mode is active (see Section 12.3.2.2, "MSCAN Control Register 1 (CANCTL1)") the TXEx flags cannot be cleared and no transmission is started. Read and write accesses to the transmit buffer will be blocked, if the corresponding TXEx bit is cleared (TXEx = 0) and the buffer is scheduled for transmission. 0 The associated message buffer is full (loaded with a message due for transmission) 1 The associated message buffer is empty (not scheduled)
12.3.2.8
MSCAN Transmitter Interrupt Enable Register (CANTIER)
This register contains the interrupt enable bits for the transmit buffer empty interrupt flags.
Module Base + 0x0007
7 6 5 4 3 2 1 0
R W Reset:
0
0
0
0
0 TXEIE2 TXEIE1 0 TXEIE0 0
0
0
0
0
0
0
= Unimplemented
Figure 12-11. MSCAN Transmitter Interrupt Enable Register (CANTIER)
NOTE The CANTIER register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is writable when not in initialization mode (INITRQ = 0 and INITAK = 0). Read: Anytime Write: Anytime when not in initialization mode
Table 12-12. CANTIER Register Field Descriptions
Field 2:0 TXEIE[2:0] Description Transmitter Empty Interrupt Enable 0 No interrupt request is generated from this event. 1 A transmitter empty (transmit buffer available for transmission) event causes a transmitter empty interrupt request.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 359
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
12.3.2.9
MSCAN Transmitter Message Abort Request Register (CANTARQ)
The CANTARQ register allows abort request of queued messages as described below.
Module Base + 0x0008
7 6 5 4 3 2 1 0
R W Reset:
0
0
0
0
0 ABTRQ2 ABTRQ1 0 ABTRQ0 0
0
0
0
0
0
0
= Unimplemented
Figure 12-12. MSCAN Transmitter Message Abort Request Register (CANTARQ)
NOTE The CANTARQ register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is writable when not in initialization mode (INITRQ = 0 and INITAK = 0). Read: Anytime Write: Anytime when not in initialization mode
Table 12-13. CANTARQ Register Field Descriptions
Field Description
2:0 Abort Request -- The CPU sets the ABTRQx bit to request that a scheduled message buffer (TXEx = 0) be ABTRQ[2:0] aborted. The MSCAN grants the request if the message has not already started transmission, or if the transmission is not successful (lost arbitration or error). When a message is aborted, the associated TXE (see Section 12.3.2.7, "MSCAN Transmitter Flag Register (CANTFLG)") and abort acknowledge flags (ABTAK, see Section 12.3.2.10, "MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK)") are set and a transmit interrupt occurs if enabled. The CPU cannot reset ABTRQx. ABTRQx is reset whenever the associated TXE flag is set. 0 No abort request 1 Abort request pending
MC3S12RG128 Data Sheet, Rev. 1.05 360 Freescale Semiconductor
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
12.3.2.10 MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK)
The CANTAAK register indicates the successful abort of a queued message, if requested by the appropriate bits in the CANTARQ register.
Module Base + 0x0009
7 6 5 4 3 2 1 0
R W Reset:
0
0
0
0
0
ABTAK2
ABTAK1
ABTAK0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 12-13. MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK)
NOTE The CANTAAK register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1). Read: Anytime Write: Unimplemented for ABTAKx flags
Table 12-14. CANTAAK Register Field Descriptions
Field Description
2:0 Abort Acknowledge -- This flag acknowledges that a message was aborted due to a pending abort request ABTAK[2:0] from the CPU. After a particular message buffer is flagged empty, this flag can be used by the application software to identify whether the message was aborted successfully or was sent anyway. The ABTAKx flag is cleared whenever the corresponding TXE flag is cleared. 0 The message was not aborted. 1 The message was aborted.
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12.3.2.11 MSCAN Transmit Buffer Selection Register (CANTBSEL)
The CANTBSEL register allows the selection of the actual transmit message buffer, which then will be accessible in the CANTXFG register space.
Module Base + 0x000A
7 6 5 4 3 2 1 0
R W Reset:
0
0
0
0
0 TX2 TX1 0 TX0 0
0
0
0
0
0
0
= Unimplemented
Figure 12-14. MSCAN Transmit Buffer Selection Register (CANTBSEL)
NOTE The CANTBSEL register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK=1). This register is writable when not in initialization mode (INITRQ = 0 and INITAK = 0). Read: Find the lowest ordered bit set to 1, all other bits will be read as 0 Write: Anytime when not in initialization mode
Table 12-15. CANTBSEL Register Field Descriptions
Field 2:0 TX[2:0] Description Transmit Buffer Select -- The lowest numbered bit places the respective transmit buffer in the CANTXFG register space (e.g., TX1 = 1 and TX0 = 1 selects transmit buffer TX0; TX1 = 1 and TX0 = 0 selects transmit buffer TX1). Read and write accesses to the selected transmit buffer will be blocked, if the corresponding TXEx bit is cleared and the buffer is scheduled for transmission (see Section 12.3.2.7, "MSCAN Transmitter Flag Register (CANTFLG)"). 0 The associated message buffer is deselected 1 The associated message buffer is selected, if lowest numbered bit
The following gives a short programming example of the usage of the CANTBSEL register: To get the next available transmit buffer, application software must read the CANTFLG register and write this value back into the CANTBSEL register. In this example Tx buffers TX1 and TX2 are available. The value read from CANTFLG is therefore 0b0000_0110. When writing this value back to CANTBSEL, the Tx buffer TX1 is selected in the CANTXFG because the lowest numbered bit set to 1 is at bit position 1. Reading back this value out of CANTBSEL results in 0b0000_0010, because only the lowest numbered bit position set to 1 is presented. This mechanism eases the application software the selection of the next available Tx buffer. * LDD CANTFLG; value read is 0b0000_0110 * STD CANTBSEL; value written is 0b0000_0110 * LDD CANTBSEL; value read is 0b0000_0010 If all transmit message buffers are deselected, no accesses are allowed to the CANTXFG registers.
MC3S12RG128 Data Sheet, Rev. 1.05 362 Freescale Semiconductor
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
12.3.2.12 MSCAN Identifier Acceptance Control Register (CANIDAC)
The CANIDAC register is used for identifier acceptance control as described below.
Module Base + 0x000B
7 6 5 4 3 2 1 0
R W Reset:
0
0 IDAM1 IDAM0 0
0
IDHIT2
IDHIT1
IDHIT0
0
0
0
0
0
0
0
= Unimplemented
Figure 12-15. MSCAN Identifier Acceptance Control Register (CANIDAC)
Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1), except bits IDHITx, which are read-only
Table 12-16. CANIDAC Register Field Descriptions
Field 5:4 IDAM[1:0] 2:0 IDHIT[2:0] Description Identifier Acceptance Mode -- The CPU sets these flags to define the identifier acceptance filter organization (see Section 12.4.3, "Identifier Acceptance Filter"). Table 12-17 summarizes the different settings. In filter closed mode, no message is accepted such that the foreground buffer is never reloaded. Identifier Acceptance Hit Indicator -- The MSCAN sets these flags to indicate an identifier acceptance hit (see Section 12.4.3, "Identifier Acceptance Filter"). Table 12-18 summarizes the different settings.
Table 12-17. Identifier Acceptance Mode Settings
IDAM1 0 0 1 1 IDAM0 0 1 0 1 Identifier Acceptance Mode Two 32-bit acceptance filters Four 16-bit acceptance filters Eight 8-bit acceptance filters Filter closed
Table 12-18. Identifier Acceptance Hit Indication
IDHIT2 0 0 0 0 1 1 1 1 IDHIT1 0 0 1 1 0 0 1 1 IDHIT0 0 1 0 1 0 1 0 1 Identifier Acceptance Hit Filter 0 hit Filter 1 hit Filter 2 hit Filter 3 hit Filter 4 hit Filter 5 hit Filter 6 hit Filter 7 hit
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 363
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
The IDHITx indicators are always related to the message in the foreground buffer (RxFG). When a message gets shifted into the foreground buffer of the receiver FIFO the indicators are updated as well.
12.3.2.13 MSCAN Reserved Registers
These registers are reserved for factory testing of the MSCAN module and is not available in normal system operation modes.
Module Base + 0x000C, 0x000D
7 6 5 4 3 2 1 0
R W Reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 12-16. MSCAN Reserved Registers
Read: Always read 0x0000 in normal system operation modes Write: Unimplemented in normal system operation modes NOTE Writing to this register when in special modes can alter the MSCAN functionality.
12.3.2.14 MSCAN Receive Error Counter (CANRXERR)
This register reflects the status of the MSCAN receive error counter.
Module Base + 0x000E
7 6 5 4 3 2 1 0
R W Reset:
RXERR7
RXERR6
RXERR5
RXERR4
RXERR3
RXERR2
RXERR1
RXERR0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 12-17. MSCAN Receive Error Counter (CANRXERR)
Read: Only when in sleep mode (SLPRQ = 1 and SLPAK = 1) or initialization mode (INITRQ = 1 and INITAK = 1) Write: Unimplemented
MC3S12RG128 Data Sheet, Rev. 1.05 364 Freescale Semiconductor
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
NOTE Reading this register when in any other mode other than sleep or initialization mode may return an incorrect value. For MCUs with dual CPUs, this may result in a CPU fault condition. Writing to this register when in special modes can alter the MSCAN functionality.
12.3.2.15 MSCAN Transmit Error Counter (CANTXERR)
This register reflects the status of the MSCAN transmit error counter.
Module Base + 0x000F
7 6 5 4 3 2 1 0
R W Reset:
TXERR7
TXERR6
TXERR5
TXERR4
TXERR3
TXERR2
TXERR1
TXERR0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 12-18. MSCAN Transmit Error Counter (CANTXERR)
Read: Only when in sleep mode (SLPRQ = 1 and SLPAK = 1) or initialization mode (INITRQ = 1 and INITAK = 1) Write: Unimplemented NOTE Reading this register when in any other mode other than sleep or initialization mode, may return an incorrect value. For MCUs with dual CPUs, this may result in a CPU fault condition. Writing to this register when in special modes can alter the MSCAN functionality.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 365
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
12.3.2.16 MSCAN Identifier Acceptance Registers (CANIDAR0-7)
On reception, each message is written into the background receive buffer. The CPU is only signalled to read the message if it passes the criteria in the identifier acceptance and identifier mask registers (accepted); otherwise, the message is overwritten by the next message (dropped). The acceptance registers of the MSCAN are applied on the IDR0-IDR3 registers (see Section 12.3.3.1, "Identifier Registers (IDR0-IDR3)") of incoming messages in a bit by bit manner (see Section 12.4.3, "Identifier Acceptance Filter"). For extended identifiers, all four acceptance and mask registers are applied. For standard identifiers, only the first two (CANIDAR0/1, CANIDMR0/1) are applied.
Module Base + 0x0010 (CANIDAR0) 0x0011 (CANIDAR1) 0x0012 (CANIDAR2) 0x0013 (CANIDAR3)
7 6 5 4 3 2 1 0
R W Reset
AC7 0
7
AC6 0
6
AC5 0
5
AC4 0
4
AC3 0
3
AC2 0
2
AC1 0
1
AC0 0
0
R W Reset
AC7 0
7
AC6 0
6
AC5 0
5
AC4 0
4
AC3 0
3
AC2 0
2
AC1 0
1
AC0 0
0
R W Reset
AC7 0
7
AC6 0
6
AC5 0
5
AC4 0
4
AC3 0
3
AC2 0
2
AC1 0
1
AC0 0
0
R W Reset
AC7 0
AC6 0
AC5 0
AC4 0
AC3 0
AC2 0
AC1 0
AC0 0
Figure 12-19. MSCAN Identifier Acceptance Registers (First Bank) -- CANIDAR0-CANIDAR3
Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
Table 12-19. CANIDAR0-CANIDAR3 Register Field Descriptions
Field 7:0 AC[7:0] Description Acceptance Code Bits -- AC[7:0] comprise a user-defined sequence of bits with which the corresponding bits of the related identifier register (IDRn) of the receive message buffer are compared. The result of this comparison is then masked with the corresponding identifier mask register.
MC3S12RG128 Data Sheet, Rev. 1.05 366 Freescale Semiconductor
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
Module Base + 0x0018 (CANIDAR4) 0x0019 (CANIDAR5) 0x001A (CANIDAR6) 0x001B (CANIDAR7)
7 6 5 4 3 2 1 0
R W Reset
AC7 0
7
AC6 0
6
AC5 0
5
AC4 0
4
AC3 0
3
AC2 0
2
AC1 0
1
AC0 0
0
R W Reset
AC7 0
7
AC6 0
6
AC5 0
5
AC4 0
4
AC3 0
3
AC2 0
2
AC1 0
1
AC0 0
0
R W Reset
AC7 0
7
AC6 0
6
AC5 0
5
AC4 0
4
AC3 0
3
AC2 0
2
AC1 0
1
AC0 0
0
R W Reset
AC7 0
AC6 0
AC5 0
AC4 0
AC3 0
AC2 0
AC1 0
AC0 0
Figure 12-20. MSCAN Identifier Acceptance Registers (Second Bank) -- CANIDAR4-CANIDAR7
Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
Table 12-20. CANIDAR4-CANIDAR7 Register Field Descriptions
Field 7:0 AC[7:0] Description Acceptance Code Bits -- AC[7:0] comprise a user-defined sequence of bits with which the corresponding bits of the related identifier register (IDRn) of the receive message buffer are compared. The result of this comparison is then masked with the corresponding identifier mask register.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 367
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
12.3.2.17 MSCAN Identifier Mask Registers (CANIDMR0-CANIDMR7)
The identifier mask register specifies which of the corresponding bits in the identifier acceptance register are relevant for acceptance filtering. To receive standard identifiers in 32 bit filter mode, it is required to program the last three bits (AM[2:0]) in the mask registers CANIDMR1 and CANIDMR5 to "don't care." To receive standard identifiers in 16 bit filter mode, it is required to program the last three bits (AM[2:0]) in the mask registers CANIDMR1, CANIDMR3, CANIDMR5, and CANIDMR7 to "don't care."
Module Base + 0x0014 (CANIDMR0) 0x0015 (CANIDMR1) 0x0016 (CANIDMR2) 0x0017 (CANIDMR3)
7 6 5 4 3 2 1 0
R W Reset
AM7 0
7
AM6 0
6
AM5 0
5
AM4 0
4
AM3 0
3
AM2 0
2
AM1 0
1
AM0 0
0
R W Reset
AM7 0
7
AM6 0
6
AM5 0
5
AM4 0
4
AM3 0
3
AM2 0
2
AM1 0
1
AM0 0
0
R W Reset
AM7 0
7
AM6 0
6
AM5 0
5
AM4 0
4
AM3 0
3
AM2 0
2
AM1 0
1
AM0 0
0
R W Reset
AM7 0
AM6 0
AM5 0
AM4 0
AM3 0
AM2 0
AM1 0
AM0 0
Figure 12-21. MSCAN Identifier Mask Registers (First Bank) -- CANIDMR0-CANIDMR3
Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
Table 12-21. CANIDMR0-CANIDMR3 Register Field Descriptions
Field 7:0 AM[7:0] Description Acceptance Mask Bits -- If a particular bit in this register is cleared, this indicates that the corresponding bit in the identifier acceptance register must be the same as its identifier bit before a match is detected. The message is accepted if all such bits match. If a bit is set, it indicates that the state of the corresponding bit in the identifier acceptance register does not affect whether or not the message is accepted. 0 Match corresponding acceptance code register and identifier bits 1 Ignore corresponding acceptance code register bit
MC3S12RG128 Data Sheet, Rev. 1.05 368 Freescale Semiconductor
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
Module Base + 0x001C (CANIDMR4) 0x001D (CANIDMR5) 0x001E (CANIDMR6) 0x001F (CANIDMR7)
7 6 5 4 3 2 1 0
R W Reset
AM7 0
7
AM6 0
6
AM5 0
5
AM4 0
4
AM3 0
3
AM2 0
2
AM1 0
1
AM0 0
0
R W Reset
AM7 0
7
AM6 0
6
AM5 0
5
AM4 0
4
AM3 0
3
AM2 0
2
AM1 0
1
AM0 0
0
R W Reset
AM7 0
7
AM6 0
6
AM5 0
5
AM4 0
4
AM3 0
3
AM2 0
2
AM1 0
1
AM0 0
0
R W Reset
AM7 0
AM6 0
AM5 0
AM4 0
AM3 0
AM2 0
AM1 0
AM0 0
Figure 12-22. MSCAN Identifier Mask Registers (Second Bank) -- CANIDMR4-CANIDMR7
Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
Table 12-22. CANIDMR4-CANIDMR7 Register Field Descriptions
Field 7:0 AM[7:0] Description Acceptance Mask Bits -- If a particular bit in this register is cleared, this indicates that the corresponding bit in the identifier acceptance register must be the same as its identifier bit before a match is detected. The message is accepted if all such bits match. If a bit is set, it indicates that the state of the corresponding bit in the identifier acceptance register does not affect whether or not the message is accepted. 0 Match corresponding acceptance code register and identifier bits 1 Ignore corresponding acceptance code register bit
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 369
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
12.3.3
Programmer's Model of Message Storage
The following section details the organization of the receive and transmit message buffers and the associated control registers. To simplify the programmer interface, the receive and transmit message buffers have the same outline. Each message buffer allocates 16 bytes in the memory map containing a 13 byte data structure. An additional transmit buffer priority register (TBPR) is defined for the transmit buffers. Within the last two bytes of this memory map, the MSCAN stores a special 16-bit time stamp, which is sampled from an internal timer after successful transmission or reception of a message. This feature is only available for transmit and receiver buffers, if the TIME bit is set (see Section 12.3.2.1, "MSCAN Control Register 0 (CANCTL0)"). The time stamp register is written by the MSCAN. The CPU can only read these registers.
Table 12-23. Message Buffer Organization
Offset Address 0x00X0 0x00X1 0x00X2 0x00X3 0x00X4 0x00X5 0x00X6 0x00X7 0x00X8 0x00X9 0x00XA 0x00XB 0x00XC 0x00XD 0x00XE 0x00XF
1 2
Register Identifier Register 0 Identifier Register 1 Identifier Register 2 Identifier Register 3 Data Segment Register 0 Data Segment Register 1 Data Segment Register 2 Data Segment Register 3 Data Segment Register 4 Data Segment Register 5 Data Segment Register 6 Data Segment Register 7 Data Length Register Transmit Buffer Priority Register1 Time Stamp Register (High Byte)2 Time Stamp Register (Low Byte)3
Access
Not applicable for receive buffers Read-only for CPU 3 Read-only for CPU
Figure 12-23 shows the common 13-byte data structure of receive and transmit buffers for extended identifiers. The mapping of standard identifiers into the IDR registers is shown in Figure 12-24. All bits of the receive and transmit buffers are `x' out of reset because of RAM-based implementation1. All reserved or unused bits of the receive and transmit buffers always read `x'.
1. Exception: The transmit priority registers are 0 out of reset. MC3S12RG128 Data Sheet, Rev. 1.05 370 Freescale Semiconductor
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
Register Name 0x00X0 IDR0 0x00X1 IDR1 0x00X2 IDR2 0x00X3 IDR3 0x00X4 DSR0 0x00X5 DSR1 0x00X6 DSR2 0x00X7 DSR3 0x00X8 DSR4 0x00X9 DSR5 0x00XA DSR6 0x00XB DSR7 0x00XC DLR R W R W R W R W R W R W R W R W R W R W R W R W R W
Bit 7 ID28
6 ID27
5 ID26
4 ID25
3 ID24
2 ID23
1 ID22
Bit0 ID21
ID20
ID19
ID18
SRR (=1)
IDE (=1)
ID17
ID16
ID15
ID14
ID13
ID12
ID11
ID10
ID9
ID8
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
RTR
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DLC3
DLC2
DLC1
DLC0
= Unused, always read `x'
Figure 12-23. Receive/Transmit Message Buffer -- Extended Identifier Mapping
Read: For transmit buffers, anytime when TXEx flag is set (see Section 12.3.2.7, "MSCAN Transmitter Flag Register (CANTFLG)") and the corresponding transmit buffer is selected in CANTBSEL (see Section 12.3.2.11, "MSCAN Transmit Buffer Selection Register (CANTBSEL)"). For receive buffers, only when RXF flag is set (see Section 12.3.2.5, "MSCAN Receiver Flag Register (CANRFLG)").
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 371
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
Write: For transmit buffers, anytime when TXEx flag is set (see Section 12.3.2.7, "MSCAN Transmitter Flag Register (CANTFLG)") and the corresponding transmit buffer is selected in CANTBSEL (see Section 12.3.2.11, "MSCAN Transmit Buffer Selection Register (CANTBSEL)"). Unimplemented for receive buffers. Reset: Undefined (0x00XX) because of RAM-based implementation
Register Name IDR0 0x00X0 IDR1 0x00X1 IDR2 0x00X2 IDR3 0x00X3 R W R W R W R W Bit 7 ID10 6 ID9 5 ID8 4 ID7 3 ID6 2 ID5 1 ID4 Bit 0 ID3
ID2
ID1
ID0
RTR
IDE (=0)
= Unused, always read `x'
Figure 12-24. Receive/Transmit Message Buffer -- Standard Identifier Mapping
12.3.3.1
Identifier Registers (IDR0-IDR3)
The identifier registers for an extended format identifier consist of a total of 32 bits; ID[28:0], SRR, IDE, and RTR bits. The identifier registers for a standard format identifier consist of a total of 13 bits; ID[10:0], RTR, and IDE bits. 12.3.3.1.1 IDR0-IDR3 for Extended Identifier Mapping
Module Base + 0x00X1
7 6 5 4 3 2 1 0
R ID28 W Reset: x x x x x x x x ID27 ID26 ID25 ID24 ID23 ID22 ID21
Figure 12-25. Identifier Register 0 (IDR0) -- Extended Identifier Mapping Table 12-24. IDR0 Register Field Descriptions -- Extended
Field 7:0 ID[28:21] Description Extended Format Identifier -- The identifiers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number.
MC3S12RG128 Data Sheet, Rev. 1.05 372 Freescale Semiconductor
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
Module Base + 0x00X1
7 6 5 4 3 2 1 0
R ID20 W Reset: x x x x x x x x ID19 ID18 SRR (=1) IDE (=1) ID17 ID16 ID15
Figure 12-26. Identifier Register 1 (IDR1) -- Extended Identifier Mapping Table 12-25. IDR1 Register Field Descriptions -- Extended
Field 7:5 ID[20:18] 4 SRR 3 IDE Description Extended Format Identifier -- The identifiers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number. Substitute Remote Request -- This fixed recessive bit is used only in extended format. It must be set to 1 by the user for transmission buffers and is stored as received on the CAN bus for receive buffers. ID Extended -- This flag indicates whether the extended or standard identifier format is applied in this buffer. In the case of a receive buffer, the flag is set as received and indicates to the CPU how to process the buffer identifier registers. In the case of a transmit buffer, the flag indicates to the MSCAN what type of identifier to send. 0 Standard format (11 bit) 1 Extended format (29 bit) Extended Format Identifier -- The identifiers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number.
2:0 ID[17:15]
Module Base + 0x00X2
7 6 5 4 3 2 1 0
R ID14 W Reset: x x x x x x x x ID13 ID12 ID11 ID10 ID9 ID8 ID7
Figure 12-27. Identifier Register 2 (IDR2) -- Extended Identifier Mapping Table 12-26. IDR2 Register Field Descriptions -- Extended
Field 7:0 ID[14:7] Description Extended Format Identifier -- The identifiers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 373
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
Module Base + 0x00X3
7 6 5 4 3 2 1 0
R ID6 W Reset: x x x x x x x x ID5 ID4 ID3 ID2 ID1 ID0 RTR
Figure 12-28. Identifier Register 3 (IDR3) -- Extended Identifier Mapping Table 12-27. IDR3 Register Field Descriptions -- Extended
Field 7:1 ID[6:0] 0 RTR Description Extended Format Identifier -- The identifiers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number. Remote Transmission Request -- This flag reflects the status of the remote transmission request bit in the CAN frame. In the case of a receive buffer, it indicates the status of the received frame and supports the transmission of an answering frame in software. In the case of a transmit buffer, this flag defines the setting of the RTR bit to be sent. 0 Data frame 1 Remote frame
12.3.3.1.2
IDR0-IDR3 for Standard Identifier Mapping
Module Base + 0x00X0
7 6 5 4 3 2 1 0
R ID10 W Reset: x x x x x x x x ID9 ID8 ID7 ID6 ID5 ID4 ID3
Figure 12-29. Identifier Register 0 -- Standard Mapping Table 12-28. IDR0 Register Field Descriptions -- Standard
Field 7:0 ID[10:3] Description Standard Format Identifier -- The identifiers consist of 11 bits (ID[10:0]) for the standard format. ID10 is the most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number. See also ID bits in Table 12-29.
MC3S12RG128 Data Sheet, Rev. 1.05 374 Freescale Semiconductor
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
Module Base + 0x00X1
7 6 5 4 3 2 1 0
R ID2 W Reset: x x x x x x x x ID1 ID0 RTR IDE (=0)
= Unused; always read `x'
Figure 12-30. Identifier Register 1 -- Standard Mapping Table 12-29. IDR1 Register Field Descriptions
Field 7:5 ID[2:0] 4 RTR Description Standard Format Identifier -- The identifiers consist of 11 bits (ID[10:0]) for the standard format. ID10 is the most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number. See also ID bits in Table 12-28. Remote Transmission Request -- This flag reflects the status of the Remote Transmission Request bit in the CAN frame. In the case of a receive buffer, it indicates the status of the received frame and supports the transmission of an answering frame in software. In the case of a transmit buffer, this flag defines the setting of the RTR bit to be sent. 0 Data frame 1 Remote frame ID Extended -- This flag indicates whether the extended or standard identifier format is applied in this buffer. In the case of a receive buffer, the flag is set as received and indicates to the CPU how to process the buffer identifier registers. In the case of a transmit buffer, the flag indicates to the MSCAN what type of identifier to send. 0 Standard format (11 bit) 1 Extended format (29 bit)
3 IDE
Module Base + 0x00X2
7 6 5 4 3 2 1 0
R W Reset: x x x x x x x x
= Unused; always read `x'
Figure 12-31. Identifier Register 2 -- Standard Mapping
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 375
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
Module Base + 0x00X3
7 6 5 4 3 2 1 0
R W Reset: x x x x x x x x
= Unused; always read `x'
Figure 12-32. Identifier Register 3 -- Standard Mapping
12.3.3.2
Data Segment Registers (DSR0-7)
The eight data segment registers, each with bits DB[7:0], contain the data to be transmitted or received. The number of bytes to be transmitted or received is determined by the data length code in the corresponding DLR register.
Module Base + 0x0004 (DSR0) 0x0005 (DSR1) 0x0006 (DSR2) 0x0007 (DSR3) 0x0008 (DSR4) 0x0009 (DSR5) 0x000A (DSR6) 0x000B (DSR7)
7 6 5 4 3 2 1 0
R DB7 W Reset: x x x x x x x x DB6 DB5 DB4 DB3 DB2 DB1 DB0
Figure 12-33. Data Segment Registers (DSR0-DSR7) -- Extended Identifier Mapping
Table 12-30. DSR0-DSR7 Register Field Descriptions
Field 7:0 DB[7:0] Data bits 7:0 Description
MC3S12RG128 Data Sheet, Rev. 1.05 376 Freescale Semiconductor
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
12.3.3.3
Data Length Register (DLR)
This register keeps the data length field of the CAN frame.
Module Base + 0x00XB
7 6 5 4 3 2 1 0
R DLC3 W Reset: x x x x x x x x DLC2 DLC1 DLC0
= Unused; always read "x"
Figure 12-34. Data Length Register (DLR) -- Extended Identifier Mapping
Table 12-31. DLR Register Field Descriptions
Field 3:0 DLC[3:0] Description Data Length Code Bits -- The data length code contains the number of bytes (data byte count) of the respective message. During the transmission of a remote frame, the data length code is transmitted as programmed while the number of transmitted data bytes is always 0. The data byte count ranges from 0 to 8 for a data frame. Table 12-32 shows the effect of setting the DLC bits.
Table 12-32. Data Length Codes
Data Length Code DLC3 0 0 0 0 0 0 0 0 1 DLC2 0 0 0 0 1 1 1 1 0 DLC1 0 0 1 1 0 0 1 1 0 DLC0 0 1 0 1 0 1 0 1 0 Data Byte Count 0 1 2 3 4 5 6 7 8
12.3.3.4
Transmit Buffer Priority Register (TBPR)
This register defines the local priority of the associated message buffer. The local priority is used for the internal prioritization process of the MSCAN and is defined to be highest for the smallest binary number. The MSCAN implements the following internal prioritization mechanisms: * All transmission buffers with a cleared TXEx flag participate in the prioritization immediately before the SOF (start of frame) is sent. * The transmission buffer with the lowest local priority field wins the prioritization.
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In cases of more than one buffer having the same lowest priority, the message buffer with the lower index number wins.
Module Base + 0xXXXD
7 6 5 4 3 2 1 0
R PRIO7 W Reset: 0 0 0 0 0 0 0 0 PRIO6 PRIO5 PRIO4 PRIO3 PRIO2 PRIO1 PRIO0
Figure 12-35. Transmit Buffer Priority Register (TBPR)
Read: Anytime when TXEx flag is set (see Section 12.3.2.7, "MSCAN Transmitter Flag Register (CANTFLG)") and the corresponding transmit buffer is selected in CANTBSEL (see Section 12.3.2.11, "MSCAN Transmit Buffer Selection Register (CANTBSEL)"). Write: Anytime when TXEx flag is set (see Section 12.3.2.7, "MSCAN Transmitter Flag Register (CANTFLG)") and the corresponding transmit buffer is selected in CANTBSEL (see Section 12.3.2.11, "MSCAN Transmit Buffer Selection Register (CANTBSEL)").
12.3.3.5
Time Stamp Register (TSRH-TSRL)
If the TIME bit is enabled, the MSCAN will write a time stamp to the respective registers in the active transmit or receive buffer right after the EOF of a valid message on the CAN bus (see Section 12.3.2.1, "MSCAN Control Register 0 (CANCTL0)"). In case of a transmission, the CPU can only read the time stamp after the respective transmit buffer has been flagged empty. The timer value, which is used for stamping, is taken from a free running internal CAN bit clock. A timer overrun is not indicated by the MSCAN. The timer is reset (all bits set to 0) during initialization mode. The CPU can only read the time stamp registers.
Module Base + 0xXXXE
7 6 5 4 3 2 1 0
R W Reset:
TSR15
TSR14
TSR13
TSR12
TSR11
TSR10
TSR9
TSR8
x
x
x
x
x
x
x
x
Figure 12-36. Time Stamp Register -- High Byte (TSRH)
Module Base + 0xXXXF
7 6 5 4 3 2 1 0
R W Reset:
TSR7
TSR6
TSR5
TSR4
TSR3
TSR2
TSR1
TSR0
x
x
x
x
x
x
x
x
Figure 12-37. Time Stamp Register -- Low Byte (TSRL)
MC3S12RG128 Data Sheet, Rev. 1.05 378 Freescale Semiconductor
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
Read: Anytime when TXEx flag is set (see Section 12.3.2.7, "MSCAN Transmitter Flag Register (CANTFLG)") and the corresponding transmit buffer is selected in CANTBSEL (see Section 12.3.2.11, "MSCAN Transmit Buffer Selection Register (CANTBSEL)"). Write: Unimplemented
12.4
12.4.1
Functional Description
General
This section provides a complete functional description of the MSCAN. It describes each of the features and modes listed in the introduction.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 379
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
12.4.2
Message Storage
CAN Receive / Transmit Engine CPU12 Memory Mapped I/O
Rx0
Rx1 Rx2 Rx3 Rx4
RXF
RxBG
MSCAN
Receiver
Tx0
RxFG
CPU bus
TXE0
TxBG
Tx1
PRIO
TXE1
TxFG
MSCAN
CPU bus
PRIO
Tx2
TXE2
Transmitter
TxBG
PRIO
Figure 12-38. User Model for Message Buffer Organization
MSCAN facilitates a sophisticated message storage system which addresses the requirements of a broad range of network applications.
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Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
12.4.2.1
Message Transmit Background
Modern application layer software is built upon two fundamental assumptions: * Any CAN node is able to send out a stream of scheduled messages without releasing the CAN bus between the two messages. Such nodes arbitrate for the CAN bus immediately after sending the previous message and only release the CAN bus in case of lost arbitration. * The internal message queue within any CAN node is organized such that the highest priority message is sent out first, if more than one message is ready to be sent. The behavior described in the bullets above cannot be achieved with a single transmit buffer. That buffer must be reloaded immediately after the previous message is sent. This loading process lasts a finite amount of time and must be completed within the inter-frame sequence (IFS) to be able to send an uninterrupted stream of messages. Even if this is feasible for limited CAN bus speeds, it requires that the CPU reacts with short latencies to the transmit interrupt. A double buffer scheme de-couples the reloading of the transmit buffer from the actual message sending and, therefore, reduces the reactiveness requirements of the CPU. Problems can arise if the sending of a message is finished while the CPU re-loads the second buffer. No buffer would then be ready for transmission, and the CAN bus would be released. At least three transmit buffers are required to meet the first of the above requirements under all circumstances. The MSCAN has three transmit buffers. The second requirement calls for some sort of internal prioritization which the MSCAN implements with the "local priority" concept described in Section 12.4.2.2, "Transmit Structures."
12.4.2.2
Transmit Structures
The MSCAN triple transmit buffer scheme optimizes real-time performance by allowing multiple messages to be set up in advance. The three buffers are arranged as shown in Figure 12-38. All three buffers have a 13-byte data structure similar to the outline of the receive buffers (see Section 12.3.3, "Programmer's Model of Message Storage"). An additional Section 12.3.3.4, "Transmit Buffer Priority Register (TBPR) contains an 8-bit local priority field (PRIO) (see Section 12.3.3.4, "Transmit Buffer Priority Register (TBPR)"). The remaining two bytes are used for time stamping of a message, if required (see Section 12.3.3.5, "Time Stamp Register (TSRH-TSRL)"). To transmit a message, the CPU must identify an available transmit buffer, which is indicated by a set transmitter buffer empty (TXEx) flag (see Section 12.3.2.7, "MSCAN Transmitter Flag Register (CANTFLG)"). If a transmit buffer is available, the CPU must set a pointer to this buffer by writing to the CANTBSEL register (see Section 12.3.2.11, "MSCAN Transmit Buffer Selection Register (CANTBSEL)"). This makes the respective buffer accessible within the CANTXFG address space (see Section 12.3.3, "Programmer's Model of Message Storage"). The algorithmic feature associated with the CANTBSEL register simplifies the transmit buffer selection. In addition, this scheme makes the handler software simpler because only one address area is applicable for the transmit process, and the required address space is minimized. The CPU then stores the identifier, the control bits, and the data content into one of the transmit buffers. Finally, the buffer is flagged as ready for transmission by clearing the associated TXE flag.
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The MSCAN then schedules the message for transmission and signals the successful transmission of the buffer by setting the associated TXE flag. A transmit interrupt (see Section 12.4.7.2, "Transmit Interrupt") is generated1 when TXEx is set and can be used to drive the application software to re-load the buffer. If more than one buffer is scheduled for transmission when the CAN bus becomes available for arbitration, the MSCAN uses the local priority setting of the three buffers to determine the prioritization. For this purpose, every transmit buffer has an 8-bit local priority field (PRIO). The application software programs this field when the message is set up. The local priority reflects the priority of this particular message relative to the set of messages being transmitted from this node. The lowest binary value of the PRIO field is defined to be the highest priority. The internal scheduling process takes place whenever the MSCAN arbitrates for the CAN bus. This is also the case after the occurrence of a transmission error. When a high priority message is scheduled by the application software, it may become necessary to abort a lower priority message in one of the three transmit buffers. Because messages that are already in transmission cannot be aborted, the user must request the abort by setting the corresponding abort request bit (ABTRQ) (see Section 12.3.2.9, "MSCAN Transmitter Message Abort Request Register (CANTARQ)".) The MSCAN then grants the request, if possible, by: 1. Setting the corresponding abort acknowledge flag (ABTAK) in the CANTAAK register. 2. Setting the associated TXE flag to release the buffer. 3. Generating a transmit interrupt. The transmit interrupt handler software can determine from the setting of the ABTAK flag whether the message was aborted (ABTAK = 1) or sent (ABTAK = 0).
12.4.2.3
Receive Structures
The received messages are stored in a five stage input FIFO. The five message buffers are alternately mapped into a single memory area (see Figure 12-38). The background receive buffer (RxBG) is exclusively associated with the MSCAN, but the foreground receive buffer (RxFG) is addressable by the CPU (see Figure 12-38). This scheme simplifies the handler software because only one address area is applicable for the receive process. All receive buffers have a size of 15 bytes to store the CAN control bits, the identifier (standard or extended), the data contents, and a time stamp, if enabled (see Section 12.3.3, "Programmer's Model of Message Storage"). The receiver full flag (RXF) (see Section 12.3.2.5, "MSCAN Receiver Flag Register (CANRFLG)") signals the status of the foreground receive buffer. When the buffer contains a correctly received message with a matching identifier, this flag is set. On reception, each message is checked to see whether it passes the filter (see Section 12.4.3, "Identifier Acceptance Filter") and simultaneously is written into the active RxBG. After successful reception of a valid message, the MSCAN shifts the content of RxBG into the receiver FIFO2, sets the RXF flag, and generates a receive interrupt (see Section 12.4.7.3, "Receive Interrupt") to the CPU3. The user's receive handler must read the received message from the RxFG and then reset the RXF flag to acknowledge the interrupt and to release the foreground buffer. A new message, which can follow immediately after the IFS
1. The transmit interrupt occurs only if not masked. A polling scheme can be applied on TXEx also. 2. Only if the RXF flag is not set. 3. The receive interrupt occurs only if not masked. A polling scheme can be applied on RXF also. MC3S12RG128 Data Sheet, Rev. 1.05 382 Freescale Semiconductor
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
field of the CAN frame, is received into the next available RxBG. If the MSCAN receives an invalid message in its RxBG (wrong identifier, transmission errors, etc.) the actual contents of the buffer will be over-written by the next message. The buffer will then not be shifted into the FIFO. When the MSCAN module is transmitting, the MSCAN receives its own transmitted messages into the background receive buffer, RxBG, but does not shift it into the receiver FIFO, generate a receive interrupt, or acknowledge its own messages on the CAN bus. The exception to this rule is in loopback mode (see Section 12.3.2.2, "MSCAN Control Register 1 (CANCTL1)") where the MSCAN treats its own messages exactly like all other incoming messages. The MSCAN receives its own transmitted messages in the event that it loses arbitration. If arbitration is lost, the MSCAN must be prepared to become a receiver. An overrun condition occurs when all receive message buffers in the FIFO are filled with correctly received messages with accepted identifiers and another message is correctly received from the CAN bus with an accepted identifier. The latter message is discarded and an error interrupt with overrun indication is generated if enabled (see Section 12.4.7.5, "Error Interrupt"). The MSCAN remains able to transmit messages while the receiver FIFO being filled, but all incoming messages are discarded. As soon as a receive buffer in the FIFO is available again, new valid messages will be accepted.
12.4.3
Identifier Acceptance Filter
The MSCAN identifier acceptance registers (see Section 12.3.2.12, "MSCAN Identifier Acceptance Control Register (CANIDAC)") define the acceptable patterns of the standard or extended identifier (ID[10:0] or ID[28:0]). Any of these bits can be marked `don't care' in the MSCAN identifier mask registers (see Section 12.3.2.17, "MSCAN Identifier Mask Registers (CANIDMR0-CANIDMR7)"). A filter hit is indicated to the application software by a set receive buffer full flag (RXF = 1) and three bits in the CANIDAC register (see Section 12.3.2.12, "MSCAN Identifier Acceptance Control Register (CANIDAC)"). These identifier hit flags (IDHIT[2:0]) clearly identify the filter section that caused the acceptance. They simplify the application software's task to identify the cause of the receiver interrupt. If more than one hit occurs (two or more filters match), the lower hit has priority. A very flexible programmable generic identifier acceptance filter has been introduced to reduce the CPU interrupt loading. The filter is programmable to operate in four different modes (see Bosch CAN 2.0A/B protocol specification): * Two identifier acceptance filters, each to be applied to: -- The full 29 bits of the extended identifier and to the following bits of the CAN 2.0B frame: - Remote transmission request (RTR) - Identifier extension (IDE) - Substitute remote request (SRR) -- The 11 bits of the standard identifier plus the RTR and IDE bits of the CAN 2.0A/B messages1. This mode implements two filters for a full length CAN 2.0B compliant extended identifier. Figure 12-39 shows how the first 32-bit filter bank (CANIDAR0-CANIDAR3, CANIDMR0-CANIDMR3) produces a filter 0 hit. Similarly, the second filter bank (CANIDAR4-CANIDAR7, CANIDMR4-CANIDMR7) produces a filter 1 hit.
1.Although this mode can be used for standard identifiers, it is recommended to use the four or eight identifier acceptance filters for standard identifiers MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 383
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
*
*
*
Four identifier acceptance filters, each to be applied to -- a) the 14 most significant bits of the extended identifier plus the SRR and IDE bits of CAN 2.0B messages or -- b) the 11 bits of the standard identifier, the RTR and IDE bits of CAN 2.0A/B messages. Figure 12-40 shows how the first 32-bit filter bank (CANIDAR0-CANIDA3, CANIDMR0-3CANIDMR) produces filter 0 and 1 hits. Similarly, the second filter bank (CANIDAR4-CANIDAR7, CANIDMR4-CANIDMR7) produces filter 2 and 3 hits. Eight identifier acceptance filters, each to be applied to the first 8 bits of the identifier. This mode implements eight independent filters for the first 8 bits of a CAN 2.0A/B compliant standard identifier or a CAN 2.0B compliant extended identifier. Figure 12-41 shows how the first 32-bit filter bank (CANIDAR0-CANIDAR3, CANIDMR0-CANIDMR3) produces filter 0 to 3 hits. Similarly, the second filter bank (CANIDAR4-CANIDAR7, CANIDMR4-CANIDMR7) produces filter 4 to 7 hits. Closed filter. No CAN message is copied into the foreground buffer RxFG, and the RXF flag is never set.
IDR0 IDR0 ID21 ID3 ID20 ID2 IDR1 IDR1 ID15 IDE ID14 ID10 IDR2 IDR2 ID7 ID3 ID6 ID10 IDR3 IDR3 RTR ID3
CAN 2.0B Extended Identifier ID28 CAN 2.0A/B Standard Identifier ID10
AM7
CANIDMR0
AM0
AM7
CANIDMR1
AM0
AM7
CANIDMR2
AM0
AM7
CANIDMR3
AM0
AC7
CANIDAR0
AC0
AC7
CANIDAR1
AC0
AC7
CANIDAR2
AC0
AC7
CANIDAR3
AC0
ID Accepted (Filter 0 Hit)
Figure 12-39. 32-bit Maskable Identifier Acceptance Filter
MC3S12RG128 Data Sheet, Rev. 1.05 384 Freescale Semiconductor
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
CAN 2.0B Extended Identifier CAN 2.0A/B Standard Identifier
ID28 ID10
IDR0 IDR0
ID21 ID3
ID20 ID2
IDR1 IDR1
ID15 IDE
ID14 ID10
IDR2 IDR2
ID7 ID3
ID6 ID10
IDR3 IDR3
RTR ID3
AM7
CANIDMR0
AM0
AM7
CANIDMR1
AM0
AC7
CANIDAR0
AC0
AC7
CANIDAR1
AC0
ID Accepted (Filter 0 Hit)
AM7
CANIDMR2
AM0
AM7
CANIDMR3
AM0
AC7
CANIDAR2
AC0
AC7
CANIDAR3
AC0
ID Accepted (Filter 1 Hit)
Figure 12-40. 16-bit Maskable Identifier Acceptance Filters
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CAN 2.0B Extended Identifier ID28 CAN 2.0A/B Standard Identifier ID10
IDR0 IDR0
ID21 ID3
ID20 ID2
IDR1 IDR1
ID15 IDE
ID14 ID10
IDR2 IDR2
ID7 ID3
ID6 ID10
IDR3 IDR3
RTR ID3
AM7
CIDMR0
AM0
AC7
CIDAR0
AC0
ID Accepted (Filter 0 Hit)
AM7
CIDMR1
AM0
AC7
CIDAR1
AC0
ID Accepted (Filter 1 Hit)
AM7
CIDMR2
AM0
AC7
CIDAR2
AC0
ID Accepted (Filter 2 Hit)
AM7
CIDMR3
AM0
AC7
CIDAR3
AC0
ID Accepted (Filter 3 Hit)
Figure 12-41. 8-bit Maskable Identifier Acceptance Filters
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12.4.3.1
Protocol Violation Protection
The MSCAN protects the user from accidentally violating the CAN protocol through programming errors. The protection logic implements the following features: * The receive and transmit error counters cannot be written or otherwise manipulated. * All registers which control the configuration of the MSCAN cannot be modified while the MSCAN is on-line. The MSCAN has to be in Initialization Mode. The corresponding INITRQ/INITAK handshake bits in the CANCTL0/CANCTL1 registers (see Section 12.3.2.1, "MSCAN Control Register 0 (CANCTL0)") serve as a lock to protect the following registers: -- MSCAN control 1 register (CANCTL1) -- MSCAN bus timing registers 0 and 1 (CANBTR0, CANBTR1) -- MSCAN identifier acceptance control register (CANIDAC) -- MSCAN identifier acceptance registers (CANIDAR0-CANIDAR7) -- MSCAN identifier mask registers (CANIDMR0-CANIDMR7) * The TXCAN pin is immediately forced to a recessive state when the MSCAN goes into the power down mode or initialization mode (see Section 12.4.5.6, "MSCAN Power Down Mode," and Section 12.4.5.5, "MSCAN Initialization Mode"). * The MSCAN enable bit (CANE) is writable only once in normal system operation modes, which provides further protection against inadvertently disabling the MSCAN.
12.4.3.2
Clock System
Figure 12-42 shows the structure of the MSCAN clock generation circuitry.
MSCAN
Bus Clock
CANCLK CLKSRC
Prescaler (1 .. 64)
Time quanta clock (Tq)
CLKSRC Oscillator Clock
Figure 12-42. MSCAN Clocking Scheme
The clock source bit (CLKSRC) in the CANCTL1 register (12.3.2.2/12-350) defines whether the internal CANCLK is connected to the output of a crystal oscillator (oscillator clock) or to the bus clock. The clock source has to be chosen such that the tight oscillator tolerance requirements (up to 0.4%) of the CAN protocol are met. Additionally, for high CAN bus rates (1 Mbps), a 45% to 55% duty cycle of the clock is required.
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If the bus clock is generated from a PLL, it is recommended to select the oscillator clock rather than the bus clock due to jitter considerations, especially at the faster CAN bus rates. For microcontrollers without a clock and reset generator (CRG), CANCLK is driven from the crystal oscillator (oscillator clock). A programmable prescaler generates the time quanta (Tq) clock from CANCLK. A time quantum is the atomic unit of time handled by the MSCAN.
Eqn. 12-2
f CANCLK = ----------------------------------------------------Tq ( Prescaler value ) A bit time is subdivided into three segments as described in the Bosch CAN specification. (see Figure 12-43): * SYNC_SEG: This segment has a fixed length of one time quantum. Signal edges are expected to happen within this section. * Time Segment 1: This segment includes the PROP_SEG and the PHASE_SEG1 of the CAN standard. It can be programmed by setting the parameter TSEG1 to consist of 4 to 16 time quanta. * Time Segment 2: This segment represents the PHASE_SEG2 of the CAN standard. It can be programmed by setting the TSEG2 parameter to be 2 to 8 time quanta long.
Eqn. 12-3
f Tq Bit Rate = -------------------------------------------------------------------------------( number of Time Quanta )
NRZ Signal
SYNC_SEG
Time Segment 1 (PROP_SEG + PHASE_SEG1) 4 ... 16 8 ... 25 Time Quanta = 1 Bit Time
Time Segment 2 (PHASE_SEG2) 2 ... 8
1
Transmit Point
Sample Point (single or triple sampling)
Figure 12-43. Segments within the Bit Time
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Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
Table 12-33. Time Segment Syntax
Syntax SYNC_SEG Transmit Point Description System expects transitions to occur on the CAN bus during this period. A node in transmit mode transfers a new value to the CAN bus at this point. A node in receive mode samples the CAN bus at this point. If the three samples per bit option is selected, then this point marks the position of the third sample.
Sample Point
The synchronization jump width (see the Bosch CAN specification for details) can be programmed in a range of 1 to 4 time quanta by setting the SJW parameter. The SYNC_SEG, TSEG1, TSEG2, and SJW parameters are set by programming the MSCAN bus timing registers (CANBTR0, CANBTR1) (see Section 12.3.2.3, "MSCAN Bus Timing Register 0 (CANBTR0)" and Section 12.3.2.4, "MSCAN Bus Timing Register 1 (CANBTR1)"). Table 12-34 gives an overview of the CAN compliant segment settings and the related parameter values. NOTE It is the user's responsibility to ensure the bit time settings are in compliance with the CAN standard.
Table 12-34. CAN Standard Compliant Bit Time Segment Settings
Time Segment 1 5 .. 10 4 .. 11 5 .. 12 6 .. 13 7 .. 14 8 .. 15 9 .. 16 TSEG1 4 .. 9 3 .. 10 4 .. 11 5 .. 12 6 .. 13 7 .. 14 8 .. 15 Time Segment 2 2 3 4 5 6 7 8 TSEG2 1 2 3 4 5 6 7 Synchronization Jump Width 1 .. 2 1 .. 3 1 .. 4 1 .. 4 1 .. 4 1 .. 4 1 .. 4 SJW 0 .. 1 0 .. 2 0 .. 3 0 .. 3 0 .. 3 0 .. 3 0 .. 3
12.4.4
12.4.4.1
Modes of Operation
Normal Modes
The MSCAN module behaves as described within this specification in all normal system operation modes.
12.4.4.2
Special Modes
The MSCAN module behaves as described within this specification in all special system operation modes.
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Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
12.4.4.3
Emulation Modes
In all emulation modes, the MSCAN module behaves just like normal system operation modes as described within this specification.
12.4.4.4
Listen-Only Mode
In an optional CAN bus monitoring mode (listen-only), the CAN node is able to receive valid data frames and valid remote frames, but it sends only "recessive" bits on the CAN bus. In addition, it cannot start a transmision. If the MAC sub-layer is required to send a "dominant" bit (ACK bit, overload flag, or active error flag), the bit is rerouted internally so that the MAC sub-layer monitors this "dominant" bit, although the CAN bus may remain in recessive state externally.
12.4.4.5
Security Modes
The MSCAN module has no security features.
12.4.5
Low-Power Options
If the MSCAN is disabled (CANE = 0), the MSCAN clocks are stopped for power saving. If the MSCAN is enabled (CANE = 1), the MSCAN has two additional modes with reduced power consumption, compared to normal mode: sleep and power down mode. In sleep mode, power consumption is reduced by stopping all clocks except those to access the registers from the CPU side. In power down mode, all clocks are stopped and no power is consumed. Table 12-35 summarizes the combinations of MSCAN and CPU modes. A particular combination of modes is entered by the given settings on the CSWAI and SLPRQ/SLPAK bits. For all modes, an MSCAN wake-up interrupt can occur only if the MSCAN is in sleep mode (SLPRQ = 1 and SLPAK = 1), wake-up functionality is enabled (WUPE = 1), and the wake-up interrupt is enabled (WUPIE = 1).
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Table 12-35. CPU vs. MSCAN Operating Modes
MSCAN Mode CPU Mode Normal Sleep CSWAI = X1 SLPRQ = 0 SLPAK = 0 CSWAI = 0 SLPRQ = 0 SLPAK = 0 CSWAI = X SLPRQ = 1 SLPAK = 1 CSWAI = 0 SLPRQ = 1 SLPAK = 1 CSWAI = 1 SLPRQ = X SLPAK = X CSWAI = X SLPRQ = X SLPAK = X Power Down Reduced Power Consumption Disabled (CANE=0) CSWAI = X SLPRQ = X SLPAK = X CSWAI = X SLPRQ = X SLPAK = X CSWAI = X SLPRQ = X SLPAK = X
RUN
WAIT
STOP
1
`X' means don't care.
12.4.5.1
Operation in Run Mode
As shown in Table 12-35, only MSCAN sleep mode is available as low power option when the CPU is in run mode.
12.4.5.2
Operation in Wait Mode
The WAI instruction puts the MCU in a low power consumption stand-by mode. If the CSWAI bit is set, additional power can be saved in power down mode because the CPU clocks are stopped. After leaving this power down mode, the MSCAN restarts its internal controllers and enters normal mode again. While the CPU is in wait mode, the MSCAN can be operated in normal mode and generate interrupts (registers can be accessed via background debug mode). The MSCAN can also operate in any of the low-power modes depending on the values of the SLPRQ/SLPAK and CSWAI bits as seen in Table 12-35.
12.4.5.3
Operation in Stop Mode
The STOP instruction puts the MCU in a low power consumption stand-by mode. In stop mode, the MSCAN is set in power down mode regardless of the value of the SLPRQ/SLPAK and CSWAI bits Table 12-35.
12.4.5.4
MSCAN Sleep Mode
The CPU can request the MSCAN to enter this low power mode by asserting the SLPRQ bit in the CANCTL0 register. The time when the MSCAN enters sleep mode depends on a fixed synchronization delay and its current activity:
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Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
*
* *
If there are one or more message buffers scheduled for transmission (TXEx = 0), the MSCAN will continue to transmit until all transmit message buffers are empty (TXEx = 1, transmitted successfully or aborted) and then goes into sleep mode. If the MSCAN is receiving, it continues to receive and goes into sleep mode as soon as the CAN bus next becomes idle. If the MSCAN is neither transmitting nor receiving, it immediately goes into sleep mode.
Bus Clock Domain
CAN Clock Domain SLPRQ Flag
SLPRQ CPU Sleep Request
SYNC
sync. SLPRQ
SLPAK Flag
sync.
SLPAK
SYNC
SLPAK MSCAN in Sleep Mode
Figure 12-44. Sleep Request / Acknowledge Cycle
NOTE The application software must avoid setting up a transmission (by clearing one or more TXEx flag(s)) and immediately request sleep mode (by setting SLPRQ). Whether the MSCAN starts transmitting or goes into sleep mode directly depends on the exact sequence of operations. If sleep mode is active, the SLPRQ and SLPAK bits are set (Figure 12-44). The application software must use SLPAK as a handshake indication for the request (SLPRQ) to go into sleep mode. When in sleep mode (SLPRQ = 1 and SLPAK = 1), the MSCAN stops its internal clocks. However, clocks that allow register accesses from the CPU side continue to run. If the MSCAN is in bus-off state, it stops counting the 128 occurrences of 11 consecutive recessive bits due to the stopped clocks. The TXCAN pin remains in a recessive state. If RXF = 1, the message can be read and RXF can be cleared. Shifting a new message into the foreground buffer of the receiver FIFO (RxFG) does not take place while in sleep mode. It is possible to access the transmit buffers and to clear the associated TXE flags. No message abort takes place while in sleep mode. If the WUPE bit in CANCLT0 is not asserted, the MSCAN will mask any activity it detects on CAN. The RXCAN pin is therefore held internally in a recessive state. This locks the MSCAN in sleep mode (Figure 12-45). WUPE must be set before entering sleep mode to take effect.
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The MSCAN is able to leave sleep mode (wake up) only when: * CAN bus activity occurs and WUPE = 1 or * the CPU clears the SLPRQ bit NOTE The CPU cannot clear the SLPRQ bit before sleep mode (SLPRQ = 1 and SLPAK = 1) is active. After wake-up, the MSCAN waits for 11 consecutive recessive bits to synchronize to the CAN bus. As a consequence, if the MSCAN is woken-up by a CAN frame, this frame is not received. The receive message buffers (RxFG and RxBG) contain messages if they were received before sleep mode was entered. All pending actions will be executed upon wake-up; copying of RxBG into RxFG, message aborts and message transmissions. If the MSCAN remains in bus-off state after sleep mode was exited, it continues counting the 128 occurrences of 11 consecutive recessive bits.
CAN Activity
StartUp
Wait for Idle
CAN Activity SLPRQ
(CAN Activity & WUPE) | SLPRQ
CAN Activity & SLPRQ
Idle
Sleep
(CAN Activity & WUPE) |
CAN Activity & SLPRQ
CAN Activity CAN Activity
Tx/Rx Message Active
CAN Activity
Figure 12-45. Simplified State Transitions for Entering/Leaving Sleep Mode
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 393
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
12.4.5.5
MSCAN Initialization Mode
In initialization mode, any on-going transmission or reception is immediately aborted and synchronization to the CAN bus is lost, potentially causing CAN protocol violations. To protect the CAN bus system from fatal consequences of violations, the MSCAN immediately drives the TXCAN pin into a recessive state. NOTE The user is responsible for ensuring that the MSCAN is not active when initialization mode is entered. The recommended procedure is to bring the MSCAN into sleep mode (SLPRQ = 1 and SLPAK = 1) before setting the INITRQ bit in the CANCTL0 register. Otherwise, the abort of an on-going message can cause an error condition and can impact other CAN bus devices. In initialization mode, the MSCAN is stopped. However, interface registers remain accessible. This mode is used to reset the CANCTL0, CANRFLG, CANRIER, CANTFLG, CANTIER, CANTARQ, CANTAAK, and CANTBSEL registers to their default values. In addition, the MSCAN enables the configuration of the CANBTR0, CANBTR1 bit timing registers; CANIDAC; and the CANIDAR, CANIDMR message filters. See Section 12.3.2.1, "MSCAN Control Register 0 (CANCTL0)," for a detailed description of the initialization mode.
Bus Clock Domain
CAN Clock Domain INIT Flag
INITRQ CPU Init Request
SYNC
sync. INITRQ
INITAK Flag
sync.
INITAK
SYNC
INITAK
Figure 12-46. Initialization Request/Acknowledge Cycle
Due to independent clock domains within the MSCAN, INITRQ must be synchronized to all domains by using a special handshake mechanism. This handshake causes additional synchronization delay (see Section Figure 12-46., "Initialization Request/Acknowledge Cycle"). If there is no message transfer ongoing on the CAN bus, the minimum delay will be two additional bus clocks and three additional CAN clocks. When all parts of the MSCAN are in initialization mode, the INITAK flag is set. The application software must use INITAK as a handshake indication for the request (INITRQ) to go into initialization mode. NOTE The CPU cannot clear INITRQ before initialization mode (INITRQ = 1 and INITAK = 1) is active.
MC3S12RG128 Data Sheet, Rev. 1.05 394 Freescale Semiconductor
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
12.4.5.6
MSCAN Power Down Mode
The MSCAN is in power down mode (Table 12-35) when * CPU is in stop mode or * CPU is in wait mode and the CSWAI bit is set When entering the power down mode, the MSCAN immediately stops all ongoing transmissions and receptions, potentially causing CAN protocol violations. To protect the CAN bus system from fatal consequences of violations to the above rule, the MSCAN immediately drives the TXCAN pin into a recessive state. NOTE The user is responsible for ensuring that the MSCAN is not active when power down mode is entered. The recommended procedure is to bring the MSCAN into Sleep mode before the STOP or WAI instruction (if CSWAI is set) is executed. Otherwise, the abort of an ongoing message can cause an error condition and impact other CAN bus devices. In power down mode, all clocks are stopped and no registers can be accessed. If the MSCAN was not in sleep mode before power down mode became active, the module performs an internal recovery cycle after powering up. This causes some fixed delay before the module enters normal mode again.
12.4.5.7
Programmable Wake-Up Function
The MSCAN can be programmed to wake up the MSCAN as soon as CAN bus activity is detected (see control bit WUPE in Section 12.3.2.1, "MSCAN Control Register 0 (CANCTL0)"). The sensitivity to existing CAN bus action can be modified by applying a low-pass filter function to the RXCAN input line while in sleep mode (see control bit WUPM in Section 12.3.2.2, "MSCAN Control Register 1 (CANCTL1)"). This feature can be used to protect the MSCAN from wake-up due to short glitches on the CAN bus lines. Such glitches can result from--for example--electromagnetic interference within noisy environments.
12.4.6
Reset Initialization
The reset state of each individual bit is listed in Section 12.3.2, "Register Descriptions," which details all the registers and their bit-fields.
12.4.7
Interrupts
This section describes all interrupts originated by the MSCAN. It documents the enable bits and generated flags. Each interrupt is listed and described separately.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 395
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
12.4.7.1
Description of Interrupt Operation
The MSCAN supports four interrupt vectors (see Table 12-36), any of which can be individually masked (for details see sections from Section 12.3.2.6, "MSCAN Receiver Interrupt Enable Register (CANRIER)," to Section 12.3.2.8, "MSCAN Transmitter Interrupt Enable Register (CANTIER)"). NOTE The dedicated interrupt vector addresses are defined in the Resets and Interrupts chapter.
Table 12-36. Interrupt Vectors
Interrupt Source Wake-Up Interrupt (WUPIF) Error Interrupts Interrupt (CSCIF, OVRIF) Receive Interrupt (RXF) Transmit Interrupts (TXE[2:0]) CCR Mask I bit I bit I bit I bit Local Enable CANRIER (WUPIE) CANRIER (CSCIE, OVRIE) CANRIER (RXFIE) CANTIER (TXEIE[2:0])
12.4.7.2
Transmit Interrupt
At least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message for transmission. The TXEx flag of the empty message buffer is set.
12.4.7.3
Receive Interrupt
A message is successfully received and shifted into the foreground buffer (RxFG) of the receiver FIFO. This interrupt is generated immediately after receiving the EOF symbol. The RXF flag is set. If there are multiple messages in the receiver FIFO, the RXF flag is set as soon as the next message is shifted to the foreground buffer.
12.4.7.4
Wake-Up Interrupt
A wake-up interrupt is generated if activity on the CAN bus occurs during MSCN internal sleep mode. WUPE (see Section 12.3.2.1, "MSCAN Control Register 0 (CANCTL0)") must be enabled.
12.4.7.5
Error Interrupt
An error interrupt is generated if an overrun of the receiver FIFO, error, warning, or bus-off condition occurrs. Section 12.3.2.5, "MSCAN Receiver Flag Register (CANRFLG) indicates one of the following conditions: * Overrun -- An overrun condition of the receiver FIFO as described in Section 12.4.2.3, "Receive Structures," occurred. * CAN Status Change -- The actual value of the transmit and receive error counters control the CAN bus state of the MSCAN. As soon as the error counters skip into a critical range (Tx/Rx-warning, Tx/Rx-error, bus-off) the MSCAN flags an error condition. The status change, which caused the error condition, is indicated by the TSTAT and RSTAT flags (see
MC3S12RG128 Data Sheet, Rev. 1.05 396 Freescale Semiconductor
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
Section 12.3.2.5, "MSCAN Receiver Flag Register (CANRFLG)" and Section 12.3.2.6, "MSCAN Receiver Interrupt Enable Register (CANRIER)").
12.4.7.6
Interrupt Acknowledge
Interrupts are directly associated with one or more status flags in either the Section 12.3.2.5, "MSCAN Receiver Flag Register (CANRFLG)" or the Section 12.3.2.7, "MSCAN Transmitter Flag Register (CANTFLG)." Interrupts are pending as long as one of the corresponding flags is set. The flags in CANRFLG and CANTFLG must be reset within the interrupt handler to handshake the interrupt. The flags are reset by writing a 1 to the corresponding bit position. A flag cannot be cleared if the respective condition prevails. NOTE It must be guaranteed that the CPU clears only the bit causing the current interrupt. For this reason, bit manipulation instructions (BSET) must not be used to clear interrupt flags. These instructions may cause accidental clearing of interrupt flags which are set after entering the current interrupt service routine.
12.4.7.7
Recovery from Stop or Wait
The MSCAN can recover from stop or wait via the wake-up interrupt. This interrupt can only occur if the MSCAN was in sleep mode (SLPRQ = 1 and SLPAK = 1) before entering power down mode, the wake-up option is enabled (WUPE = 1), and the wake-up interrupt is enabled (WUPIE = 1).
12.5
12.5.1
Initialization/Application Information
MSCAN initialization
The procedure to initially start up the MSCAN module out of reset is as follows: 1. Assert CANE 2. Write to the configuration registers in initialization mode 3. Clear INITRQ to leave initialization mode and enter normal mode If the configuration of registers which are writable in initialization mode needs to be changed only when the MSCAN module is in normal mode: 1. Bring the module into sleep mode by setting SLPRQ and awaiting SLPAK to assert after the CAN bus becomes idle. 2. Enter initialization mode: assert INITRQ and await INITAK 3. Write to the configuration registers in initialization mode 4. Clear INITRQ to leave initialization mode and continue in normal mode
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 397
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
MC3S12RG128 Data Sheet, Rev. 1.05 398 Freescale Semiconductor
Chapter 13 Oscillator (OSCV2) Block Description
13.1 Introduction
The OSC module provides two alternative oscillator concepts: * A low noise and low power Colpitts oscillator with amplitude limitation control (ALC) * A robust full swing Pierce oscillator with the possibility to feed in an external square wave
13.1.1
Features
The Colpitts OSC option provides the following features: * Amplitude limitation control (ALC) loop: -- Low power consumption and low current induced RF emission -- Sinusoidal waveform with low RF emission -- Low crystal stress (an external damping resistor is not required) -- Normal and low amplitude mode for further reduction of power and emission * An external biasing resistor is not required The Pierce OSC option provides the following features: * Wider high frequency operation range * No DC voltage applied across the crystal * Full rail-to-rail (2.5 V nominal) swing oscillation with low EM susceptibility * Fast start up Common features: * Clock monitor (CM) * Operation from the VDDPLL 2.5 V (nominal) supply rail
13.1.2
Modes of Operation
Two modes of operation exist: * Amplitude limitation controlled Colpitts oscillator mode suitable for power and emission critical applications * Full swing Pierce oscillator mode that can also be used to feed in an externally generated square wave suitable for high frequency operation and harsh environments
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 399
Chapter 13 Oscillator (OSCV2) Block Description
13.2
External Signal Description
This section lists and describes the signals that connect off chip.
13.2.1
VDDPLL and VSSPLL -- PLL Operating Voltage, PLL Ground
These pins provide the operating voltage (VDDPLL) and ground (VSSPLL) for the OSC circuitry. This allows the supply voltage to the OSC to be independently bypassed.
13.2.2
EXTAL and XTAL -- Clock/Crystal Source Pins
These pins provide the interface for either a crystal or a CMOS compatible clock to control the internal clock generator circuitry. EXTAL is the external clock input or the input to the crystal oscillator amplifier. XTAL is the output of the crystal oscillator amplifier. All the MCU internal system clocks are derived from the EXTAL input frequency. In full stop mode (PSTP = 0) the EXTAL pin is pulled down by an internal resistor of typical 200 k. NOTE Freescale Semiconductor recommends an evaluation of the application board and chosen resonator or crystal by the resonator or crystal supplier. The Crystal circuit is changed from standard. The Colpitts circuit is not suited for overtone resonators and crystals.
EXTAL CDC* MCU XTAL C2 VSSPLL * Due to the nature of a translated ground Colpitts oscillator a DC voltage bias is applied to the crystal. Please contact the crystal manufacturer for crystal DC bias conditions and recommended capacitor value CDC. C1 Crystal or Ceramic Resonator
Figure 13-1. Colpitts Oscillator Connections (XCLKS = 0)
NOTE The Pierce circuit is not suited for overtone resonators and crystals without a careful component selection.
MC3S12RG128 Data Sheet, Rev. 1.05 400 Freescale Semiconductor
Chapter 13 Oscillator (OSCV2) Block Description
EXTAL MCU RS* XTAL C4 VSSPLL * Rs can be zero (shorted) when used with higher frequency crystals. Refer to manufacturer's data. C3 Crystal or Ceramic Resonator
RB
Figure 13-2. Pierce Oscillator Connections (XCLKS = 1)
EXTAL MCU XTAL
CMOS-Compatible External Oscillator (VDDPLL Level)
Not Connected
Figure 13-3. External Clock Connections (XCLKS = 1)
13.2.3
XCLKS -- Colpitts/Pierce Oscillator Selection Signal
The XCLKS is an input signal which controls whether a crystal in combination with the internal Colpitts (low power) oscillator is used or whether the Pierce oscillator/external clock circuitry is used. The XCLKS signal is sampled during reset with the rising edge of RESET. Table 13-1 lists the state coding of the sampled XCLKS signal. Refer to the device overview chapter for polarity of the XCLKS pin.
Table 13-1. Clock Selection Based on XCLKS XCLKS
0 1
Description
Colpitts oscillator selected Pierce oscillator/external clock selected
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 401
Chapter 13 Oscillator (OSCV2) Block Description
13.3
Memory Map and Register Definition
The CRG contains the registers and associated bits for controlling and monitoring the OSC module.
13.4
Functional Description
The OSC block has two external pins, EXTAL and XTAL. The oscillator input pin, EXTAL, is intended to be connected to either a crystal or an external clock source. The selection of Colpitts oscillator or Pierce oscillator/external clock depends on the XCLKS signal which is sampled during reset. The XTAL pin is an output signal that provides crystal circuit feedback. A buffered EXTAL signal, OSCCLK, becomes the internal reference clock. To improve noise immunity, the oscillator is powered by the VDDPLL and VSSPLL power supply pins. The Pierce oscillator can be used for higher frequencies compared to the low power Colpitts oscillator.
13.4.1
Amplitude Limitation Control (ALC)
The Colpitts oscillator is equipped with a feedback system which does not waste current by generating harmonics. Its configuration is "Colpitts oscillator with translated ground." The transconductor used is driven by a current source under the control of a peak detector which will measure the amplitude of the AC signal appearing on EXTAL node in order to implement an amplitude limitation control (ALC) loop. The ALC loop is in charge of reducing the quiescent current in the transconductor as a result of an increase in the oscillation amplitude. The oscillation amplitude can be limited to two values. The normal amplitude which is intended for non power saving modes and a small amplitude which is intended for low power operation modes. Please refer to the CRG block description chapter for the control and assignment of the amplitude value to operation modes.
13.4.2
Clock Monitor (CM)
The clock monitor circuit is based on an internal resistor-capacitor (RC) time delay so that it can operate without any MCU clocks. If no OSCCLK edges are detected within this RC time delay, the clock monitor indicates a failure which asserts self clock mode or generates a system reset depending on the state of SCME bit. If the clock monitor is disabled or the presence of clocks is detected no failure is indicated.The clock monitor function is enabled/disabled by the CME control bit, described in the CRG block description chapter.
13.5
Interrupts
OSC contains a clock monitor, which can trigger an interrupt or reset. The control bits and status bits for the clock monitor are described in the CRG block description chapter.
MC3S12RG128 Data Sheet, Rev. 1.05 402 Freescale Semiconductor
Chapter 14 Pulse-Width Modulator (PWM8B8CV1)
14.1 Introduction
The PWM definition is based on the HC12 PWM definitions. It contains the basic features from the HC11 with some of the enhancements incorporated on the HC12: center aligned output mode and four available clock sources.The PWM module has eight channels with independent control of left and center aligned outputs on each channel. Each of the eight channels has a programmable period and duty cycle as well as a dedicated counter. A flexible clock select scheme allows a total of four different clock sources to be used with the counters. Each of the modulators can create independent continuous waveforms with software-selectable duty rates from 0% to 100%. The PWM outputs can be programmed as left aligned outputs or center aligned outputs.
14.1.1
Features
The PWM block includes these distinctive features: * Eight independent PWM channels with programmable period and duty cycle * Dedicated counter for each PWM channel * Programmable PWM enable/disable for each channel * Software selection of PWM duty pulse polarity for each channel * Period and duty cycle are double buffered. Change takes effect when the end of the effective period is reached (PWM counter reaches zero) or when the channel is disabled. * Programmable center or left aligned outputs on individual channels * Eight 8-bit channel or four 16-bit channel PWM resolution * Four clock sources (A, B, SA, and SB) provide for a wide range of frequencies * Programmable clock select logic * Emergency shutdown
14.1.2
Modes of Operation
There is a software programmable option for low power consumption in wait mode that disables the input clock to the prescaler. In freeze mode there is a software programmable option to disable the input clock to the prescaler. This is useful for emulation.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 403
Chapter 14 Pulse-Width Modulator (PWM8B8CV1)
14.1.3
Block Diagram
Figure 14-1 shows the block diagram for the 8-bit 8-channel PWM block.
PWM8B8C
PWM Channels Channel 7 Period and Duty Channel 6 Counter PWM7
PWM6 Counter
Bus Clock
Clock Select
PWM Clock
Period and Duty
Channel 5 Period and Duty Control Channel 4 Period and Duty Counter Counter
PWM5
PWM4
Channel 3 Enable Period and Duty Counter
PWM3
Polarity
Channel 2 Period and Duty Counter
PWM2
Alignment
Channel 1 Period and Duty Channel 0 Period and Duty Counter Counter
PWM1
PWM0
Figure 14-1. PWM Block Diagram
14.2
External Signal Description
The PWM module has a total of 8 external pins.
14.2.1
PWM7 -- PWM Channel 7
This pin serves as waveform output of PWM channel 7 and as an input for the emergency shutdown feature.
14.2.2
PWM6 -- PWM Channel 6
This pin serves as waveform output of PWM channel 6.
MC3S12RG128 Data Sheet, Rev. 1.05 404 Freescale Semiconductor
Chapter 14 Pulse-Width Modulator (PWM8B8CV1)
14.2.3
PWM5 -- PWM Channel 5
This pin serves as waveform output of PWM channel 5.
14.2.4
PWM4 -- PWM Channel 4
This pin serves as waveform output of PWM channel 4.
14.2.5
PWM3 -- PWM Channel 3
This pin serves as waveform output of PWM channel 3.
14.2.6
PWM3 -- PWM Channel 2
This pin serves as waveform output of PWM channel 2.
14.2.7
PWM3 -- PWM Channel 1
This pin serves as waveform output of PWM channel 1.
14.2.8
PWM3 -- PWM Channel 0
This pin serves as waveform output of PWM channel 0.
14.3
Memory Map and Register Definition
This section describes in detail all the registers and register bits in the PWM module. The special-purpose registers and register bit functions that are not normally available to device end users, such as factory test control registers and reserved registers, are clearly identified by means of shading the appropriate portions of address maps and register diagrams. Notes explaining the reasons for restricting access to the registers and functions are also explained in the individual register descriptions.
14.3.1
Module Memory Map
This section describes the content of the registers in the PWM module. The base address of the PWM module is determined at the MCU level when the MCU is defined. The register decode map is fixed and begins at the first address of the module address offset. The figure below shows the registers associated with the PWM and their relative offset from the base address. The register detail description follows the order they appear in the register map. Reserved bits within a register will always read as 0 and the write will be unimplemented. Unimplemented functions are indicated by shading the bit. .
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 405
Chapter 14 Pulse-Width Modulator (PWM8B8CV1)
NOTE Register Address = Base Address + Address Offset, where the Base Address is defined at the MCU level and the Address Offset is defined at the module level.
14.3.2
Register Descriptions
This section describes in detail all the registers and register bits in the PWM module.
Register Name 0x0000 PWME 0x0001 PWMPOL 0x0002 PWMCLK R W R W R W Bit 7 PWME7 6 PWME6 5 PWME5 4 PWME4 3 PWME3 2 PWME2 1 PWME1 Bit 0 PWME0
PPOL7
PPOL6
PPOL5
PPOL4
PPOL3
PPOL2
PPOL1
PPOL0
PCLK7 0
PCLKL6
PCLK5
PCLK4
PCLK3 0
PCLK2
PCLK1
PCLK0
0x0003 R PWMPRCLK W 0x0004 PWMCAE 0x0005 PWMCTL 0x0006 PWMTST1 R W R W R W
PCKB2
PCKB1
PCKB0
PCKA2
PCKA1
PCKA0
CAE7
CAE6
CAE5
CAE4
CAE3
CAE2
CAE1 0
CAE0 0
CON67 0
CON45 0
CON23 0
CON01 0
PSWAI 0
PFRZ 0
0
0
0x0007 R PWMPRSC1 W 0x0008 R PWMSCLA W 0x0009 R PWMSCLB W 0x000A R PWMSCNTA W 1
0
0
0
0
0
0
0
0
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7 0
6 0
5 0
4 0
3 0
2 0
1 0
Bit 0 0
= Unimplemented or Reserved
Figure 14-2. PWM Register Summary (Sheet 1 of 3)
MC3S12RG128 Data Sheet, Rev. 1.05 406 Freescale Semiconductor
Chapter 14 Pulse-Width Modulator (PWM8B8CV1)
Register Name R 0x000B PWMSCNTB W 1 0x000C R PWMCNT0 W 0x000D R PWMCNT1 W 0x000E R PWMCNT2 W 0x000F R PWMCNT3 W 0x0010 R PWMCNT4 W 0x0011 R PWMCNT5 W 0x0012 R PWMCNT6 W 0x0013 R PWMCNT7 W 0x0014 R PWMPER0 W 0x0015 R PWMPER1 W 0x0016 R PWMPER2 W 0x0017 R PWMPER3 W 0x0018 R PWMPER4 W 0x0019 R PWMPER5 W
Bit 7 0
6 0
5 0
4 0
3 0
2 0
1 0
Bit 0 0
Bit 7 0 Bit 7 0 Bit 7 0 Bit 7 0 Bit 7 0 Bit 7 0 Bit 7 0 Bit 7 0 Bit 7
6 0 6 0 6 0 6 0 6 0 6 0 6 0 6 0 6
5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5
4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4
3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3
2 0 2 0 2 0 2 0 2 0 2 0 2 0 2 0 2
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
= Unimplemented or Reserved
Figure 14-2. PWM Register Summary (Sheet 2 of 3)
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 407
Chapter 14 Pulse-Width Modulator (PWM8B8CV1)
Register Name 0x001A R PWMPER6 W 0x001B R PWMPER7 W 0x001C R PWMDTY0 W 0x001D R PWMDTY1 W 0x001E R PWMDTY2 W 0x001F R PWMDTY3 W 0x0010 R PWMDTY4 W 0x0021 R PWMDTY5 W 0x0022 R PWMDTY6 W 0x0023 R PWMDTY7 W 0x0024 PWMSDN R W
Bit 7 Bit 7
6 6
5 5
4 4
3 3
2 2
1 1
Bit 0 Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5 0 PWMRSTRT
4
3 0
2 PWM7IN
1
Bit 0
PWMIF
PWMIE
PWMLVL
PWM7INL
PWM7ENA
= Unimplemented or Reserved
Figure 14-2. PWM Register Summary (Sheet 3 of 3)
1
Intended for factory test purposes only.
14.3.2.1
PWM Enable Register (PWME)
Each PWM channel has an enable bit (PWMEx) to start its waveform output. When any of the PWMEx bits are set (PWMEx = 1), the associated PWM output is enabled immediately. However, the actual PWM waveform is not available on the associated PWM output until its clock source begins its next cycle due to the synchronization of PWMEx and the clock source. NOTE The first PWM cycle after enabling the channel can be irregular.
MC3S12RG128 Data Sheet, Rev. 1.05 408 Freescale Semiconductor
Chapter 14 Pulse-Width Modulator (PWM8B8CV1)
An exception to this is when channels are concatenated. Once concatenated mode is enabled (CONxx bits set in PWMCTL register), enabling/disabling the corresponding 16-bit PWM channel is controlled by the low order PWMEx bit.In this case, the high order bytes PWMEx bits have no effect and their corresponding PWM output lines are disabled. While in run mode, if all eight PWM channels are disabled (PWME7-0 = 0), the prescaler counter shuts off for power savings.
Module Base + 0x0000
7 6 5 4 3 2 1 0
R W Reset
PWME7 0
PWME6 0
PWME5 0
PWME4 0
PWME3 0
PWME2 0
PWME1 0
PWME0 0
Figure 14-3. PWM Enable Register (PWME)
Read: Anytime Write: Anytime
Table 14-1. PWME Field Descriptions
Field 7 PWME7 Description Pulse Width Channel 7 Enable 0 Pulse width channel 7 is disabled. 1 Pulse width channel 7 is enabled. The pulse modulated signal becomes available at PWM output bit 7 when its clock source begins its next cycle. Pulse Width Channel 6 Enable 0 Pulse width channel 6 is disabled. 1 Pulse width channel 6 is enabled. The pulse modulated signal becomes available at PWM output bit6 when its clock source begins its next cycle. If CON67=1, then bit has no effect and PWM output line 6 is disabled. Pulse Width Channel 5 Enable 0 Pulse width channel 5 is disabled. 1 Pulse width channel 5 is enabled. The pulse modulated signal becomes available at PWM output bit 5 when its clock source begins its next cycle. Pulse Width Channel 4 Enable 0 Pulse width channel 4 is disabled. 1 Pulse width channel 4 is enabled. The pulse modulated signal becomes available at PWM, output bit 4 when its clock source begins its next cycle. If CON45 = 1, then bit has no effect and PWM output bit4 is disabled. Pulse Width Channel 3 Enable 0 Pulse width channel 3 is disabled. 1 Pulse width channel 3 is enabled. The pulse modulated signal becomes available at PWM, output bit 3 when its clock source begins its next cycle. Pulse Width Channel 2 Enable 0 Pulse width channel 2 is disabled. 1 Pulse width channel 2 is enabled. The pulse modulated signal becomes available at PWM, output bit 2 when its clock source begins its next cycle. If CON23 = 1, then bit has no effect and PWM output bit2 is disabled.
6 PWME6
5 PWME5
4 PWME4
3 PWME3
2 PWME2
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 409
Chapter 14 Pulse-Width Modulator (PWM8B8CV1)
Table 14-1. PWME Field Descriptions (continued)
Field 1 PWME1 Description Pulse Width Channel 1 Enable 0 Pulse width channel 1 is disabled. 1 Pulse width channel 1 is enabled. The pulse modulated signal becomes available at PWM, output bit 1 when its clock source begins its next cycle. Pulse Width Channel 0 Enable 0 Pulse width channel 0 is disabled. 1 Pulse width channel 0 is enabled. The pulse modulated signal becomes available at PWM, output bit 0 when its clock source begins its next cycle. If CON01 = 1, then bit has no effect and PWM output line0 is disabled.
0 PWME0
14.3.2.2
PWM Polarity Register (PWMPOL)
The starting polarity of each PWM channel waveform is determined by the associated PPOLx bit in the PWMPOL register. If the polarity bit is one, the PWM channel output is high at the beginning of the cycle and then goes low when the duty count is reached. Conversely, if the polarity bit is zero, the output starts low and then goes high when the duty count is reached.
Module Base + 0x0001
7 6 5 4 3 2 1 0
R W Reset
PPOL7 0
PPOL6 0
PPOL5 0
PPOL4 0
PPOL3 0
PPOL2 0
PPOL1 0
PPOL0 0
Figure 14-4. PWM Polarity Register (PWMPOL)
Read: Anytime Write: Anytime NOTE PPOLx register bits can be written anytime. If the polarity is changed while a PWM signal is being generated, a truncated or stretched pulse can occur during the transition
Table 14-2. PWMPOL Field Descriptions
Field 7-0 PPOL[7:0] Description Pulse Width Channel 7-0 Polarity Bits 0 PWM channel 7-0 outputs are low at the beginning of the period, then go high when the duty count is reached. 1 PWM channel 7-0 outputs are high at the beginning of the period, then go low when the duty count is reached.
14.3.2.3
PWM Clock Select Register (PWMCLK)
Each PWM channel has a choice of two clocks to use as the clock source for that channel as described below.
MC3S12RG128 Data Sheet, Rev. 1.05 410 Freescale Semiconductor
Chapter 14 Pulse-Width Modulator (PWM8B8CV1)
Module Base + 0x0002
7 6 5 4 3 2 1 0
R W Reset
PCLK7 0
PCLKL6 0
PCLK5 0
PCLK4 0
PCLK3 0
PCLK2 0
PCLK1 0
PCLK0 0
Figure 14-5. PWM Clock Select Register (PWMCLK)
Read: Anytime Write: Anytime NOTE Register bits PCLK0 to PCLK7 can be written anytime. If a clock select is changed while a PWM signal is being generated, a truncated or stretched pulse can occur during the transition.
Table 14-3. PWMCLK Field Descriptions
Field 7 PCLK7 6 PCLK6 5 PCLK5 4 PCLK4 3 PCLK3 2 PCLK2 1 PCLK1 0 PCLK0 Description Pulse Width Channel 7 Clock Select 0 Clock B is the clock source for PWM channel 7. 1 Clock SB is the clock source for PWM channel 7. Pulse Width Channel 6 Clock Select 0 Clock B is the clock source for PWM channel 6. 1 Clock SB is the clock source for PWM channel 6. Pulse Width Channel 5 Clock Select 0 Clock A is the clock source for PWM channel 5. 1 Clock SA is the clock source for PWM channel 5. Pulse Width Channel 4 Clock Select 0 Clock A is the clock source for PWM channel 4. 1 Clock SA is the clock source for PWM channel 4. Pulse Width Channel 3 Clock Select 0 Clock B is the clock source for PWM channel 3. 1 Clock SB is the clock source for PWM channel 3. Pulse Width Channel 2 Clock Select 0 Clock B is the clock source for PWM channel 2. 1 Clock SB is the clock source for PWM channel 2. Pulse Width Channel 1 Clock Select 0 Clock A is the clock source for PWM channel 1. 1 Clock SA is the clock source for PWM channel 1. Pulse Width Channel 0 Clock Select 0 Clock A is the clock source for PWM channel 0. 1 Clock SA is the clock source for PWM channel 0.
14.3.2.4
PWM Prescale Clock Select Register (PWMPRCLK)
This register selects the prescale clock source for clocks A and B independently.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 411
Chapter 14 Pulse-Width Modulator (PWM8B8CV1)
Module Base + 0x0003
7 6 5 4 3 2 1 0
R W Reset
0 0
PCKB2 0
PCKB1 0
PCKB0 0
0 0
PCKA2 0
PCKA1 0
PCKA0 0
= Unimplemented or Reserved
Figure 14-6. PWM Prescale Clock Select Register (PWMPRCLK)
Read: Anytime Write: Anytime NOTE PCKB2-0 and PCKA2-0 register bits can be written anytime. If the clock pre-scale is changed while a PWM signal is being generated, a truncated or stretched pulse can occur during the transition.
Table 14-4. PWMPRCLK Field Descriptions
Field 6-4 PCKB[2:0] 2-0 PCKA[2:0]
s
Description Prescaler Select for Clock B -- Clock B is one of two clock sources which can be used for channels 2, 3, 6, or 7. These three bits determine the rate of clock B, as shown in Table 14-5. Prescaler Select for Clock A -- Clock A is one of two clock sources which can be used for channels 0, 1, 4 or 5. These three bits determine the rate of clock A, as shown in Table 14-6.
Table 14-5. Clock B Prescaler Selects
PCKB2 0 0 0 0 1 1 1 1 PCKB1 0 0 1 1 0 0 1 1 PCKB0 0 1 0 1 0 1 0 1 Value of Clock B Bus clock Bus clock / 2 Bus clock / 4 Bus clock / 8 Bus clock / 16 Bus clock / 32 Bus clock / 64 Bus clock / 128
Table 14-6. Clock A Prescaler Selects
PCKA2 0 0 0 0 1 1 1 1 PCKA1 0 0 1 1 0 0 1 1 PCKA0 0 1 0 1 0 1 0 1 Value of Clock A Bus clock Bus clock / 2 Bus clock / 4 Bus clock / 8 Bus clock / 16 Bus clock / 32 Bus clock / 64 Bus clock / 128
MC3S12RG128 Data Sheet, Rev. 1.05 412 Freescale Semiconductor
Chapter 14 Pulse-Width Modulator (PWM8B8CV1)
14.3.2.5
PWM Center Align Enable Register (PWMCAE)
The PWMCAE register contains eight control bits for the selection of center aligned outputs or left aligned outputs for each PWM channel. If the CAEx bit is set to a one, the corresponding PWM output will be center aligned. If the CAEx bit is cleared, the corresponding PWM output will be left aligned. See Section 14.4.2.5, "Left Aligned Outputs" and Section 14.4.2.6, "Center Aligned Outputs" for a more detailed description of the PWM output modes.
Module Base + 0x0004
7 6 5 4 3 2 1 0
R W Reset
CAE7 0
CAE6 0
CAE5 0
CAE4 0
CAE3 0
CAE2 0
CAE1 0
CAE0 0
Figure 14-7. PWM Center Align Enable Register (PWMCAE)
Read: Anytime Write: Anytime NOTE Write these bits only when the corresponding channel is disabled.
Table 14-7. PWMCAE Field Descriptions
Field 7-0 CAE[7:0] Description Center Aligned Output Modes on Channels 7-0 0 Channels 7-0 operate in left aligned output mode. 1 Channels 7-0 operate in center aligned output mode.
14.3.2.6
PWM Control Register (PWMCTL)
The PWMCTL register provides for various control of the PWM module.
Module Base + 0x0005
7 6 5 4 3 2 1 0
R W Reset
CON67 0
CON45 0
CON23 0
CON01 0
PSWAI 0
PFRZ 0
0 0
0 0
= Unimplemented or Reserved
Figure 14-8. PWM Control Register (PWMCTL)
Read: Anytime Write: Anytime There are three control bits for concatenation, each of which is used to concatenate a pair of PWM channels into one 16-bit channel. When channels 6 and 7are concatenated, channel 6 registers become the high order bytes of the double byte channel. When channels 4 and 5 are concatenated, channel 4 registers become the high order bytes of the double byte channel. When channels 2 and 3 are concatenated, channel
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 413
Chapter 14 Pulse-Width Modulator (PWM8B8CV1)
2 registers become the high order bytes of the double byte channel. When channels 0 and 1 are concatenated, channel 0 registers become the high order bytes of the double byte channel. See Section 14.4.2.7, "PWM 16-Bit Functions" for a more detailed description of the concatenation PWM Function. NOTE Change these bits only when both corresponding channels are disabled.
Table 14-8. PWMCTL Field Descriptions
Field 7 CON67 Description Concatenate Channels 6 and 7 0 Channels 6 and 7 are separate 8-bit PWMs. 1 Channels 6 and 7 are concatenated to create one 16-bit PWM channel. Channel 6 becomes the high order byte and channel 7 becomes the low order byte. Channel 7 output pin is used as the output for this 16-bit PWM (bit 7 of port PWMP). Channel 7 clock select control-bit determines the clock source, channel 7 polarity bit determines the polarity, channel 7 enable bit enables the output and channel 7 center aligned enable bit determines the output mode. Concatenate Channels 4 and 5 0 Channels 4 and 5 are separate 8-bit PWMs. 1 Channels 4 and 5 are concatenated to create one 16-bit PWM channel. Channel 4 becomes the high order byte and channel 5 becomes the low order byte. Channel 5 output pin is used as the output for this 16-bit PWM (bit 5 of port PWMP). Channel 5 clock select control-bit determines the clock source, channel 5 polarity bit determines the polarity, channel 5 enable bit enables the output and channel 5 center aligned enable bit determines the output mode. Concatenate Channels 2 and 3 0 Channels 2 and 3 are separate 8-bit PWMs. 1 Channels 2 and 3 are concatenated to create one 16-bit PWM channel. Channel 2 becomes the high order byte and channel 3 becomes the low order byte. Channel 3 output pin is used as the output for this 16-bit PWM (bit 3 of port PWMP). Channel 3 clock select control-bit determines the clock source, channel 3 polarity bit determines the polarity, channel 3 enable bit enables the output and channel 3 center aligned enable bit determines the output mode. Concatenate Channels 0 and 1 0 Channels 0 and 1 are separate 8-bit PWMs. 1 Channels 0 and 1 are concatenated to create one 16-bit PWM channel. Channel 0 becomes the high order byte and channel 1 becomes the low order byte. Channel 1 output pin is used as the output for this 16-bit PWM (bit 1 of port PWMP). Channel 1 clock select control-bit determines the clock source, channel 1 polarity bit determines the polarity, channel 1 enable bit enables the output and channel 1 center aligned enable bit determines the output mode. PWM Stops in Wait Mode -- Enabling this bit allows for lower power consumption in wait mode by disabling the input clock to the prescaler. 0 Allow the clock to the prescaler to continue while in wait mode. 1 Stop the input clock to the prescaler whenever the MCU is in wait mode. PWM Counters Stop in Freeze Mode -- In freeze mode, there is an option to disable the input clock to the prescaler by setting the PFRZ bit in the PWMCTL register. If this bit is set, whenever the MCU is in freeze mode, the input clock to the prescaler is disabled. This feature is useful during emulation as it allows the PWM function to be suspended. In this way, the counters of the PWM can be stopped while in freeze mode so that once normal program flow is continued, the counters are re-enabled to simulate real-time operations. Since the registers can still be accessed in this mode, to re-enable the prescaler clock, either disable the PFRZ bit or exit freeze mode. 0 Allow PWM to continue while in freeze mode. 1 Disable PWM input clock to the prescaler whenever the part is in freeze mode. This is useful for emulation.
6 CON45
5 CON23
4 CON01
3 PSWAI
2 PFREZ
MC3S12RG128 Data Sheet, Rev. 1.05 414 Freescale Semiconductor
Chapter 14 Pulse-Width Modulator (PWM8B8CV1)
14.3.2.7
Reserved Register (PWMTST)
This register is reserved for factory testing of the PWM module and is not available in normal modes.
Module Base + 0x0006
7 6 5 4 3 2 1 0
R W Reset
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
= Unimplemented or Reserved
Figure 14-9. Reserved Register (PWMTST)
Read: Always read $00 in normal modes Write: Unimplemented in normal modes NOTE Writing to this register when in special modes can alter the PWM functionality.
14.3.2.8
Reserved Register (PWMPRSC)
This register is reserved for factory testing of the PWM module and is not available in normal modes.
Module Base + 0x0007
7 6 5 4 3 2 1 0
R W Reset
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
= Unimplemented or Reserved
Figure 14-10. Reserved Register (PWMPRSC)
Read: Always read $00 in normal modes Write: Unimplemented in normal modes NOTE Writing to this register when in special modes can alter the PWM functionality.
14.3.2.9
PWM Scale A Register (PWMSCLA)
PWMSCLA is the programmable scale value used in scaling clock A to generate clock SA. Clock SA is generated by taking clock A, dividing it by the value in the PWMSCLA register and dividing that by two. Clock SA = Clock A / (2 * PWMSCLA)
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 415
Chapter 14 Pulse-Width Modulator (PWM8B8CV1)
NOTE When PWMSCLA = $00, PWMSCLA value is considered a full scale value of 256. Clock A is thus divided by 512. Any value written to this register will cause the scale counter to load the new scale value (PWMSCLA).
Module Base + 0x0008
7 6 5 4 3 2 1 0
R W Reset
Bit 7 0
6 0
5 0
4 0
3 0
2 0
1 0
Bit 0 0
Figure 14-11. PWM Scale A Register (PWMSCLA)
Read: Anytime Write: Anytime (causes the scale counter to load the PWMSCLA value)
14.3.2.10 PWM Scale B Register (PWMSCLB)
PWMSCLB is the programmable scale value used in scaling clock B to generate clock SB. Clock SB is generated by taking clock B, dividing it by the value in the PWMSCLB register and dividing that by two. Clock SB = Clock B / (2 * PWMSCLB) NOTE When PWMSCLB = $00, PWMSCLB value is considered a full scale value of 256. Clock B is thus divided by 512. Any value written to this register will cause the scale counter to load the new scale value (PWMSCLB).
Module Base + 0x0009
7 6 5 4 3 2 1 0
R W Reset
Bit 7 0
6 0
5 0
4 0
3 0
2 0
1 0
Bit 0 0
Figure 14-12. PWM Scale B Register (PWMSCLB)
Read: Anytime Write: Anytime (causes the scale counter to load the PWMSCLB value).
14.3.2.11 Reserved Registers (PWMSCNTx)
The registers PWMSCNTA and PWMSCNTB are reserved for factory testing of the PWM module and are not available in normal modes.
MC3S12RG128 Data Sheet, Rev. 1.05 416 Freescale Semiconductor
Chapter 14 Pulse-Width Modulator (PWM8B8CV1)
Module Base + 0x000A, 0x000B
7 6 5 4 3 2 1 0
R W Reset
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
= Unimplemented or Reserved
Figure 14-13. Reserved Registers (PWMSCNTx)
Read: Always read $00 in normal modes Write: Unimplemented in normal modes NOTE Writing to these registers when in special modes can alter the PWM functionality.
14.3.2.12 PWM Channel Counter Registers (PWMCNTx)
Each channel has a dedicated 8-bit up/down counter which runs at the rate of the selected clock source. The counter can be read at any time without affecting the count or the operation of the PWM channel. In left aligned output mode, the counter counts from 0 to the value in the period register - 1. In center aligned output mode, the counter counts from 0 up to the value in the period register and then back down to 0. Any value written to the counter causes the counter to reset to $00, the counter direction to be set to up, the immediate load of both duty and period registers with values from the buffers, and the output to change according to the polarity bit. The counter is also cleared at the end of the effective period (see Section 14.4.2.5, "Left Aligned Outputs" and Section 14.4.2.6, "Center Aligned Outputs" for more details). When the channel is disabled (PWMEx = 0), the PWMCNTx register does not count. When a channel becomes enabled (PWMEx = 1), the associated PWM counter starts at the count in the PWMCNTx register. For more detailed information on the operation of the counters, see Section 14.4.2.4, "PWM Timer Counters". In concatenated mode, writes to the 16-bit counter by using a 16-bit access or writes to either the low or high order byte of the counter will reset the 16-bit counter. Reads of the 16-bit counter must be made by 16-bit access to maintain data coherency. NOTE Writing to the counter while the channel is enabled can cause an irregular PWM cycle to occur.
Module Base + 0x000C = PWMCNT0, 0x000D = PWMCNT1, 0x000E = PWMCNT2, 0x000F = PWMCNT3 Module Base + 0x0010 = PWMCNT4, 0x0011 = PWMCNT5, 0x0012 = PWMCNT6, 0x0013 = PWMCNT7
7 6 5 4 3 2 1 0
R W Reset
Bit 7 0 0
6 0 0
5 0 0
4 0 0
3 0 0
2 0 0
1 0 0
Bit 0 0 0
Figure 14-14. PWM Channel Counter Registers (PWMCNTx)
Read: Anytime
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 417
Chapter 14 Pulse-Width Modulator (PWM8B8CV1)
Write: Anytime (any value written causes PWM counter to be reset to $00).
14.3.2.13 PWM Channel Period Registers (PWMPERx)
There is a dedicated period register for each channel. The value in this register determines the period of the associated PWM channel. The period registers for each channel are double buffered so that if they change while the channel is enabled, the change will NOT take effect until one of the following occurs: * The effective period ends * The counter is written (counter resets to $00) * The channel is disabled In this way, the output of the PWM will always be either the old waveform or the new waveform, not some variation in between. If the channel is not enabled, then writes to the period register will go directly to the latches as well as the buffer. NOTE Reads of this register return the most recent value written. Reads do not necessarily return the value of the currently active period due to the double buffering scheme. See Section 14.4.2.3, "PWM Period and Duty" for more information. To calculate the output period, take the selected clock source period for the channel of interest (A, B, SA, or SB) and multiply it by the value in the period register for that channel: * Left aligned output (CAEx = 0) * PWMx Period = Channel Clock Period * PWMPERx Center Aligned Output (CAEx = 1) PWMx Period = Channel Clock Period * (2 * PWMPERx) For boundary case programming values, please refer to Section 14.4.2.8, "PWM Boundary Cases".
Module Base + 0x0014 = PWMPER0, 0x0015 = PWMPER1, 0x0016 = PWMPER2, 0x0017 = PWMPER3 Module Base + 0x0018 = PWMPER4, 0x0019 = PWMPER5, 0x001A = PWMPER6, 0x001B = PWMPER7
7 6 5 4 3 2 1 0
R W Reset
Bit 7 1
6 1
5 1
4 1
3 1
2 1
1 1
Bit 0 1
Figure 14-15. PWM Channel Period Registers (PWMPERx)
Read: Anytime Write: Anytime
MC3S12RG128 Data Sheet, Rev. 1.05 418 Freescale Semiconductor
Chapter 14 Pulse-Width Modulator (PWM8B8CV1)
14.3.2.14 PWM Channel Duty Registers (PWMDTYx)
There is a dedicated duty register for each channel. The value in this register determines the duty of the associated PWM channel. The duty value is compared to the counter and if it is equal to the counter value a match occurs and the output changes state. The duty registers for each channel are double buffered so that if they change while the channel is enabled, the change will NOT take effect until one of the following occurs: * The effective period ends * The counter is written (counter resets to $00) * The channel is disabled In this way, the output of the PWM will always be either the old duty waveform or the new duty waveform, not some variation in between. If the channel is not enabled, then writes to the duty register will go directly to the latches as well as the buffer. NOTE Reads of this register return the most recent value written. Reads do not necessarily return the value of the currently active duty due to the double buffering scheme. See Section 14.4.2.3, "PWM Period and Duty" for more information. NOTE Depending on the polarity bit, the duty registers will contain the count of either the high time or the low time. If the polarity bit is one, the output starts high and then goes low when the duty count is reached, so the duty registers contain a count of the high time. If the polarity bit is zero, the output starts low and then goes high when the duty count is reached, so the duty registers contain a count of the low time. To calculate the output duty cycle (high time as a% of period) for a particular channel: * Polarity = 0 (PPOL x =0) Duty Cycle = [(PWMPERx-PWMDTYx)/PWMPERx] * 100% * Polarity = 1 (PPOLx = 1) Duty Cycle = [PWMDTYx / PWMPERx] * 100% For boundary case programming values, please refer to Section 14.4.2.8, "PWM Boundary Cases".
Module Base + 0x001C = PWMDTY0, 0x001D = PWMDTY1, 0x001E = PWMDTY2, 0x001F = PWMDTY3 Module Base + 0x0020 = PWMDTY4, 0x0021 = PWMDTY5, 0x0022 = PWMDTY6, 0x0023 = PWMDTY7
7 6 5 4 3 2 1 0
R W Reset
Bit 7 1
6 1
5 1
4 1
3 1
2 1
1 1
Bit 0 1
Figure 14-16. PWM Channel Duty Registers (PWMDTYx)
Read: Anytime
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 419
Chapter 14 Pulse-Width Modulator (PWM8B8CV1)
Write: Anytime
14.3.2.15 PWM Shutdown Register (PWMSDN)
The PWMSDN register provides for the shutdown functionality of the PWM module in the emergency cases. For proper operation, channel 7 must be driven to the active level for a minimum of two bus clocks.
Module Base + 0x0024
7 6 5 4 3 2 1 0
R W Reset
PWMIF 0
PWMIE 0
0 PWMRSTRT 0
PWMLVL 0
0 0
PWM7IN 0
PWM7INL 0
PWM7ENA 0
= Unimplemented or Reserved
Figure 14-17. PWM Shutdown Register (PWMSDN)
Read: Anytime Write: Anytime
Table 14-9. PWMSDN Field Descriptions
Field 7 PWMIF Description PWM Interrupt Flag -- Any change from passive to asserted (active) state or from active to passive state will be flagged by setting the PWMIF flag = 1. The flag is cleared by writing a logic 1 to it. Writing a 0 has no effect. 0 No change on PWM7IN input. 1 Change on PWM7IN input PWM Interrupt Enable -- If interrupt is enabled an interrupt to the CPU is asserted. 0 PWM interrupt is disabled. 1 PWM interrupt is enabled.
6 PWMIE
5 PWM Restart -- The PWM can only be restarted if the PWM channel input 7 is de-asserted. After writing a logic PWMRSTRT 1 to the PWMRSTRT bit (trigger event) the PWM channels start running after the corresponding counter passes next "counter == 0" phase. Also, if the PWM7ENA bit is reset to 0, the PWM do not start before the counter passes $00. The bit is always read as "0". 4 PWMLVL PWM Shutdown Output Level If active level as defined by the PWM7IN input, gets asserted all enabled PWM channels are immediately driven to the level defined by PWMLVL. 0 PWM outputs are forced to 0 1 Outputs are forced to 1. PWM Channel 7 Input Status -- This reflects the current status of the PWM7 pin. PWM Shutdown Active Input Level for Channel 7 -- If the emergency shutdown feature is enabled (PWM7ENA = 1), this bit determines the active level of the PWM7channel. 0 Active level is low 1 Active level is high PWM Emergency Shutdown Enable -- If this bit is logic 1, the pin associated with channel 7 is forced to input and the emergency shutdown feature is enabled. All the other bits in this register are meaningful only if PWM7ENA = 1. 0 PWM emergency feature disabled. 1 PWM emergency feature is enabled.
2 PWM7IN 1 PWM7INL
0 PWM7ENA
MC3S12RG128 Data Sheet, Rev. 1.05 420 Freescale Semiconductor
Chapter 14 Pulse-Width Modulator (PWM8B8CV1)
14.4
14.4.1
Functional Description
PWM Clock Select
There are four available clocks: clock A, clock B, clock SA (scaled A), and clock SB (scaled B). These four clocks are based on the bus clock. Clock A and B can be software selected to be 1, 1/2, 1/4, 1/8,..., 1/64, 1/128 times the bus clock. Clock SA uses clock A as an input and divides it further with a reloadable counter. Similarly, clock SB uses clock B as an input and divides it further with a reloadable counter. The rates available for clock SA are software selectable to be clock A divided by 2, 4, 6, 8,..., or 512 in increments of divide by 2. Similar rates are available for clock SB. Each PWM channel has the capability of selecting one of two clocks, either the pre-scaled clock (clock A or B) or the scaled clock (clock SA or SB). The block diagram in Figure 14-18 shows the four different clocks and how the scaled clocks are created.
14.4.1.1
Prescale
The input clock to the PWM prescaler is the bus clock. It can be disabled whenever the part is in freeze mode by setting the PFRZ bit in the PWMCTL register. If this bit is set, whenever the MCU is in freeze mode (freeze mode signal active) the input clock to the prescaler is disabled. This is useful for emulation in order to freeze the PWM. The input clock can also be disabled when all eight PWM channels are disabled (PWME7-0 = 0). This is useful for reducing power by disabling the prescale counter. Clock A and clock B are scaled values of the input clock. The value is software selectable for both clock A and clock B and has options of 1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, or 1/128 times the bus clock. The value selected for clock A is determined by the PCKA2, PCKA1, PCKA0 bits in the PWMPRCLK register. The value selected for clock B is determined by the PCKB2, PCKB1, PCKB0 bits also in the PWMPRCLK register.
14.4.1.2
Clock Scale
The scaled A clock uses clock A as an input and divides it further with a user programmable value and then divides this by 2. The scaled B clock uses clock B as an input and divides it further with a user programmable value and then divides this by 2. The rates available for clock SA are software selectable to be clock A divided by 2, 4, 6, 8,..., or 512 in increments of divide by 2. Similar rates are available for clock SB.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 421
Chapter 14 Pulse-Width Modulator (PWM8B8CV1)
Clock A Clock A/2, A/4, A/6,....A/512
M U X PCLK0 M U X
Clock to PWM Ch 0
PCKA2 PCKA1 PCKA0
8-Bit Down Counter
Count = 1
Load PWMSCLA M U X 2 4 8 16 32 64 128 DIV 2 Clock SA
Clock to PWM Ch 1
PCLK1 M U X PCLK2 M U X PCLK3 Clock to PWM Ch 3 Clock to PWM Ch 2
Divide by Prescaler Taps:
Clock B Clock B/2, B/4, B/6,....B/512
M U X PCLK4
Clock to PWM Ch 4
M U X 8-Bit Down Counter Count = 1
Load PWMSCLB DIV 2 Clock SB
M U X PCLK5 M U X PCLK6 M U X PCLK7
Clock to PWM Ch 5
Clock to PWM Ch 6
Bus Clock PFRZ Freeze Mode Signal
PWME7-0
PCKB2 PCKB1 PCKB0
Clock to PWM Ch 7
Prescale
Scale
Clock Select
Figure 14-18. PWM Clock Select Block Diagram
MC3S12RG128 Data Sheet, Rev. 1.05 422 Freescale Semiconductor
Chapter 14 Pulse-Width Modulator (PWM8B8CV1)
Clock A is used as an input to an 8-bit down counter. This down counter loads a user programmable scale value from the scale register (PWMSCLA). When the down counter reaches one, a pulse is output and the 8-bit counter is re-loaded. The output signal from this circuit is further divided by two. This gives a greater range with only a slight reduction in granularity. Clock SA equals clock A divided by two times the value in the PWMSCLA register. NOTE Clock SA = Clock A / (2 * PWMSCLA) When PWMSCLA = $00, PWMSCLA value is considered a full scale value of 256. Clock A is thus divided by 512. Similarly, clock B is used as an input to an 8-bit down counter followed by a divide by two producing clock SB. Thus, clock SB equals clock B divided by two times the value in the PWMSCLB register. NOTE Clock SB = Clock B / (2 * PWMSCLB) When PWMSCLB = $00, PWMSCLB value is considered a full scale value of 256. Clock B is thus divided by 512. As an example, consider the case in which the user writes $FF into the PWMSCLA register. Clock A for this case will be E divided by 4. A pulse will occur at a rate of once every 255x4 E cycles. Passing this through the divide by two circuit produces a clock signal at an E divided by 2040 rate. Similarly, a value of $01 in the PWMSCLA register when clock A is E divided by 4 will produce a clock at an E divided by 8 rate. Writing to PWMSCLA or PWMSCLB causes the associated 8-bit down counter to be re-loaded. Otherwise, when changing rates the counter would have to count down to $01 before counting at the proper rate. Forcing the associated counter to re-load the scale register value every time PWMSCLA or PWMSCLB is written prevents this. NOTE Writing to the scale registers while channels are operating can cause irregularities in the PWM outputs.
14.4.1.3
Clock Select
Each PWM channel has the capability of selecting one of two clocks. For channels 0, 1, 4, and 5 the clock choices are clock A or clock SA. For channels 2, 3, 6, and 7 the choices are clock B or clock SB. The clock selection is done with the PCLKx control bits in the PWMCLK register. NOTE Changing clock control bits while channels are operating can cause irregularities in the PWM outputs.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 423
Chapter 14 Pulse-Width Modulator (PWM8B8CV1)
14.4.2
PWM Channel Timers
The main part of the PWM module are the actual timers. Each of the timer channels has a counter, a period register and a duty register (each are 8-bit). The waveform output period is controlled by a match between the period register and the value in the counter. The duty is controlled by a match between the duty register and the counter value and causes the state of the output to change during the period. The starting polarity of the output is also selectable on a per channel basis. Shown below in Figure 14-19 is the block diagram for the PWM timer.
Clock Source 8-Bit Counter Gate (Clock Edge Sync) Up/Down Reset 8-bit Compare = T PWMDTYx R 8-bit Compare = PWMPERx PPOLx Q Q M U X M U X To Pin Driver PWMCNTx From Port PWMP Data Register
Q Q
T R
CAEx
PWMEx
Figure 14-19. PWM Timer Channel Block Diagram
14.4.2.1
PWM Enable
Each PWM channel has an enable bit (PWMEx) to start its waveform output. When any of the PWMEx bits are set (PWMEx = 1), the associated PWM output signal is enabled immediately. However, the actual PWM waveform is not available on the associated PWM output until its clock source begins its next cycle due to the synchronization of PWMEx and the clock source. An exception to this is when channels are concatenated. Refer to Section 14.4.2.7, "PWM 16-Bit Functions" for more detail. NOTE The first PWM cycle after enabling the channel can be irregular.
MC3S12RG128 Data Sheet, Rev. 1.05 424 Freescale Semiconductor
Chapter 14 Pulse-Width Modulator (PWM8B8CV1)
On the front end of the PWM timer, the clock is enabled to the PWM circuit by the PWMEx bit being high. There is an edge-synchronizing circuit to guarantee that the clock will only be enabled or disabled at an edge. When the channel is disabled (PWMEx = 0), the counter for the channel does not count.
14.4.2.2
PWM Polarity
Each channel has a polarity bit to allow starting a waveform cycle with a high or low signal. This is shown on the block diagram as a mux select of either the Q output or the Q output of the PWM output flip flop. When one of the bits in the PWMPOL register is set, the associated PWM channel output is high at the beginning of the waveform, then goes low when the duty count is reached. Conversely, if the polarity bit is zero, the output starts low and then goes high when the duty count is reached.
14.4.2.3
PWM Period and Duty
Dedicated period and duty registers exist for each channel and are double buffered so that if they change while the channel is enabled, the change will NOT take effect until one of the following occurs: * The effective period ends * The counter is written (counter resets to $00) * The channel is disabled In this way, the output of the PWM will always be either the old waveform or the new waveform, not some variation in between. If the channel is not enabled, then writes to the period and duty registers will go directly to the latches as well as the buffer. A change in duty or period can be forced into effect "immediately" by writing the new value to the duty and/or period registers and then writing to the counter. This forces the counter to reset and the new duty and/or period values to be latched. In addition, since the counter is readable, it is possible to know where the count is with respect to the duty value and software can be used to make adjustments NOTE When forcing a new period or duty into effect immediately, an irregular PWM cycle can occur. Depending on the polarity bit, the duty registers will contain the count of either the high time or the low time.
14.4.2.4
PWM Timer Counters
Each channel has a dedicated 8-bit up/down counter which runs at the rate of the selected clock source (see Section 14.4.1, "PWM Clock Select" for the available clock sources and rates). The counter compares to two registers, a duty register and a period register as shown in Figure 14-19. When the PWM counter matches the duty register, the output flip-flop changes state, causing the PWM waveform to also change state. A match between the PWM counter and the period register behaves differently depending on what output mode is selected as shown in Figure 14-19 and described in Section 14.4.2.5, "Left Aligned Outputs" and Section 14.4.2.6, "Center Aligned Outputs".
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 425
Chapter 14 Pulse-Width Modulator (PWM8B8CV1)
Each channel counter can be read at anytime without affecting the count or the operation of the PWM channel. Any value written to the counter causes the counter to reset to $00, the counter direction to be set to up, the immediate load of both duty and period registers with values from the buffers, and the output to change according to the polarity bit. When the channel is disabled (PWMEx = 0), the counter stops. When a channel becomes enabled (PWMEx = 1), the associated PWM counter continues from the count in the PWMCNTx register. This allows the waveform to continue where it left off when the channel is re-enabled. When the channel is disabled, writing "0" to the period register will cause the counter to reset on the next selected clock. NOTE If the user wants to start a new "clean" PWM waveform without any "history" from the old waveform, the user must write to channel counter (PWMCNTx) prior to enabling the PWM channel (PWMEx = 1). Generally, writes to the counter are done prior to enabling a channel in order to start from a known state. However, writing a counter can also be done while the PWM channel is enabled (counting). The effect is similar to writing the counter when the channel is disabled, except that the new period is started immediately with the output set according to the polarity bit. NOTE Writing to the counter while the channel is enabled can cause an irregular PWM cycle to occur. The counter is cleared at the end of the effective period (see Section 14.4.2.5, "Left Aligned Outputs" and Section 14.4.2.6, "Center Aligned Outputs" for more details).
Table 14-10. PWM Timer Counter Conditions
Counter Clears ($00) When PWMCNTx register written to any value Effective period ends Counter Counts When PWM channel is enabled (PWMEx = 1). Counts from last value in PWMCNTx. Counter Stops When PWM channel is disabled (PWMEx = 0)
14.4.2.5
Left Aligned Outputs
The PWM timer provides the choice of two types of outputs, left aligned or center aligned. They are selected with the CAEx bits in the PWMCAE register. If the CAEx bit is cleared (CAEx = 0), the corresponding PWM output will be left aligned. In left aligned output mode, the 8-bit counter is configured as an up counter only. It compares to two registers, a duty register and a period register as shown in the block diagram in Figure 14-19. When the PWM counter matches the duty register the output flip-flop changes state causing the PWM waveform to also change state. A match between the PWM counter and the period register resets the counter and the output flip-flop, as shown in Figure 14-19, as well as performing a load from the double buffer period and duty register to the associated registers, as described in Section 14.4.2.3, "PWM Period and Duty". The counter counts from 0 to the value in the period register - 1.
MC3S12RG128 Data Sheet, Rev. 1.05 426 Freescale Semiconductor
Chapter 14 Pulse-Width Modulator (PWM8B8CV1)
NOTE Changing the PWM output mode from left aligned to center aligned output (or vice versa) while channels are operating can cause irregularities in the PWM output. It is recommended to program the output mode before enabling the PWM channel.
PPOLx = 0
PPOLx = 1 PWMDTYx Period = PWMPERx
Figure 14-20. PWM Left Aligned Output Waveform
To calculate the output frequency in left aligned output mode for a particular channel, take the selected clock source frequency for the channel (A, B, SA, or SB) and divide it by the value in the period register for that channel. * PWMx Frequency = Clock (A, B, SA, or SB) / PWMPERx * PWMx Duty Cycle (high time as a% of period): -- Polarity = 0 (PPOLx = 0) * Duty Cycle = [(PWMPERx-PWMDTYx)/PWMPERx] * 100% -- Polarity = 1 (PPOLx = 1) Duty Cycle = [PWMDTYx / PWMPERx] * 100% As an example of a left aligned output, consider the following case: Clock Source = E, where E = 10 MHz (100 ns period) PPOLx = 0 PWMPERx = 4 PWMDTYx = 1 PWMx Frequency = 10 MHz/4 = 2.5 MHz PWMx Period = 400 ns PWMx Duty Cycle = 3/4 *100% = 75% The output waveform generated is shown in Figure 14-21.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 427
Chapter 14 Pulse-Width Modulator (PWM8B8CV1)
E = 100 ns
Duty Cycle = 75% Period = 400 ns
Figure 14-21. PWM Left Aligned Output Example Waveform
14.4.2.6
Center Aligned Outputs
For center aligned output mode selection, set the CAEx bit (CAEx = 1) in the PWMCAE register and the corresponding PWM output will be center aligned. The 8-bit counter operates as an up/down counter in this mode and is set to up whenever the counter is equal to $00. The counter compares to two registers, a duty register and a period register as shown in the block diagram in Figure 14-19. When the PWM counter matches the duty register, the output flip-flop changes state, causing the PWM waveform to also change state. A match between the PWM counter and the period register changes the counter direction from an up-count to a down-count. When the PWM counter decrements and matches the duty register again, the output flip-flop changes state causing the PWM output to also change state. When the PWM counter decrements and reaches zero, the counter direction changes from a down-count back to an up-count and a load from the double buffer period and duty registers to the associated registers is performed, as described in Section 14.4.2.3, "PWM Period and Duty". The counter counts from 0 up to the value in the period register and then back down to 0. Thus the effective period is PWMPERx*2. NOTE Changing the PWM output mode from left aligned to center aligned output (or vice versa) while channels are operating can cause irregularities in the PWM output. It is recommended to program the output mode before enabling the PWM channel.
PPOLx = 0
PPOLx = 1 PWMDTYx PWMPERx Period = PWMPERx*2 PWMDTYx PWMPERx
Figure 14-22. PWM Center Aligned Output Waveform
MC3S12RG128 Data Sheet, Rev. 1.05 428 Freescale Semiconductor
Chapter 14 Pulse-Width Modulator (PWM8B8CV1)
To calculate the output frequency in center aligned output mode for a particular channel, take the selected clock source frequency for the channel (A, B, SA, or SB) and divide it by twice the value in the period register for that channel. * PWMx Frequency = Clock (A, B, SA, or SB) / (2*PWMPERx) * PWMx Duty Cycle (high time as a% of period): -- Polarity = 0 (PPOLx = 0) Duty Cycle = [(PWMPERx-PWMDTYx)/PWMPERx] * 100% -- Polarity = 1 (PPOLx = 1) Duty Cycle = [PWMDTYx / PWMPERx] * 100%
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 429
Chapter 14 Pulse-Width Modulator (PWM8B8CV1)
As an example of a center aligned output, consider the following case: Clock Source = E, where E = 10 MHz (100 ns period) PPOLx = 0 PWMPERx = 4 PWMDTYx = 1 PWMx Frequency = 10 MHz/8 = 1.25 MHz PWMx Period = 800 ns PWMx Duty Cycle = 3/4 *100% = 75% Shown in Figure 14-23 is the output waveform generated.
E = 100 ns E = 100 ns
DUTY CYCLE = 75% PERIOD = 800 ns
Figure 14-23. PWM Center Aligned Output Example Waveform
14.4.2.7
PWM 16-Bit Functions
The PWM timer also has the option of generating 8-channels of 8-bits or 4-channels of 16-bits for greater PWM resolution. This 16-bit channel option is achieved through the concatenation of two 8-bit channels. The PWMCTL register contains four control bits, each of which is used to concatenate a pair of PWM channels into one 16-bit channel. Channels 6 and 7 are concatenated with the CON67 bit, channels 4 and 5 are concatenated with the CON45 bit, channels 2 and 3 are concatenated with the CON23 bit, and channels 0 and 1 are concatenated with the CON01 bit. NOTE Change these bits only when both corresponding channels are disabled. When channels 6 and 7 are concatenated, channel 6 registers become the high order bytes of the double byte channel, as shown in Figure 14-24. Similarly, when channels 4 and 5 are concatenated, channel 4 registers become the high order bytes of the double byte channel. When channels 2 and 3 are concatenated, channel 2 registers become the high order bytes of the double byte channel. When channels 0 and 1 are concatenated, channel 0 registers become the high order bytes of the double byte channel. When using the 16-bit concatenated mode, the clock source is determined by the low order 8-bit channel clock select control bits. That is channel 7 when channels 6 and 7 are concatenated, channel 5 when channels 4 and 5 are concatenated, channel 3 when channels 2 and 3 are concatenated, and channel 1 when channels 0 and 1 are concatenated. The resulting PWM is output to the pins of the corresponding low order 8-bit channel as also shown in Figure 14-24. The polarity of the resulting PWM output is controlled by the PPOLx bit of the corresponding low order 8-bit channel as well.
MC3S12RG128 Data Sheet, Rev. 1.05 430 Freescale Semiconductor
Chapter 14 Pulse-Width Modulator (PWM8B8CV1)
Clock Source 7 High PWMCNT6 Low PWCNT7
Period/Duty Compare
PWM7
Clock Source 5 High PWMCNT4 Low PWCNT5
Period/Duty Compare
PWM5
Clock Source 3 High PWMCNT2 Low PWCNT3
Period/Duty Compare
PWM3
Clock Source 1 High PWMCNT0 Low PWCNT1
Period/Duty Compare
PWM1
Figure 14-24. PWM 16-Bit Mode
Once concatenated mode is enabled (CONxx bits set in PWMCTL register), enabling/disabling the corresponding 16-bit PWM channel is controlled by the low order PWMEx bit. In this case, the high order bytes PWMEx bits have no effect and their corresponding PWM output is disabled. In concatenated mode, writes to the 16-bit counter by using a 16-bit access or writes to either the low or high order byte of the counter will reset the 16-bit counter. Reads of the 16-bit counter must be made by 16-bit access to maintain data coherency.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 431
Chapter 14 Pulse-Width Modulator (PWM8B8CV1)
Either left aligned or center aligned output mode can be used in concatenated mode and is controlled by the low order CAEx bit. The high order CAEx bit has no effect. Table 14-11 is used to summarize which channels are used to set the various control bits when in 16-bit mode.
Table 14-11. 16-bit Concatenation Mode Summary
CONxx CON67 CON45 CON23 CON01 PWMEx PWME7 PWME5 PWME3 PWME1 PPOLx PPOL7 PPOL5 PPOL3 PPOL1 PCLKx PCLK7 PCLK5 PCLK3 PCLK1 CAEx CAE7 CAE5 CAE3 CAE1 PWMx Output PWM7 PWM5 PWM3 PWM1
14.4.2.8
PWM Boundary Cases
Table 14-12 summarizes the boundary conditions for the PWM regardless of the output mode (left aligned or center aligned) and 8-bit (normal) or 16-bit (concatenation).
Table 14-12. PWM Boundary Cases
PWMDTYx $00 (indicates no duty) $00 (indicates no duty) XX XX >= PWMPERx >= PWMPERx
1
PWMPERx >$00 >$00 $001 (indicates no period) $001 (indicates no period) XX XX
PPOLx 1 0 1 0 1 0
PWMx Output Always low Always high Always high Always low Always high Always low
Counter = $00 and does not count.
14.5
Resets
The reset state of each individual bit is listed within the Section 14.3.2, "Register Descriptions" which details the registers and their bit-fields. All special functions or modes which are initialized during or just following reset are described within this section. * The 8-bit up/down counter is configured as an up counter out of reset. * All the channels are disabled and all the counters do not count.
MC3S12RG128 Data Sheet, Rev. 1.05 432 Freescale Semiconductor
Chapter 14 Pulse-Width Modulator (PWM8B8CV1)
14.6
Interrupts
The PWM module has only one interrupt which is generated at the time of emergency shutdown, if the corresponding enable bit (PWMIE) is set. This bit is the enable for the interrupt. The interrupt flag PWMIF is set whenever the input level of the PWM7 channel changes while PWM7ENA = 1 or when PWMENA is being asserted while the level at PWM7 is active. In stop mode or wait mode (with the PSWAI bit set), the emergency shutdown feature will drive the PWM outputs to their shutdown output levels but the PWMIF flag will not be set. A description of the registers involved and affected due to this interrupt is explained in Section 14.3.2.15, "PWM Shutdown Register (PWMSDN)". The PWM block only generates the interrupt and does not service it. The interrupt signal name is PWM interrupt signal.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 433
Chapter 14 Pulse-Width Modulator (PWM8B8CV1)
MC3S12RG128 Data Sheet, Rev. 1.05 434 Freescale Semiconductor
Chapter 15 Read-Only Memory 64K x 16 (ROM64KX16V1) Block Description
15.1 Introduction
This document describes the ROM64KX16 module which controls a 128 K byte mask-programmed read-only memory array for use with 0.25 micron HCS12 devices.
15.1.1
Glossary
Table 15-1. Terminology Term ROM Meaning
Read-Only Memory
The following terms and abbreviations are used in the document.
15.1.2
Features
The ROM64KX16 includes the following features: * Control read access to 128 K bytes of mask-programmed ROM memory comprised of one 64Kx16 byte block * Security with user backdoor key entry
15.1.3
Modes of Operation
The modes of operation for ROM64KX16 are listed below. * Run The ROM64KX16 interface provides one cycle read access to the ROM hard block. * Standby Whenever the on-chip ROM is not being accessed, the ROM64KX16 module holds the ROM hard block in standby.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 435
Chapter 15 Read-Only Memory 64K x 16 (ROM64KX16V1) Block Description
15.1.4
Block Diagram
Figure 15-1 is a high level block diagram of the ROM64KX16 interface control block.
ROM_64KX16
ROM Registers & Security
ROM data
ROM Control Address
ROM Hard block
16 Bytes Reserved
Figure 15-1. ROM64KX16 Block Diagram
15.2
External Signal Description
No external signal connections exist for the ROM64KX16 module.
15.3
Memory Map and Registers
This section provides a detailed description of all memory and registers.
MC3S12RG128 Data Sheet, Rev. 1.05 436 Freescale Semiconductor
Chapter 15 Read-Only Memory 64K x 16 (ROM64KX16V1) Block Description
15.3.1
Module Memory Map
The ROM64KX16 module occupies a 16 byte memory space within the on-chip memory map (address offsets $0000 - $000F). A summary of the ROM control registers is given in Figure 15-2 while their accessibility is detailed in section Section 15.3.2, "Register Descriptions".
Address 0x0000 0x0001 0x0002 0x0003 0x0004 - 0x000B 0x000C 0x000D 0x000E 0x000F Name Reserved ROPT Reserved RCNFG Reserved RDSC0 RDSC1 RDSC2 RESERVED R W R W R W R W R W R W R W R W R W Bit 7 0 KEYEN1 0 0 0 6 0 KEYEN0 0 0 0 5 0 NV5 0 4 0 NV4 0 0 0 3 0 NV3 0 0 0 2 0 NV2 0 0 0 1 0 SEC1 0 0 0 Bit 0 0 SEC0 0 0 0
KEYACC 0
DSC0[7:0] DSC1[7:0] DSC2[7:0] 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 15-2. ROM64KX16 Register Summary
15.3.2
15.3.2.1
Register Descriptions
ROM Options Register (ROPT)
Module Base + 0x0001
7 6 5 4 3 2 1 0
R W Reset
1
KEYEN1
KEYEN0
NV5
NV4
NV3
NV2
SEC1
SEC0
R1
R1
R1
R1
R1
R1
R1
R1
Read from non-volatile registers in ROM
Figure 15-3. ROM Options Register (ROPT)
Read: Anytime Write: Never
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 437
Chapter 15 Read-Only Memory 64K x 16 (ROM64KX16V1) Block Description
Table 15-2. ROPT Field Descriptions
Field Description
7-6 Key Enable Bits -- Backdoor Key Mechanism Enable. The KEYEN[1:0] bits control backdoor key access to the KEYEN[1:0] ROM module as shown in Table 15-3. If the backdoor key mechanism is enabled, user firmware can write a 4-words value that matches the non-volatile backdoor key (NVBACKKEY+0x0000 through NVBACKKEY+0x0007 in that order), to temporarily disengage security until the next reset. The backdoor key mechanism is accessible only from user (secured) firmware. BDM commands cannot be used to write key comparison values that would unlock the backdoor key. If disabled, no backdoor key access allowed. Note: Please note that backdoor keywords $0000 and $FFFF are invalid and will effectively disable backdoor key access when used. Note: On Mask-ROM devices the backdoor key is also used to protect access to internal product analysis features. No product analysis will be possible on a secured ROM if backdoor key access is disabled or keywords are invalid. 5-2 NV[5:2] 1-0 SEC[1:0] Non-Volatile Flag Bits -- These 4 bits are available to the user as non-volatile flags. Security State Code -- This 2-bit field determines the security state of the MCU. The security state is coded as shown in Table 15-4.
Table 15-3. ROM Backdoor Key Enable States KEYEN[1:0] 00 01 10 11
1Preferred
Status of Backdoor Key Access Disabled Disabled1 Enabled Disabled
KEYEN state to disable Backdoor Key Access.
Table 15-4. ROM Security States SEC[1:0] 00 01 10 11
1
Status of Security Secured Secured1 Unsecured Secured
Preferred SEC state to secure the MCU.
MC3S12RG128 Data Sheet, Rev. 1.05 438 Freescale Semiconductor
Chapter 15 Read-Only Memory 64K x 16 (ROM64KX16V1) Block Description
15.3.2.2
ROM Configuration Register (RCNFG)
Module Base + 0x0003
7 6 5 4 3 2 1 0
R W Reset
0
0 KEYACC
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 15-4. ROM Configuration Register (RCNFG)
Read: Anytime Write: Anytime
Table 15-5. RCNFG Field Descriptions
Field 5 KEYACC Description Key Access Bit -- Enable writing of security access (backdoor) key. This bit enables writing of the backdoor comparison key for disabling security. This bit cannot be set unless the KEYEN[1:0] bits in the ROPT register are set to "10". While this bit is set, normal accesses to the ROM array are blocked, returned data is undefined. 0 Backdoor key access enabled 1 Backdoor key access disabled
15.3.2.3
ROM Device SC Number Registers (RDSC0-RDSC2)
Module Base + 0x000C Module Base + 0x000D Module Base + 0x000E
7 6 5 4 3 2 1 0
R W Reset
1
DSCn[7:0]
R1
R1
R1
R1
R1
R1
R1
R1
Read from non-volatile registers in ROM
Figure 15-5. ROM Device SC Number Register (RDSC0-RDSC2)
Read: Anytime Write: Never
Table 15-6. RDSC0-RDSC2 Field Descriptions
Field 7-0 DSCn[7:0] Description Device SC Number n -- Device SC Number byte n (n=<0,1,2>).
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 439
Chapter 15 Read-Only Memory 64K x 16 (ROM64KX16V1) Block Description
15.3.3
Non-volatile Registers
A range of addresses in the ROM array is reserved for the option bits and backdoor key. Additionally, some locations are reserved for the ROM Device SC number and for the 32 bit CRC value which is used by the ROM BIST engine to verify the ROM array content during production test.
Address 0xFF00 0xFF07 0xFF08 0xFF09 0xFF0A 0xFF0B 0xFF0C 0xFF0D 0xFF0E 0xFF0F Name NVBACKKEY NVCRC0 NVCRC1 NVCRC2 NVCRC3 NVSC0 NVSC1 NVSC2 NVOPT Bit 7 6 5 4 3 2 1 Bit 0
8-Byte Comparison Key CRC value Byte 0 CRC value Byte 1 CRC value Byte 2 CRC value Byte 3 Device SC number Byte 0 Device SC number Byte 1 Device SC number Byte 2 NV5 NV4 NV3 NV2
KEYEN1
KEYEN0
SEC1
SEC0
NOTE Both the CRC bytes and the Device SC number bytes are reserved for Freescale use. Any data present in these locations will be overwritten with Freescale assigned values when a ROM code is submitted. NOTE Please note that backdoor keywords $0000 or $FFFF are invalid and will effectively disable backdoor key access when used. NOTE On Mask-ROM devices the backdoor key is also used to protect access to internal product analysis features. No product analysis will be possible on a secured ROM if backdoor key access is disabled or keywords are invalid.
15.4
15.4.1
Functional Description
ROM Security
The ROM64KX16 module provides the necessary security information to the rest of the device. After each reset, the ROM64KX16 module determines the security state of the microcontroller as defined in Section 15.3.2.1, "ROM Options Register (ROPT)". If the NVM Options byte at 0xFF0F in the NVM Options Field is in secure state, any reset will cause the microcontroller to return to the secure operating mode
MC3S12RG128 Data Sheet, Rev. 1.05 440 Freescale Semiconductor
Chapter 15 Read-Only Memory 64K x 16 (ROM64KX16V1) Block Description
15.4.1.1
Security and Backdoor Key Access definition
Security is engaged or disengaged based on the state of two non-volatile register bits (SEC[1:0]) in the ROPT register. During reset, the contents of the non-volatile location NVOPT are copied from ROM into the working ROPT register in high-page register space. A user engages security by defining the security bits in the NVOPT location to select security enabled. This data is included along with the ROM program and data file which is delivered when ordering a ROM device. The SEC[1:0] = "10" state disengages security while the other three combinations engage security. In a similar manner the user can choose to allow or disallow a security unlocking mechanism through an 8-byte backdoor security key. There is no way to disable security unless the non-volatile KEYEN[1:0] bits in NVOPT/ROPT are set to "10". NOTE On Mask-ROM devices the backdoor key is also used to protect access to internal product analysis features. No product analysis will be possible on a secured ROM if backdoor key access is disabled or keywords are invalid.
15.4.1.2
Unsecuring the MCU using the Backdoor Key Access
Provided that the key access is permitted, security can be disabled by the backdoor access sequence described below: 1. Write 1 to KEYACC in the RCNFG register. This causes the ROM control logic to block read accesses to the ROM array and to interpret writes to the backdoor comparison key locations (NVBACKKEY+0x0000 through NVBACKKEY+0x0007) as values to be compared against the key rather than as writes to ROM locations. 2. Write the correct four 16-bit key values to addresses NVBACKKEY+0x0000 through NVBACKKEY+0x0007 locations. These writes must be done in order starting with the value for NVBACKKEY+0x0000 and ending with NVBACKKEY+0x0007. User software normally would get the key codes from outside the MCU system through a communication interface such as a serial I/O. 3. Write 0 to KEYACC in the RCNFG register. If the 8-byte key that was just written matches the key stored in the backdoor comparison key locations, SEC[1:0] in the ROPT register are automatically changed to "10" and security will be disengaged until the next system reset. The security key can be written only from a secure memory, so it cannot be entered through background commands without the cooperation of a secure user program.
15.5
15.5.1
Initialization Information
Resets
The contents of the ROM array are unaffected by reset.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 441
Chapter 15 Read-Only Memory 64K x 16 (ROM64KX16V1) Block Description
15.5.2
Interrupts
No interrupt is generated by the ROM module.
MC3S12RG128 Data Sheet, Rev. 1.05 442 Freescale Semiconductor
Chapter 16 Serial Communications Interface (SCIV2) Block Description
16.1 Introduction
This block guide provide an overview of serial communication interface (SCI) module. The SCI allows asynchronous serial communications with peripheral devices and other CPUs.
16.1.1
Glossary
IRQ -- Interrupt Request LSB -- Least Significant Bit MSB -- Most Significant Bit NRZ -- Non-Return-to-Zero RZI -- Return-to-Zero-Inverted RXD -- Receive Pin SCI -- Serial Communication Interface TXD -- Transmit Pin
16.1.2
Features
The SCI includes these distinctive features: * Full-duplex operation * Standard mark/space non-return-to-zero (NRZ) format * 13-bit baud rate selection * Programmable 8-bit or 9-bit data format * Separately enabled transmitter and receiver * Programmable transmitter output parity * Two receiver wake up methods: -- Idle line wake-up -- Address mark wake-up * Interrupt-driven operation with eight flags: -- Transmitter empty
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 443
Chapter 16 Serial Communications Interface (SCIV2) Block Description
* * *
-- Transmission complete -- Receiver full -- Idle receiver input -- Receiver overrun -- Noise error -- Framing error -- Parity error Receiver framing error detection Hardware parity checking 1/16 bit-time noise detection
16.1.3
Modes of Operation
The SCI operation is the same independent of device resource mapping and bus interface mode. Different power modes are available to facilitate power saving.
16.1.3.1
Run Mode
Normal mode of operation.
16.1.3.2
Wait Mode
SCI operation in wait mode depends on the state of the SCISWAI bit in the SCI control register 1 (SCICR1). * If SCISWAI is clear, the SCI operates normally when the CPU is in wait mode. * If SCISWAI is set, SCI clock generation ceases and the SCI module enters a power-conservation state when the CPU is in wait mode. Setting SCISWAI does not affect the state of the receiver enable bit, RE, or the transmitter enable bit, TE. * If SCISWAI is set, any transmission or reception in progress stops at wait mode entry. The transmission or reception resumes when either an internal or external interrupt brings the CPU out of wait mode. Exiting wait mode by reset aborts any transmission or reception in progress and resets the SCI.
16.1.3.3
Stop Mode
The SCI is inactive during stop mode for reduced power consumption. The STOP instruction does not affect the SCI register states, but the SCI module clock will be disabled. The SCI operation resumes from where it left off after an external interrupt brings the CPU out of stop mode. Exiting stop mode by reset aborts any transmission or reception in progress and resets the SCI.
MC3S12RG128 Data Sheet, Rev. 1.05 444 Freescale Semiconductor
Chapter 16 Serial Communications Interface (SCIV2) Block Description
16.1.4
Block Diagram
Figure 16-1 is a high level block diagram of the SCI module, showing the interaction of various functional blocks.
SCI DATA REGISTER IRQ GENERATION IDLE IRQ
RX DATA IN
RECEIVE SHIFT REGISTER
BUS CLOCK RECEIVE & WAKE UP CONTROL
RDR/OR IRQ
BAUD GENERATOR
/16
DATA FORMAT CONTROL
TRANSMIT CONTROL IRQ GENERATION
TDRE IRQ
TRANSMIT SHIFT REGISTER
TC IRQ
SCI DATA REGISTER
TXDATA OUT
Figure 16-1. SCI Block Diagram
16.2
External Signal Description
The SCI module has a total of two external pins:
16.2.1
TXD-SCI Transmit Pin
This pin serves as transmit data output of SCI.
16.2.2
RXD-SCI Receive Pin
This pin serves as receive data input of the SCI.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 445
ORING
IRQ TO CPU
Chapter 16 Serial Communications Interface (SCIV2) Block Description
16.3
Memory Map and Registers
This section provides a detailed description of all memory and registers.
16.3.1
Module Memory Map
The memory map for the SCI module is given below in Figure 16-2. The Address listed for each register is the address offset. The total address for each register is the sum of the base address for the SCI module and the address offset for each register.
Address 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 Name SCIBDH SCIBDL SCICR1 SCICR2 SCISR1 SCISR2 SCIDRH SCIDRL R W R W R W R W R W R W R W R W Bit 7 0 6 0 5 0 4 SBR12 SBR4 M ILIE IDLE 0 0 R4 T4 3 SBR11 SBR3 WAKE TE OR 0 0 R3 T3 2 SBR10 SBR2 ILT RE NF 1 SBR9 SBR1 PE RWU FE Bit 0 SBR8 SBR0 PT SBK PF RAF 0 R0 T0
SBR7 LOOPS TIE TDRE 0 R8 R7 T7
SBR6 SCISWAI TCIE TC 0
SBR5 RSRC RIE RDRF 0 0 R5 T5
BRK13 0 R2 T2
TXDIR 0 R1 T1
T8 R6 T6
= Unimplemented or Reserved
Figure 16-2. SCI Register Summary
16.3.2
Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Writes to a reserved register location do not have any effect and reads of these locations return a zero. Details of register bit and field function follow the register diagrams, in bit order.
MC3S12RG128 Data Sheet, Rev. 1.05 446 Freescale Semiconductor
Chapter 16 Serial Communications Interface (SCIV2) Block Description
16.3.2.1
SCI Baud Rate Registers (SCIBDH and SCHBDL)
Module Base + 0x_0000
7 6 5 4 3 2 1 0
R W Reset
0
0
0 SBR12 SBR11 0 SBR10 0 SBR9 0 SBR8 0
0
0
0
0
Module Base + 0x_0001
7 6 5 4 3 2 1 0
R SBR7 W Reset 0 0 0 0 0 1 0 0 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0
= Unimplemented or Reserved
Figure 16-3. SCI Baud Rate Registers (SCIBDH and SCIBDL)
The SCI Baud Rate Register is used by the counter to determine the baud rate of the SCI. The formula for calculating the baud rate is: SCI baud rate = SCI module clock / (16 x BR) where: BR is the content of the SCI baud rate registers, bits SBR12 through SBR0. The baud rate registers can contain a value from 1 to 8191. Read: Anytime. If only SCIBDH is written to, a read will not return the correct data until SCIBDL is written to as well, following a write to SCIBDH. Write: Anytime
Table 16-1. SCIBDH AND SCIBDL Field Descriptions
Field 4-0 7-0 SBR[12:0] Description SCI Baud Rate Bits -- The baud rate for the SCI is determined by these 13 bits. Note: The baud rate generator is disabled until the TE bit or the RE bit is set for the first time after reset. The baud rate generator is disabled when BR = 0. Writing to SCIBDH has no effect without writing to SCIBDL, since writing to SCIBDH puts the data in a temporary location until SCIBDL is written to.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 447
Chapter 16 Serial Communications Interface (SCIV2) Block Description
16.3.2.2
SCI Control Register 1 (SCICR1)
Module Base + 0x_0002
7 6 5 4 3 2 1 0
R LOOPS W Reset 0 0 0 0 0 0 0 0 SCISWAI RSRC M WAKE ILT PE PT
Figure 16-4. SCI Control Register 1 (SCICR1)
Read: Anytime Write: Anytime
Table 16-2. SCICR1 Field Descriptions
Field 7 LOOPS Description Loop Select Bit -- LOOPS enables loop operation. In loop operation, the RXD pin is disconnected from the SCI and the transmitter output is internally connected to the receiver input. Both the transmitter and the receiver must be enabled to use the loop function.See Table 16-3. 0 Normal operation enabled 1 Loop operation enabled Note: The receiver input is determined by the RSRC bit. SCI Stop in Wait Mode Bit -- SCISWAI disables the SCI in wait mode. 0 SCI enabled in wait mode 1 SCI disabled in wait mode Receiver Source Bit -- When LOOPS = 1, the RSRC bit determines the source for the receiver shift register input. 0 Receiver input internally connected to transmitter output 1 Receiver input connected externally to transmitter Data Format Mode Bit -- MODE determines whether data characters are eight or nine bits long. 0 One start bit, eight data bits, one stop bit 1 One start bit, nine data bits, one stop bit Wakeup Condition Bit -- WAKE determines which condition wakes up the SCI: a logic 1 (address mark) in the most significant bit position of a received data character or an idle condition on the RXD. 0 Idle line wakeup 1 Address mark wakeup Idle Line Type Bit -- ILT determines when the receiver starts counting logic 1s as idle character bits. The counting begins either after the start bit or after the stop bit. If the count begins after the start bit, then a string of logic 1s preceding the stop bit may cause false recognition of an idle character. Beginning the count after the stop bit avoids false idle character recognition, but requires properly synchronized transmissions. 0 Idle character bit count begins after start bit 1 Idle character bit count begins after stop bit Parity Enable Bit -- PE enables the parity function. When enabled, the parity function inserts a parity bit in the most significant bit position. 0 Parity function disabled 1 Parity function enabled Parity Type Bit -- PT determines whether the SCI generates and checks for even parity or odd parity. With even parity, an even number of 1s clears the parity bit and an odd number of 1s sets the parity bit. With odd parity, an odd number of 1s clears the parity bit and an even number of 1s sets the parity bit. 0 Even parity 1 Odd parity
6 SCISWAI 5 RSRC
4 M 3 WAKE
2 ILT
1 PE
0 PT
MC3S12RG128 Data Sheet, Rev. 1.05 448 Freescale Semiconductor
Chapter 16 Serial Communications Interface (SCIV2) Block Description
Table 16-3. Loop Functions
LOOPS 0 1 1 RSRC x 0 1 Normal operation Loop mode with Rx input internally connected to Tx output Single-wire mode with Rx input connected to TXD Function
16.3.2.3
SCI Control Register 2 (SCICR2)
Module Base + 0x_0003
7 6 5 4 3 2 1 0
R TIE W Reset 0 0 0 0 0 0 0 0 TCIE RIE ILIE TE RE RWU SBK
Figure 16-5. SCI Control Register 2 (SCICR2)
Read: Anytime Write: Anytime
Table 16-4. SCICR2 Field Descriptions
Field 7 TIE Description Transmitter Interrupt Enable Bit -- TIE enables the transmit data register empty flag, TDRE, to generate interrupt requests. 0 TDRE interrupt requests disabled 1 TDRE interrupt requests enabled Transmission Complete Interrupt Enable Bit -- TCIE enables the transmission complete flag, TC, to generate interrupt requests. 0 TC interrupt requests disabled 1 TC interrupt requests enabled Receiver Full Interrupt Enable Bit -- RIE enables the receive data register full flag, RDRF, or the overrun flag, OR, to generate interrupt requests. 0 RDRF and OR interrupt requests disabled 1 RDRF and OR interrupt requests enabled Idle Line Interrupt Enable Bit -- ILIE enables the idle line flag, IDLE, to generate interrupt requests. 0 IDLE interrupt requests disabled 1 IDLE interrupt requests enabled Transmitter Enable Bit -- TE enables the SCI transmitter and configures the TXD pin as being controlled by the SCI. The TE bit can be used to queue an idle preamble. 0 Transmitter disabled 1 Transmitter enabled Receiver Enable Bit -- RE enables the SCI receiver. 0 Receiver disabled 1 Receiver enabled
6 TCIE
5 RIE
4 ILIE 3 TE
2 RE
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 449
Chapter 16 Serial Communications Interface (SCIV2) Block Description
Table 16-4. SCICR2 Field Descriptions (continued)
Field 1 RWU Description Receiver Wakeup Bit -- Standby state 0 Normal operation. 1 RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU. Send Break Bit -- Toggling SBK sends one break character (10 or 11 logic 0s, respectively 13 or 14 logics 0s if BRK13 is set). Toggling implies clearing the SBK bit before the break character has finished transmitting. As long as SBK is set, the transmitter continues to send complete break characters (10 or 11 bits, respectively 13 or 14 bits). 0 No break characters 1 Transmit break characters
0 SBK
16.3.2.4
SCI Status Register 1 (SCISR1)
The SCISR1 and SCISR2 registers provides inputs to the MCU for generation of SCI interrupts. Also, these registers can be polled by the MCU to check the status of these bits. The flag-clearing procedures require that the status register be read followed by a read or write to the SCI Data Register.It is permissible to execute other instructions between the two steps as long as it does not compromise the handling of I/O, but the order of operations is important for flag clearing.
Module Base + 0x_0004
7 6 5 4 3 2 1 0
R W Reset
TDRE
TC
RDRF
IDLE
OR
NF
FE
PF
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 16-6. SCI Status Register 1 (SCISR1)
Read: Anytime Write: Has no meaning or effect
Table 16-5. SCISR1 Field Descriptions
Field 7 TDRE Description Transmit Data Register Empty Flag -- TDRE is set when the transmit shift register receives a byte from the SCI data register. When TDRE is 1, the transmit data register (SCIDRH/L) is empty and can receive a new value to transmit.Clear TDRE by reading SCI status register 1 (SCISR1), with TDRE set and then writing to SCI data register low (SCIDRL). 0 No byte transferred to transmit shift register 1 Byte transferred to transmit shift register; transmit data register empty Transmit Complete Flag -- TC is set low when there is a transmission in progress or when a preamble or break character is loaded. TC is set high when the TDRE flag is set and no data, preamble, or break character is being transmitted.When TC is set, the TXD out signal becomes idle (logic 1). Clear TC by reading SCI status register 1 (SCISR1) with TC set and then writing to SCI data register low (SCIDRL). TC is cleared automatically when data, preamble, or break is queued and ready to be sent. TC is cleared in the event of a simultaneous set and clear of the TC flag (transmission not complete). 0 Transmission in progress 1 No transmission in progress MC3S12RG128 Data Sheet, Rev. 1.05 450 Freescale Semiconductor
6 TC
Chapter 16 Serial Communications Interface (SCIV2) Block Description
Table 16-5. SCISR1 Field Descriptions (continued)
Field 5 RDRF Description Receive Data Register Full Flag -- RDRF is set when the data in the receive shift register transfers to the SCI data register. Clear RDRF by reading SCI status register 1 (SCISR1) with RDRF set and then reading SCI data register low (SCIDRL). 0 Data not available in SCI data register 1 Received data available in SCI data register Idle Line Flag -- IDLE is set when 10 consecutive logic 1s (if M=0) or 11 consecutive logic 1s (if M=1) appear on the receiver input. Once the IDLE flag is cleared, a valid frame must again set the RDRF flag before an idle condition can set the IDLE flag.Clear IDLE by reading SCI status register 1 (SCISR1) with IDLE set and then reading SCI data register low (SCIDRL). 0 Receiver input is either active now or has never become active since the IDLE flag was last cleared 1 Receiver input has become idle Note: When the receiver wakeup bit (RWU) is set, an idle line condition does not set the IDLE flag. Overrun Flag -- OR is set when software fails to read the SCI data register before the receive shift register receives the next frame. The OR bit is set immediately after the stop bit has been completely received for the second frame. The data in the shift register is lost, but the data already in the SCI data registers is not affected. Clear OR by reading SCI status register 1 (SCISR1) with OR set and then reading SCI data register low (SCIDRL). 0 No overrun 1 Overrun Note: OR flag may read back as set when RDRF flag is clear. This may happen if the following sequence of events occurs: 1. After the first frame is received, read status register SCISR1 (returns RDRF set and OR flag clear); 2. Receive second frame without reading the first frame in the data register (the second frame is not received and OR flag is set); 3. Read data register SCIDRL (returns first frame and clears RDRF flag in the status register); 4. Read status register SCISR1 (returns RDRF clear and OR set). Event 3 may be at exactly the same time as event 2 or any time after. When this happens, a dummy SCIDRL read following event 4 will be required to clear the OR flag if further frames are to be received. Noise Flag -- NF is set when the SCI detects noise on the receiver input. NF bit is set during the same cycle as the RDRF flag but does not get set in the case of an overrun. Clear NF by reading SCI status register 1(SCISR1), and then reading SCI data register low (SCIDRL). 0 No noise 1 Noise Framing Error Flag -- FE is set when a logic 0 is accepted as the stop bit. FE bit is set during the same cycle as the RDRF flag but does not get set in the case of an overrun. FE inhibits further data reception until it is cleared. Clear FE by reading SCI status register 1 (SCISR1) with FE set and then reading the SCI data register low (SCIDRL). 0 No framing error 1 Framing error Parity Error Flag -- PF is set when the parity enable bit (PE) is set and the parity of the received data does not match the parity type bit (PT). PF bit is set during the same cycle as the RDRF flag but does not get set in the case of an overrun. Clear PF by reading SCI status register 1 (SCISR1), and then reading SCI data register low (SCIDRL). 0 No parity error 1 Parity error
4 IDLE
3 OR
2 NF
1 FE
0 PF
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 451
Chapter 16 Serial Communications Interface (SCIV2) Block Description
16.3.2.5
SCI Status Register 2 (SCISR2)
Module Base + 0x_0005
7 6 5 4 3 2 1 0
R W Reset
0
0
0
0
0 BK13 TXDIR 0
RAF
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 16-7. SCI Status Register 2 (SCISR2)
Read: Anytime Write: Anytime; writing accesses SCI status register 2; writing to any bits except TXDIR and BRK13 (SCISR2[1] & [2]) has no effect
Table 16-6. SCISR2 Field Descriptions
Field 2 BK13 Description Break Transmit Character Length -- This bit determines whether the transmit break character is 10 or 11 bit respectively 13 or 14 bits long. The detection of a framing error is not affected by this bit. 0 Break Character is 10 or 11 bit long 1 Break character is 13 or 14 bit long Transmitter Pin Data Direction in Single-Wire Mode. -- This bit determines whether the TXD pin is going to be used as an input or output, in the Single-Wire mode of operation. This bit is only relevant in the Single-Wire mode of operation. 0 TXD pin to be used as an input in Single-Wire mode 1 TXD pin to be used as an output in Single-Wire mode Receiver Active Flag -- RAF is set when the receiver detects a logic 0 during the RT1 time period of the start bit search. RAF is cleared when the receiver detects an idle character. 0 No reception in progress 1 Reception in progress
1 TXDIR
0 RAF
MC3S12RG128 Data Sheet, Rev. 1.05 452 Freescale Semiconductor
Chapter 16 Serial Communications Interface (SCIV2) Block Description
16.3.2.6
SCI Data Registers (SCIDRH and SCIDRL)
Module Base + 0x_0006
7 6 5 4 3 2 1 0
R W Reset
R8 T8 0 0
0
0
0
0
0
0
0
0
0
0
0
0
Module Base + 0x_0007
7 6 5 4 3 2 1 0
R W Reset
R7 T7 0
R6 T6 0
R5 T5 0
R4 T4 0
R3 T3 0
R2 T2 0
R1 T1 0
R0 T0 0
= Unimplemented or Reserved
Figure 16-8. SCI Data Registers (SCIDRH and SCIDRL)
Read: Anytime; reading accesses SCI receive data register Write: Anytime; writing accesses SCI transmit data register; writing to R8 has no effect
Table 16-7. SCIDRH AND SCIDRL Field Descriptions
Field 7 R8 6 T8 7-0 R[7:0] T[7:0] Description Received Bit 8 -- R8 is the ninth data bit received when the SCI is configured for 9-bit data format (M = 1). Transmit Bit 8 -- T8 is the ninth data bit transmitted when the SCI is configured for 9-bit data format (M = 1). Received Bits -- Received bits seven through zero for 9-bit or 8-bit data formats Transmit Bits -- Transmit bits seven through zero for 9-bit or 8-bit formats
NOTE If the value of T8 is the same as in the previous transmission, T8 does not have to be rewritten.The same value is transmitted until T8 is rewritten In 8-bit data format, only SCI data register low (SCIDRL) needs to be accessed. When transmitting in 9-bit data format and using 8-bit write instructions, write first to SCI data register high (SCIDRH), then SCIDRL.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 453
Chapter 16 Serial Communications Interface (SCIV2) Block Description
16.4
Functional Description
This section provides a complete functional description of the SCI block, detailing the operation of the design from the end user perspective in a number of subsections. Figure 16-9 shows the structure of the SCI module. The SCI allows full duplex, asynchronous, NRZ serial communication between the CPU and remote devices, including other CPUs. The SCI transmitter and receiver operate independently, although they use the same baud rate generator. The CPU monitors the status of the SCI, writes the data to be transmitted, and processes received data.
SCI DATA REGISTER R8 RXD RECEIVE SHIFT REGISTER RE RECEIVE AND WAKEUP CONTROL RWU LOOPS RSRC M BUS CLOCK BAUD RATE GENERATOR WAKE DATA FORMAT CONTROL ILT PE PT TE /16 TRANSMIT CONTROL LOOPS SBK RSRC T8 TRANSMIT SHIFT REGISTER SCI DATA REGISTER TDRE TC TCIE TIE RIE NF FE PF RAF IDLE RDRF RDRF/OR IRQ IDLE IRQ OR ILIE
SBR12-SBR0
IRQ TO CPU
TDRE IRQ TXD
Figure 16-9. SCI Block Diagram
MC3S12RG128 Data Sheet, Rev. 1.05 454 Freescale Semiconductor
TC IRQ
Chapter 16 Serial Communications Interface (SCIV2) Block Description
16.4.1
Data Format
The SCI uses the standard NRZ mark/space data format illustrated in Figure 16-10 below.
8-BIT DATA FORMAT BIT M IN SCICR1 CLEAR START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 PARITY OR DATA BIT BIT 7 STOP BIT PARITY OR DATA BIT BIT 7 BIT 8 STOP BIT
NEXT START BIT
9-BIT DATA FORMAT BIT M IN SCICR1 SET START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6
NEXT START BIT
Figure 16-10. SCI Data Formats
Each data character is contained in a frame that includes a start bit, eight or nine data bits, and a stop bit. Clearing the M bit in SCI control register 1 configures the SCI for 8-bit data characters.A frame with eight data bits has a total of 10 bits. Setting the M bit configures the SCI for nine-bit data characters. A frame with nine data bits has a total of 11 bits
Table 16-8. Example of 8-Bit Data Formats
Start Bit 1 1 1
1
Data Bits 8 7 7
Address Bits 0 0 11
Parity Bits 0 1 0
Stop Bit 1 1 1
The address bit identifies the frame as an address character. See Section 16.4.4.6, "Receiver Wakeup".
When the SCI is configured for 9-bit data characters, the ninth data bit is the T8 bit in SCI data register high (SCIDRH). It remains unchanged after transmission and can be used repeatedly without rewriting it. A frame with nine data bits has a total of 11 bits.
Table 16-9. Example of 9-Bit Data Formats
Start Bit 1 1 1
1
Data Bits 9 8 8
Address Bits 0 0 1
1
Parity Bits 0 1 0
Stop Bit 1 1 1
The address bit identifies the frame as an address character. See Section 16.4.4.6, "Receiver Wakeup".
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 455
Chapter 16 Serial Communications Interface (SCIV2) Block Description
16.4.2
Baud Rate Generation
A 13-bit modulus counter in the baud rate generator derives the baud rate for both the receiver and the transmitter. The value from 0 to 8191 written to the SBR12-SBR0 bits determines the module clock divisor. The SBR bits are in the SCI baud rate registers (SCIBDH and SCIBDL). The baud rate clock is synchronized with the bus clock and drives the receiver. The baud rate clock divided by 16 drives the transmitter. The receiver has an acquisition rate of 16 samples per bit time. Baud rate generation is subject to one source of error: Integer division of the module clock may not give the exact target frequency. Table 16-10 lists some examples of achieving target baud rates with a module clock frequency of 25 MHz SCI baud rate = SCI module clock / (16 * SCIBR[12:0])
Table 16-10. Baud Rates (Example: Module Clock = 25 MHz)
Bits SBR[12-0] 41 81 163 326 651 1302 2604 5208 Receiver Clock (Hz) 609,756.1 308,642.0 153,374.2 76,687.1 38,402.5 19,201.2 9600.6 4800.0 Transmitter Clock (Hz) 38,109.8 19,290.1 9585.9 4792.9 2400.2 1200.1 600.0 300.0 Target Baud Rate 38,400 19,200 9600 4800 2400 1200 600 300 Error (%) .76 .47 .16 .15 .01 .01 .00 .00
MC3S12RG128 Data Sheet, Rev. 1.05 456 Freescale Semiconductor
Chapter 16 Serial Communications Interface (SCIV2) Block Description
16.4.3
Transmitter
INTERNAL BUS
BUS CLOCK
BAUD DIVIDER
/ 16
SCI DATA REGISTERS
11-BIT TRANSMIT SHIFT REGISTER 8 7 6 5 4 3 2 1 0
START
SBR12-SBR0 STOP
M
H
L
TXD
MSB
PREAMBLE (ALL ONES)
T8 LOAD FROM SCIDR
LOOP CONTROL BREAK (ALL 0s)
TO RXD
PT
PARITY GENERATION
SHIFT ENABLE
PE
LOOPS RSRC
TRANSMITTER CONTROL
TDRE INTERRUPT REQUEST
TDRE TIE TC TCIE
TE
SBK
TC INTERRUPT REQUEST
Figure 16-11. Transmitter Block Diagram
16.4.3.1
Transmitter Character Length
The SCI transmitter can accommodate either 8-bit or 9-bit data characters. The state of the M bit in SCI control register 1 (SCICR1) determines the length of data characters. When transmitting 9-bit data, bit T8 in SCI data register high (SCIDRH) is the ninth bit (bit 8).
16.4.3.2
Character Transmission
To transmit data, the MCU writes the data bits to the SCI data registers (SCIDRH/SCIDRL), which in turn are transferred to the transmitter shift register. The transmit shift register then shifts a frame out through the Tx output signal, after it has prefaced them with a start bit and appended them with a stop bit. The SCI data registers (SCIDRH and SCIDRL) are the write-only buffers between the internal data bus and the transmit shift register. The SCI also sets a flag, the transmit data register empty flag (TDRE), every time it transfers data from the buffer (SCIDRH/L) to the transmitter shift register.The transmit driver routine may respond to this flag
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 457
Chapter 16 Serial Communications Interface (SCIV2) Block Description
by writing another byte to the Transmitter buffer (SCIDRH/SCIDRL), while the shift register is still shifting out the first byte. To initiate an SCI transmission: 1. Configure the SCI: a) Select a baud rate. Write this value to the SCI baud registers (SCIBDH/L) to begin the baud rate generator. Remember that the baud rate generator is disabled when the baud rate is zero. Writing to the SCIBDH has no effect without also writing to SCIBDL. b) Write to SCICR1 to configure word length, parity, and other configuration bits (LOOPS,RSRC,M,WAKE,ILT,PE,PT). c) Enable the transmitter, interrupts, receive, and wake up as required, by writing to the SCICR2 register bits (TIE,TCIE,RIE,ILIE,TE,RE,RWU,SBK). A preamble or idle character will now be shifted out of the transmitter shift register. 2. Transmit Procedure for Each Byte: a. Poll the TDRE flag by reading the SCISR1 or responding to the TDRE interrupt. Keep in mind that the TDRE bit resets to one. d) If the TDRE flag is set, write the data to be transmitted to SCIDRH/L, where the ninth bit is written to the T8 bit in SCIDRH if the SCI is in 9-bit data format. A new transmission will not result until the TDRE flag has been cleared. 3. Repeat step 2 for each subsequent transmission. NOTE The TDRE flag is set when the shift register is loaded with the next data to be transmitted from SCIDRH/L, which happens, generally speaking, a little over half-way through the stop bit of the previous frame. Specifically, this transfer occurs 9/16ths of a bit time AFTER the start of the stop bit of the previous frame. Writing the TE bit from 0 to a 1 automatically loads the transmit shift register with a preamble of 10 logic 1s (if M = 0) or 11 logic 1s (if M = 1). After the preamble shifts out, control logic transfers the data from the SCI data register into the transmit shift register. A logic 0 start bit automatically goes into the least significant bit position of the transmit shift register. A logic 1 stop bit goes into the most significant bit position. Hardware supports odd or even parity. When parity is enabled, the most significant bit (msb) of the data character is the parity bit. The transmit data register empty flag, TDRE, in SCI status register 1 (SCISR1) becomes set when the SCI data register transfers a byte to the transmit shift register. The TDRE flag indicates that the SCI data register can accept new data from the internal data bus. If the transmit interrupt enable bit, TIE, in SCI control register 2 (SCICR2) is also set, the TDRE flag generates a transmitter interrupt request. When the transmit shift register is not transmitting a frame, the Tx output signal goes to the idle condition, logic 1. If at any time software clears the TE bit in SCI control register 2 (SCICR2), the transmitter enable signal goes low and the transmit signal goes idle.
MC3S12RG128 Data Sheet, Rev. 1.05 458 Freescale Semiconductor
Chapter 16 Serial Communications Interface (SCIV2) Block Description
If software clears TE while a transmission is in progress (TC = 0), the frame in the transmit shift register continues to shift out. To avoid accidentally cutting off the last frame in a message, always wait for TDRE to go high after the last frame before clearing TE. To separate messages with preambles with minimum idle line time, use this sequence between messages: 1. Write the last byte of the first message to SCIDRH/L. 2. Wait for the TDRE flag to go high, indicating the transfer of the last frame to the transmit shift register. 3. Queue a preamble by clearing and then setting the TE bit. 4. Write the first byte of the second message to SCIDRH/L.
16.4.3.3
Break Characters
Writing a logic 1 to the send break bit, SBK, in SCI control register 2 (SCICR2) loads the transmit shift register with a break character. A break character contains all logic 0s and has no start, stop, or parity bit. Break character length depends on the M bit in SCI control register 1 (SCICR1). As long as SBK is at logic 1, transmitter logic continuously loads break characters into the transmit shift register. After software clears the SBK bit, the shift register finishes transmitting the last break character and then transmits at least one logic 1. The automatic logic 1 at the end of a break character guarantees the recognition of the start bit of the next frame. The SCI recognizes a break character when a start bit is followed by eight or nine logic 0 data bits and a logic 0 where the stop bit should be. Receiving a break character has these effects on SCI registers: * Sets the framing error flag, FE * Sets the receive data register full flag, RDRF * Clears the SCI data registers (SCIDRH/L) * May set the overrun flag, OR, noise flag, NF, parity error flag, PE, or the receiver active flag, RAF (see Section 16.3.2.4, "SCI Status Register 1 (SCISR1)" and Section 16.3.2.5, "SCI Status Register 2 (SCISR2)"
16.4.3.4
Idle Characters
An idle character contains all logic 1s and has no start, stop, or parity bit. Idle character length depends on the M bit in SCI control register 1 (SCICR1). The preamble is a synchronizing idle character that begins the first transmission initiated after writing the TE bit from 0 to 1. If the TE bit is cleared during a transmission, the Tx output signal becomes idle after completion of the transmission in progress. Clearing and then setting the TE bit during a transmission queues an idle character to be sent after the frame currently being transmitted.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 459
Chapter 16 Serial Communications Interface (SCIV2) Block Description
NOTE When queueing an idle character, return the TE bit to logic 1 before the stop bit of the current frame shifts out through the Tx output signal. Setting TE after the stop bit appears on Tx output signal causes data previously written to the SCI data register to be lost. Toggle the TE bit for a queued idle character while the TDRE flag is set and immediately before writing the next byte to the SCI data register. NOTE If the TE bit is clear and the transmission is complete, the SCI is not the master of the TXD pin
16.4.4
Receiver
INTERNAL BUS
SBR12-SBR0
SCI DATA REGISTER
11-BIT RECEIVE SHIFT REGISTER 8 7 6 5 4 3 2 1 0
RXD LOOP CONTROL RE RAF LOOPS RSRC M WAKE ILT PE PT
DATA RECOVERY ALL ONES
H
FROM TXD
MSB
FE NF WAKEUP LOGIC PE RWU
PARITY CHECKING IDLE ILIE RDRF
R8
IDLE INTERRUPT REQUEST
RDRF/OR INTERRUPT REQUEST RIE
OR
Figure 16-12. SCI Receiver Block Diagram
16.4.4.1
Receiver Character Length
The SCI receiver can accommodate either 8-bit or 9-bit data characters. The state of the M bit in SCI control register 1 (SCICR1) determines the length of data characters. When receiving 9-bit data, bit R8 in SCI data register high (SCIDRH) is the ninth bit (bit 8).
MC3S12RG128 Data Sheet, Rev. 1.05 460 Freescale Semiconductor
START L
STOP
BUS CLOCK
BAUD DIVIDER
Chapter 16 Serial Communications Interface (SCIV2) Block Description
16.4.4.2
Character Reception
During an SCI reception, the receive shift register shifts a frame in from the Rx input signal. The SCI data register is the read-only buffer between the internal data bus and the receive shift register. After a complete frame shifts into the receive shift register, the data portion of the frame transfers to the SCI data register. The receive data register full flag, RDRF, in SCI status register 1 (SCISR1) becomes set, indicating that the received byte can be read. If the receive interrupt enable bit, RIE, in SCI control register 2 (SCICR2) is also set, the RDRF flag generates an RDRF interrupt request.
16.4.4.3
Data Sampling
The receiver samples the Rx input signal at the RT clock rate. The RT clock is an internal signal with a frequency 16 times the baud rate. To adjust for baud rate mismatch, the RT clock (see Figure 16-13) is re-synchronized: * After every start bit * After the receiver detects a data bit change from logic 1 to logic 0 (after the majority of data bit samples at RT8, RT9, and RT10 returns a valid logic 1 and the majority of the next RT8, RT9, and RT10 samples returns a valid logic 0) To locate the start bit, data recovery logic does an asynchronous search for a logic 0 preceded by three logic 1s.When the falling edge of a possible start bit occurs, the RT clock begins to count to 16.
START BIT Rx Input Signal SAMPLES 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 LSB
START BIT QUALIFICATION
START BIT VERIFICATION
DATA SAMPLING
RT CLOCK RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT1 RT2 RT3 RT10 RT11 RT12 RT13 RT14 RT15 RT CLOCK COUNT RESET RT CLOCK RT16 RT4
Figure 16-13. Receiver Data Sampling
To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7. Table 16-11 summarizes the results of the start bit verification samples.
Table 16-11. Start Bit Verification
RT3, RT5, and RT7 Samples 000 001 010 011 Start Bit Verification Yes Yes Yes No Noise Flag 0 1 1 0
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Chapter 16 Serial Communications Interface (SCIV2) Block Description
Table 16-11. Start Bit Verification
RT3, RT5, and RT7 Samples 100 101 110 111 Start Bit Verification Yes No No No Noise Flag 1 0 0 0
If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins. To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 16-12 summarizes the results of the data bit samples.
Table 16-12. Data Bit Recovery
RT8, RT9, and RT10 Samples 000 001 010 011 100 101 110 111 Data Bit Determination 0 0 0 1 0 1 1 1 Noise Flag 0 1 1 1 1 1 1 0
NOTE The RT8, RT9, and RT10 samples do not affect start bit verification. If any or all of the RT8, RT9, and RT10 start bit samples are logic 1s following a successful start bit verification, the noise flag (NF) is set and the receiver assumes that the bit is a start bit (logic 0). To verify a stop bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 16-13 summarizes the results of the stop bit samples.
Table 16-13. Stop Bit Recovery RT8, RT9, and RT10 Samples
000 001 010 011 100 101 110 111
Framing Error Flag
1 1 1 0 1 0 0 0
Noise Flag
0 1 1 1 1 1 1 0
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Chapter 16 Serial Communications Interface (SCIV2) Block Description
In Figure 16-14 the verification samples RT3 and RT5 determine that the first low detected was noise and not the beginning of a start bit. The RT clock is reset and the start bit search begins again. The noise flag is not set because the noise occurred before the start bit was found.
START BIT Rx Input Signal SAMPLES 1 1 1 0 1 1 1 0 0 0 0 0 0 0 LSB
RT CLOCK RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT1 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT1 RT2 LSB RT6 RT10 RT11 RT12 RT13 RT14 RT15 RT CLOCK COUNT RESET RT CLOCK RT16 RT3 RT7
Figure 16-14. Start Bit Search Example 1
In Figure 16-15, verification sample at RT3 is high. The RT3 sample sets the noise flag. Although the perceived bit time is misaligned, the data samples RT8, RT9, and RT10 are within the bit time and data recovery is successful.
PERCEIVED START BIT ACTUAL START BIT Rx Input Signal SAMPLES 1 1 1 1 1 0 1 0 0 0 0 0
RT CLOCK RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT1 RT2 RT3 RT4 RT10 RT11 RT12 RT13 RT14 RT15 RT CLOCK COUNT RESET RT CLOCK RT16 RT5
Figure 16-15. Start Bit Search Example 2
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Chapter 16 Serial Communications Interface (SCIV2) Block Description
In Figure 16-16, a large burst of noise is perceived as the beginning of a start bit, although the test sample at RT5 is high. The RT5 sample sets the noise flag. Although this is a worst-case misalignment of perceived bit time, the data samples RT8, RT9, and RT10 are within the bit time and data recovery is successful.
PERCEIVED START BIT ACTUAL START BIT Rx input Signal SAMPLES 1 1 1 0 0 1 0 0 0 0 LSB
RT CLOCK RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 LSB RT2 RT10 RT11 RT12 RT13 RT14 RT15 RT CLOCK COUNT RESET RT CLOCK RT16 RT9 RT3
Figure 16-16. Start Bit Search Example 3
Figure 16-17 shows the effect of noise early in the start bit time. Although this noise does not affect proper synchronization with the start bit time, it does set the noise flag.
PERCEIVED AND ACTUAL START BIT Rx Input Signal SAMPLES 1 1 1 1 1 1 1 1 1 0 1 0
RT CLOCK RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT10 RT11 RT12 RT13 RT14 RT15 RT CLOCK COUNT RESET RT CLOCK RT16 RT1
Figure 16-17. Start Bit Search Example 4
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Chapter 16 Serial Communications Interface (SCIV2) Block Description
Figure 16-18 shows a burst of noise near the beginning of the start bit that resets the RT clock. The sample after the reset is low but is not preceded by three high samples that would qualify as a falling edge. Depending on the timing of the start bit search and on the data, the frame may be missed entirely or it may set the framing error flag.
START BIT NO START BIT FOUND 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 0 0 0 0 0 0 LSB
Rx Input Signal SAMPLES
RT CLOCK RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 LSB RT2 RT CLOCK COUNT RESET RT CLOCK RT1 RT3
Figure 16-18. Start Bit Search Example 5
In Figure 16-19, a noise burst makes the majority of data samples RT8, RT9, and RT10 high. This sets the noise flag but does not reset the RT clock. In start bits only, the RT8, RT9, and RT10 data samples are ignored.
START BIT Rx Input Signal SAMPLES 1 1 1 1 1 1 1 1 1 0 0 0 0 1 0 1
RT CLOCK RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT10 RT11 RT12 RT13 RT14 RT15 RT CLOCK COUNT RESET RT CLOCK RT16 RT1
Figure 16-19. Start Bit Search Example 6
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Chapter 16 Serial Communications Interface (SCIV2) Block Description
16.4.4.4
Framing Errors
If the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming frame, it sets the framing error flag, FE, in SCI status register 1 (SCISR1). A break character also sets the FE flag because a break character has no stop bit. The FE flag is set at the same time that the RDRF flag is set.
16.4.4.5
Baud Rate Tolerance
A transmitting device may be operating at a baud rate below or above the receiver baud rate. Accumulated bit time misalignment can cause one of the three stop bit data samples (RT8, RT9, and RT10) to fall outside the actual stop bit.A noise error will occur if the RT8, RT9, and RT10 samples are not all the same logical values. A framing error will occur if the receiver clock is misaligned in such a way that the majority of the RT8, RT9, and RT10 stop bit samples are a logic zero. As the receiver samples an incoming frame, it re-synchronizes the RT clock on any valid falling edge within the frame. Re synchronization within frames will correct a misalignment between transmitter bit times and receiver bit times. 16.4.4.5.1 Slow Data Tolerance
Figure 16-20 shows how much a slow received frame can be misaligned without causing a noise error or a framing error. The slow stop bit begins at RT8 instead of RT1 but arrives in time for the stop bit data samples at RT8, RT9, and RT10.
MSB
STOP
RECEIVER RT CLOCK RT10 RT11 RT12 RT13 RT14 RT15 RT16 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9
DATA SAMPLES
Figure 16-20. Slow Data
Let's take RTr as receiver RT clock and RTt as transmitter RT clock. For an 8-bit data character, it takes the receiver 9 bit times x 16 RTr cycles +7 RTr cycles =151 RTr cycles to start data sampling of the stop bit. With the misaligned character shown in Figure 16-20, the receiver counts 151 RTr cycles at the point when the count of the transmitting device is 9 bit times x 16 RTt cycles = 144 RTt cycles. The maximum percent difference between the receiver count and the transmitter count of a slow 8-bit data character with no errors is: ((151 - 144) / 151) x 100 = 4.63% For a 9-bit data character, it takes the receiver 10 bit times x 16 RTr cycles + 7 RTr cycles = 167 RTr cycles to start data sampling of the stop bit.
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Chapter 16 Serial Communications Interface (SCIV2) Block Description
With the misaligned character shown in Figure 16-20, the receiver counts 167 RTr cycles at the point when the count of the transmitting device is 10 bit times x 16 RTt cycles = 160 RTt cycles. The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit character with no errors is: ((167 - 160) / 167) X 100 = 4.19% 16.4.4.5.2 Fast Data Tolerance
Figure 16-21 shows how much a fast received frame can be misaligned. The fast stop bit ends at RT10 instead of RT16 but is still sampled at RT8, RT9, and RT10.
STOP
IDLE OR NEXT FRAME
RECEIVER RT CLOCK RT10 RT11 RT12 RT13 RT14 RT15 RT16 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9
DATA SAMPLES
Figure 16-21. Fast Data
For an 8-bit data character, it takes the receiver 9 bit times x 16 RTr cycles + 10 RTr cycles = 154 RTr cycles to finish data sampling of the stop bit. With the misaligned character shown in Figure 16-21, the receiver counts 154 RTr cycles at the point when the count of the transmitting device is 10 bit times x 16 RTt cycles = 160 RTt cycles. The maximum percent difference between the receiver count and the transmitter count of a fast 8-bit character with no errors is: ((160 - 154) / 160) x 100 = 3.75% For a 9-bit data character, it takes the receiver 10 bit times x 16 RTr cycles + 10 RTr cycles = 170 RTr cycles to finish data sampling of the stop bit. With the misaligned character shown in Figure 16-21, the receiver counts 170 RTr cycles at the point when the count of the transmitting device is 11 bit times x 16 RTt cycles = 176 RTt cycles. The maximum percent difference between the receiver count and the transmitter count of a fast 9-bit character with no errors is: ((176 - 170) / 176) x 100 = 3.40%
16.4.4.6
Receiver Wakeup
To enable the SCI to ignore transmissions intended only for other receivers in multiple-receiver systems, the receiver can be put into a standby state. Setting the receiver wakeup bit, RWU, in SCI control register 2 (SCICR2) puts the receiver into standby state during which receiver interrupts are disabled.The SCI will still load the receive data into the SCIDRH/L registers, but it will not set the RDRF flag.
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Chapter 16 Serial Communications Interface (SCIV2) Block Description
The transmitting device can address messages to selected receivers by including addressing information in the initial frame or frames of each message. The WAKE bit in SCI control register 1 (SCICR1) determines how the SCI is brought out of the standby state to process an incoming message. The WAKE bit enables either idle line wakeup or address mark wakeup. 16.4.4.6.1 Idle Input Line Wakeup (WAKE = 0)
In this wakeup method, an idle condition on the Rx Input signal clears the RWU bit and wakes up the SCI. The initial frame or frames of every message contain addressing information. All receivers evaluate the addressing information, and receivers for which the message is addressed process the frames that follow. Any receiver for which a message is not addressed can set its RWU bit and return to the standby state. The RWU bit remains set and the receiver remains on standby until another idle character appears on the Rx Input signal. Idle line wakeup requires that messages be separated by at least one idle character and that no message contains idle characters. The idle character that wakes a receiver does not set the receiver idle bit, IDLE, or the receive data register full flag, RDRF. The idle line type bit, ILT, determines whether the receiver begins counting logic 1s as idle character bits after the start bit or after the stop bit. ILT is in SCI control register 1 (SCICR1). 16.4.4.6.2 Address Mark Wakeup (WAKE = 1)
In this wakeup method, a logic 1 in the most significant bit (msb) position of a frame clears the RWU bit and wakes up the SCI. The logic 1 in the msb position marks a frame as an address frame that contains addressing information. All receivers evaluate the addressing information, and the receivers for which the message is addressed process the frames that follow.Any receiver for which a message is not addressed can set its RWU bit and return to the standby state. The RWU bit remains set and the receiver remains on standby until another address frame appears on the Rx Input signal. The logic 1 msb of an address frame clears the receiver's RWU bit before the stop bit is received and sets the RDRF flag. Address mark wakeup allows messages to contain idle characters but requires that the msb be reserved for use in address frames.{sci_wake} NOTE With the WAKE bit clear, setting the RWU bit after the Rx Input signal has been idle can cause the receiver to wake up immediately.
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Chapter 16 Serial Communications Interface (SCIV2) Block Description
16.4.5
Single-Wire Operation
Normally, the SCI uses two pins for transmitting and receiving. In single-wire operation, the RXD pin is disconnected from the SCI. The SCI uses the TXD pin for both receiving and transmitting.
TRANSMITTER Tx OUTPUT SIGNAL Tx INPUT SIGNAL
RECEIVER
RXD
Figure 16-22. Single-Wire Operation (LOOPS = 1, RSRC = 1)
Enable single-wire operation by setting the LOOPS bit and the receiver source bit, RSRC, in SCI control register 1 (SCICR1). Setting the LOOPS bit disables the path from the Rx Input signal to the receiver. Setting the RSRC bit connects the receiver input to the output of the TXD pin driver. Both the transmitter and receiver must be enabled (TE = 1 and RE = 1).The TXDIR bit (SCISR2[1]) determines whether the TXD pin is going to be used as an input (TXDIR = 0) or an output (TXDIR = 1) in this mode of operation.
16.4.6
Loop Operation
In loop operation the transmitter output goes to the receiver input. The Rx Input signal is disconnected from the SCI
.
TRANSMITTER
Tx OUTPUT SIGNAL
RECEIVER
RXD
Figure 16-23. Loop Operation (LOOPS = 1, RSRC = 0)
Enable loop operation by setting the LOOPS bit and clearing the RSRC bit in SCI control register 1 (SCICR1). Setting the LOOPS bit disables the path from the Rx Input signal to the receiver. Clearing the RSRC bit connects the transmitter output to the receiver input. Both the transmitter and receiver must be enabled (TE = 1 and RE = 1).
16.5
16.5.1
Initialization Information
Reset Initialization
The reset state of each individual bit is listed in Section 16.3, "Memory Map and Registers" which details the registers and their bit fields. All special functions or modes which are initialized during or just following reset are described within this section.
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16.5.2
16.5.2.1
Interrupt Operation
System Level Interrupt Sources
There are five interrupt sources that can generate an SCI interrupt in to the CPU. They are listed in Table 16-14.
Table 16-14. SCI Interrupt Source
Interrupt Source Transmitter Transmitter Receiver Receiver Flag TDRE TC RDRF OR IDLE ILIE Local Enable TIE TCIE RIE
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Chapter 16 Serial Communications Interface (SCIV2) Block Description
16.5.2.2
Interrupt Descriptions
The SCI only originates interrupt requests. The following is a description of how the SCI makes a request and how the MCU should acknowledge that request. The interrupt vector offset and interrupt number are chip dependent. The SCI only has a single interrupt line (SCI Interrupt Signal, active high operation) and all the following interrupts, when generated, are ORed together and issued through that port. 16.5.2.2.1 TDRE Description
The TDRE interrupt is set high by the SCI when the transmit shift register receives a byte from the SCI data register. A TDRE interrupt indicates that the transmit data register (SCIDRH/L) is empty and that a new byte can be written to the SCIDRH/L for transmission.Clear TDRE by reading SCI status register 1 with TDRE set and then writing to SCI data register low (SCIDRL). 16.5.2.2.2 TC Description
The TC interrupt is set by the SCI when a transmission has been completed.A TC interrupt indicates that there is no transmission in progress. TC is set high when the TDRE flag is set and no data, preamble, or break character is being transmitted. When TC is set, the TXD pin becomes idle (logic 1). Clear TC by reading SCI status register 1 (SCISR1) with TC set and then writing to SCI data register low (SCIDRL).TC is cleared automatically when data, preamble, or break is queued and ready to be sent. 16.5.2.2.3 RDRF Description
The RDRF interrupt is set when the data in the receive shift register transfers to the SCI data register. A RDRF interrupt indicates that the received data has been transferred to the SCI data register and that the byte can now be read by the MCU. The RDRF interrupt is cleared by reading the SCI status register one (SCISR1) and then reading SCI data register low (SCIDRL). 16.5.2.2.4 OR Description
The OR interrupt is set when software fails to read the SCI data register before the receive shift register receives the next frame. The newly acquired data in the shift register will be lost in this case, but the data already in the SCI data registers is not affected. The OR interrupt is cleared by reading the SCI status register one (SCISR1) and then reading SCI data register low (SCIDRL).
16.5.2.3
IDLE Description
The IDLE interrupt is set when 10 consecutive logic 1s (if M = 0) or 11 consecutive logic 1s (if M = 1) appear on the receiver input. Once the IDLE is cleared, a valid frame must again set the RDRF flag before an idle condition can set the IDLE flag. Clear IDLE by reading SCI status register 1 (SCISR1) with IDLE set and then reading SCI data register low (SCIDRL).
16.5.3
Recovery from Wait Mode
The SCI interrupt request can be used to bring the CPU out of wait mode.
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MC3S12RG128 Data Sheet, Rev. 1.05 472 Freescale Semiconductor
Chapter 16 Serial Communications Interface (SCIV2) Block Description
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 473
Chapter 16 Serial Communications Interface (SCIV2) Block Description
MC3S12RG128 Data Sheet, Rev. 1.05 474 Freescale Semiconductor
Chapter 16 Serial Communications Interface (SCIV2) Block Description
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Chapter 16 Serial Communications Interface (SCIV2) Block Description
MC3S12RG128 Data Sheet, Rev. 1.05 476 Freescale Semiconductor
Chapter 17 Serial Peripheral Interface (SPIV3) Block Description
17.1 Introduction
The SPI module allows a duplex, synchronous, serial communication between the MCU and peripheral devices. Software can poll the SPI status flags or the SPI operation can be interrupt driven.
17.1.1
Features
The SPI includes these distinctive features: * Master mode and slave mode * Bidirectional mode * Slave select output * Mode fault error flag with CPU interrupt capability * Double-buffered data register * Serial clock with programmable polarity and phase * Control of SPI operation during wait mode
17.1.2
Modes of Operation
The SPI functions in three modes, run, wait, and stop. * Run Mode This is the basic mode of operation. * Wait Mode SPI operation in wait mode is a configurable low power mode, controlled by the SPISWAI bit located in the SPICR2 register. In wait mode, if the SPISWAI bit is clear, the SPI operates like in Run Mode. If the SPISWAI bit is set, the SPI goes into a power conservative state, with the SPI clock generation turned off. If the SPI is configured as a master, any transmission in progress stops, but is resumed after CPU goes into Run Mode. If the SPI is configured as a slave, reception and transmission of a byte continues, so that the slave stays synchronized to the master. * Stop Mode The SPI is inactive in stop mode for reduced power consumption. If the SPI is configured as a master, any transmission in progress stops, but is resumed after CPU goes into run mode. If the SPI is configured as a slave, reception and transmission of a byte continues, so that the slave stays synchronized to the master. This is a high level description only, detailed descriptions of operating modes are contained in Section 17.4, "Functional Description."
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17.1.3
Block Diagram
Figure 17-1 gives an overview on the SPI architecture. The main parts of the SPI are status, control, and data registers, shifter logic, baud rate generator, master/slave control logic, and port control logic.
SPI 2 SPI Control Register 1 BIDIROE SPI Control Register 2 2 SPC0 SPI Status Register SPIF SPI Interrupt Request Baud Rate Generator Counter Bus Clock Prescaler Clock Select SPPR 3 SPR 3 Shifter SPI Baud Rate Register LSBFE=1 8 SPI Data Register 8 LSBFE=0 MSB LSBFE=0 LSBFE=1 LSBFE=0 LSBFE=1 LSB data out data in Baud Rate Shift Clock Sample Clock MODF SPTEF Slave Control
CPOL
CPHA
MOSI
Interrupt Control
Phase + SCK in Slave Baud Rate Polarity Control Master Baud Rate Phase + SCK out Polarity Control Master Control
Port Control Logic
SCK
SS
Figure 17-1. SPI Block Diagram
17.2
External Signal Description
This section lists the name and description of all ports including inputs and outputs that do, or may, connect off chip. The SPI module has a total of four external pins.
17.2.1
MOSI -- Master Out/Slave In Pin
This pin is used to transmit data out of the SPI module when it is configured as a master and receive data when it is configured as slave.
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Chapter 17 Serial Peripheral Interface (SPIV3) Block Description
17.2.2
MISO -- Master In/Slave Out Pin
This pin is used to transmit data out of the SPI module when it is configured as a slave and receive data when it is configured as master.
17.2.3
SS -- Slave Select Pin
This pin is used to output the select signal from the SPI module to another peripheral with which a data transfer is to take place when its configured as a master and its used as an input to receive the slave select signal when the SPI is configured as slave.
17.2.4
SCK -- Serial Clock Pin
This pin is used to output the clock with respect to which the SPI transfers data or receive clock in case of slave.
17.3
Memory Map and Register Definition
This section provides a detailed description of address space and registers used by the SPI.
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17.3.1
Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order.
Name 0x0000 SPICR1 0x0001 SPICR2 0x0002 SPIBR 0x0003 SPISR 0x0004 Reserved 0x0005 SPIDR 0x0006 Reserved 0x0007 Reserved R W R W R W R W R W R W R W R W = Unimplemented or Reserved Bit 7 6 5 4 3 2 2 Bit 0 SPIF 0 SPPR2 0 SPPR1 SPTEF 7 SPIE 0 6 SPE 0 5 SPTIE 0 4 MSTR 3 CPOL 2 CPHA 0 1 SSOE 0 LSBFE
MODFEN
BIDIROE 0
SPISWAI
SPC0
SPPR0 MODF
SPR2 0
SPR1 0
SPR0 0
0
Figure 17-2. SPI Register Summary
17.3.1.1
SPI Control Register 1 (SPICR1)
Module Base 0x0000
7 6 5 4 3 2 1 0
R SPIE W Reset 0 0 0 0 0 1 0 0 SPE SPTIE MSTR CPOL CPHA SSOE LSBFE
Figure 17-3. SPI Control Register 1 (SPICR1)
Read: anytime Write: anytime
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Chapter 17 Serial Peripheral Interface (SPIV3) Block Description
Table 17-1. SPICR1 Field Descriptions
Field 7 SPIE 6 SPE Description SPI Interrupt Enable Bit -- This bit enables SPI interrupt requests, if SPIF or MODF status flag is set. 0 SPI interrupts disabled. 1 SPI interrupts enabled. SPI System Enable Bit -- This bit enables the SPI system and dedicates the SPI port pins to SPI system functions. If SPE is cleared, SPI is disabled and forced into idle state, status bits in SPISR register are reset. 0 SPI disabled (lower power consumption). 1 SPI enabled, port pins are dedicated to SPI functions. SPI Transmit Interrupt Enable -- This bit enables SPI interrupt requests, if SPTEF flag is set. 0 SPTEF interrupt disabled. 1 SPTEF interrupt enabled. SPI Master/Slave Mode Select Bit -- This bit selects, if the SPI operates in master or slave mode. Switching the SPI from master to slave or vice versa forces the SPI system into idle state. 0 SPI is in slave mode 1 SPI is in master mode SPI Clock Polarity Bit -- This bit selects an inverted or non-inverted SPI clock. To transmit data between SPI modules, the SPI modules must have identical CPOL values. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. 0 Active-high clocks selected. In idle state SCK is low. 1 Active-low clocks selected. In idle state SCK is high. SPI Clock Phase Bit -- This bit is used to select the SPI clock format. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. 0 Sampling of data occurs at odd edges (1,3,5,...,15) of the SCK clock 1 Sampling of data occurs at even edges (2,4,6,...,16) of the SCK clock Slave Select Output Enable -- The SS output feature is enabled only in master mode, if MODFEN is set, by asserting the SSOE as shown in Table 17-2. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. LSB-First Enable -- This bit does not affect the position of the MSB and LSB in the data register. Reads and writes of the data register always have the MSB in bit 7. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. 0 Data is transferred most significant bit first. 1 Data is transferred least significant bit first.
5 SPTIE 4 MSTR
3 CPOL
2 CPHA
1 SSOE 0 LSBFE
Table 17-2. SS Input / Output Selection
MODFEN 0 0 1 1 SSOE 0 1 0 1 Master Mode SS not used by SPI SS not used by SPI SS input with MODF feature SS is slave select output Slave Mode SS input SS input SS input SS input
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17.3.1.2
SPI Control Register 2 (SPICR2)
Module Base 0x0001
7 6 5 4 3 2 1 0
R W Reset
0
0
0 MODFEN BIDIROE 0
0 SPISWAI 0 0 SPC0 0
0
0
0
0
= Unimplemented or Reserved
Figure 17-4. SPI Control Register 2 (SPICR2)
Read: anytime Write: anytime; writes to the reserved bits have no effect
Table 17-3. SPICR2 Field Descriptions
Field 4 MODFEN Description Mode Fault Enable Bit -- This bit allows the MODF failure being detected. If the SPI is in master mode and MODFEN is cleared, then the SS port pin is not used by the SPI. In slave mode, the SS is available only as an input regardless of the value of MODFEN. For an overview on the impact of the MODFEN bit on the SS port pin configuration refer to Table 17-2. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. 0 SS port pin is not used by the SPI 1 SS port pin with MODF feature Output Enable in the Bidirectional Mode of Operation -- This bit controls the MOSI and MISO output buffer of the SPI, when in bidirectional mode of operation (SPC0 is set). In master mode this bit controls the output buffer of the MOSI port, in slave mode it controls the output buffer of the MISO port. In master mode, with SPC0 set, a change of this bit will abort a transmission in progress and force the SPI into idle state. 0 Output buffer disabled 1 Output buffer enabled SPI Stop in Wait Mode Bit -- This bit is used for power conservation while in wait mode. 0 SPI clock operates normally in wait mode 1 Stop SPI clock generation when in wait mode Serial Pin Control Bit 0 -- This bit enables bidirectional pin configurations as shown in Table 17-4. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state
3 BIDIROE
1 SPISWAI 0 SPC0
Table 17-4. Bidirectional Pin Configurations
Pin Mode SPC0 BIDIROE MISO MOSI
Master Mode of Operation Normal Bidirectional 0 1 X 0 1 Slave Mode of Operation Normal 0 X Slave Out Slave In Master In MISO not used by SPI Master Out Master In Master I/O
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Chapter 17 Serial Peripheral Interface (SPIV3) Block Description
Table 17-4. Bidirectional Pin Configurations (continued)
Pin Mode Bidirectional SPC0 1 BIDIROE 0 1 MISO Slave In Slave I/O MOSI MOSI not used by SPI
17.3.1.3
SPI Baud Rate Register (SPIBR)
Module Base 0x0002
7 6 5 4 3 2 1 0
R W Reset
0 SPPR2 0 0 SPPR1 0 SPPR0 0
0 SPR2 0 0 SPR1 0 SPR0 0
= Unimplemented or Reserved
Figure 17-5. SPI Baud Rate Register (SPIBR)
Read: anytime Write: anytime; writes to the reserved bits have no effect
Table 17-5. SPIBR Field Descriptions
Field 6:4 SPPR[2:0] 2:0 SPR[2:0} Description SPI Baud Rate Preselection Bits -- These bits specify the SPI baud rates as shown in Table 17-6. In master mode, a change of these bits will abort a transmission in progress and force the SPI system into idle state. SPI Baud Rate Selection Bits -- These bits specify the SPI baud rates as shown in Table 17-6. In master mode, a change of these bits will abort a transmission in progress and force the SPI system into idle state.
The baud rate divisor equation is as follows:
BaudRateDivisor = ( SPPR + 1 ) * 2 ( SPR + 1 )
The baud rate can be calculated with the following equation:
Baud Rate = BusClock BaudRateDivisor
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 483
Chapter 17 Serial Peripheral Interface (SPIV3) Block Description
Table 17-6. Example SPI Baud Rate Selection (25 MHz Bus Clock)
SPPR2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 SPPR1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 SPPR0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 SPR2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 SPR1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 SPR0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Baud Rate Divisor 2 4 8 16 32 64 128 256 4 8 16 32 64 128 256 512 6 12 24 48 96 192 384 768 8 16 32 64 128 256 512 1024 10 20 40 80 160 320 640 Baud Rate 12.5 MHz 6.25 MHz 3.125 MHz 1.5625 MHz 781.25 kHz 390.63 kHz 195.31 kHz 97.66 kHz 6.25 MHz 3.125 MHz 1.5625 MHz 781.25 kHz 390.63 kHz 195.31 kHz 97.66 kHz 48.83 kHz 4.16667 MHz 2.08333 MHz 1.04167 MHz 520.83 kHz 260.42 kHz 130.21 kHz 65.10 kHz 32.55 kHz 3.125 MHz 1.5625 MHz 781.25 kHz 390.63 kHz 195.31 kHz 97.66 kHz 48.83 kHz 24.41 kHz 2.5 MHz 1.25 MHz 625 kHz 312.5 kHz 156.25 kHz 78.13 kHz 39.06 kHz
MC3S12RG128 Data Sheet, Rev. 1.05 484 Freescale Semiconductor
Chapter 17 Serial Peripheral Interface (SPIV3) Block Description
Table 17-6. Example SPI Baud Rate Selection (25 MHz Bus Clock) (continued)
SPPR2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 SPPR1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 SPPR0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 SPR2 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SPR1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SPR0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Baud Rate Divisor 1280 12 24 48 96 192 384 768 1536 14 28 56 112 224 448 896 1792 16 32 64 128 256 512 1024 2048 Baud Rate 19.53 kHz 2.08333 MHz 1.04167 MHz 520.83 kHz 260.42 kHz 130.21 kHz 65.10 kHz 32.55 kHz 16.28 kHz 1.78571 MHz 892.86 kHz 446.43 kHz 223.21 kHz 111.61 kHz 55.80 kHz 27.90 kHz 13.95 kHz 1.5625 MHz 781.25 kHz 390.63 kHz 195.31 kHz 97.66 kHz 48.83 kHz 24.41 kHz 12.21 kHz
NOTE In slave mode of SPI S-clock speed DIV2 is not supported.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 485
Chapter 17 Serial Peripheral Interface (SPIV3) Block Description
17.3.1.4
SPI Status Register (SPISR)
Module Base 0x0003
7 6 5 4 3 2 1 0
R W Reset
SPIF
0
SPTEF
MODF
0
0
0
0
0
0
1
0
0
0
0
0
= Unimplemented or Reserved
Figure 17-6. SPI Status Register (SPISR)
Read: anytime Write: has no effect
Table 17-7. SPISR Field Descriptions
Field 7 SPIF Description SPIF Interrupt Flag -- This bit is set after a received data byte has been transferred into the SPI Data Register. This bit is cleared by reading the SPISR register (with SPIF set) followed by a read access to the SPI Data Register. 0 Transfer not yet complete 1 New data copied to SPIDR SPI Transmit Empty Interrupt Flag -- If set, this bit indicates that the transmit data register is empty. To clear this bit and place data into the transmit data register, SPISR has to be read with SPTEF = 1, followed by a write to SPIDR. Any write to the SPI Data Register without reading SPTEF = 1, is effectively ignored. 0 SPI Data register not empty 1 SPI Data register empty Mode Fault Flag -- This bit is set if the SS input becomes low while the SPI is configured as a master and mode fault detection is enabled, MODFEN bit of SPICR2 register is set. Refer to MODFEN bit description in Section 17.3.1.2, "SPI Control Register 2 (SPICR2)." The flag is cleared automatically by a read of the SPI Status Register (with MODF set) followed by a write to the SPI Control Register 1. 0 Mode fault has not occurred. 1 Mode fault has occurred.
5 SPTEF
4 MODF
17.3.1.5
SPI Data Register (SPIDR)
Module Base 0x0005
7 6 5 4 3 2 1 0
R Bit 7 W Reset 0 0 0 0 0 0 0 0 6 5 4 3 2 2 Bit 0
= Unimplemented or Reserved
Figure 17-7. SPI Data Register (SPIDR)
Read: anytime; normally read only after SPIF is set
MC3S12RG128 Data Sheet, Rev. 1.05 486 Freescale Semiconductor
Chapter 17 Serial Peripheral Interface (SPIV3) Block Description
Write: anytime The SPI Data Register is both the input and output register for SPI data. A write to this register allows a data byte to be queued and transmitted. For a SPI configured as a master, a queued data byte is transmitted immediately after the previous transmission has completed. The SPI Transmitter Empty Flag SPTEF in the SPISR register indicates when the SPI Data Register is ready to accept new data. Reading the data can occur anytime from after the SPIF is set to before the end of the next transfer. If the SPIF is not serviced by the end of the successive transfers, those data bytes are lost and the data within the SPIDR retains the first byte until SPIF is serviced.
17.4
Functional Description
The SPI module allows a duplex, synchronous, serial communication between the MCU and peripheral devices. Software can poll the SPI status flags or SPI operation can be interrupt driven. The SPI system is enabled by setting the SPI enable (SPE) bit in SPI Control Register 1. While SPE bit is set, the four associated SPI port pins are dedicated to the SPI function as: * Slave select (SS) * Serial clock (SCK) * Master out/slave in (MOSI) * Master in/slave out (MISO) The main element of the SPI system is the SPI Data Register. The 8-bit data register in the master and the 8-bit data register in the slave are linked by the MOSI and MISO pins to form a distributed 16-bit register. When a data transfer operation is performed, this 16-bit register is serially shifted eight bit positions by the S-clock from the master, so data is exchanged between the master and the slave. Data written to the master SPI Data Register becomes the output data for the slave, and data read from the master SPI Data Register after a transfer operation is the input data from the slave. A read of SPISR with SPTEF = 1 followed by a write to SPIDR puts data into the transmit data register. When a transfer is complete, received data is moved into the receive data register. Data may be read from this double-buffered system any time before the next transfer has completed. This 8-bit data register acts as the SPI receive data register for reads and as the SPI transmit data register for writes. A single SPI register address is used for reading data from the read data buffer and for writing data to the transmit data register. The clock phase control bit (CPHA) and a clock polarity control bit (CPOL) in the SPI Control Register 1 (SPICR1) select one of four possible clock formats to be used by the SPI system. The CPOL bit simply selects a non-inverted or inverted clock. The CPHA bit is used to accommodate two fundamentally different protocols by sampling data on odd numbered SCK edges or on even numbered SCK edges (see Section 17.4.3, "Transmission Formats"). The SPI can be configured to operate as a master or as a slave. When the MSTR bit in SPI Control Register1 is set, master mode is selected, when the MSTR bit is clear, slave mode is selected.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 487
Chapter 17 Serial Peripheral Interface (SPIV3) Block Description
17.4.1
Master Mode
The SPI operates in master mode when the MSTR bit is set. Only a master SPI module can initiate transmissions. A transmission begins by writing to the master SPI Data Register. If the shift register is empty, the byte immediately transfers to the shift register. The byte begins shifting out on the MOSI pin under the control of the serial clock. * S-clock The SPR2, SPR1, and SPR0 baud rate selection bits in conjunction with the SPPR2, SPPR1, and SPPR0 baud rate preselection bits in the SPI Baud Rate register control the baud rate generator and determine the speed of the transmission. The SCK pin is the SPI clock output. Through the SCK pin, the baud rate generator of the master controls the shift register of the slave peripheral. * MOSI and MISO Pins In master mode, the function of the serial data output pin (MOSI) and the serial data input pin (MISO) is determined by the SPC0 and BIDIROE control bits. * SS Pin If MODFEN and SSOE bit are set, the SS pin is configured as slave select output. The SS output becomes low during each transmission and is high when the SPI is in idle state. If MODFEN is set and SSOE is cleared, the SS pin is configured as input for detecting mode fault error. If the SS input becomes low this indicates a mode fault error where another master tries to drive the MOSI and SCK lines. In this case, the SPI immediately switches to slave mode, by clearing the MSTR bit and also disables the slave output buffer MISO (or SISO in bidirectional mode). So the result is that all outputs are disabled and SCK, MOSI and MISO are inputs. If a transmission is in progress when the mode fault occurs, the transmission is aborted and the SPI is forced into idle state. This mode fault error also sets the mode fault (MODF) flag in the SPI Status Register (SPISR). If the SPI interrupt enable bit (SPIE) is set when the MODF flag gets set, then an SPI interrupt sequence is also requested. When a write to the SPI Data Register in the master occurs, there is a half SCK-cycle delay. After the delay, SCK is started within the master. The rest of the transfer operation differs slightly, depending on the clock format specified by the SPI clock phase bit, CPHA, in SPI Control Register 1 (see Section 17.4.3, "Transmission Formats"). NOTE A change of the bits CPOL, CPHA, SSOE, LSBFE, MODFEN, SPC0, BIDIROE with SPC0 set, SPPR2-SPPR0 and SPR2-SPR0 in master mode will abort a transmission in progress and force the SPI into idle state. The remote slave cannot detect this, therefore the master has to ensure that the remote slave is set back to idle state.
MC3S12RG128 Data Sheet, Rev. 1.05 488 Freescale Semiconductor
Chapter 17 Serial Peripheral Interface (SPIV3) Block Description
17.4.2
Slave Mode
The SPI operates in slave mode when the MSTR bit in SPI Control Register1 is clear. * SCK Clock In slave mode, SCK is the SPI clock input from the master. * MISO and MOSI Pins In slave mode, the function of the serial data output pin (MISO) and serial data input pin (MOSI) is determined by the SPC0 bit and BIDIROE bit in SPI Control Register 2. * SS Pin The SS pin is the slave select input. Before a data transmission occurs, the SS pin of the slave SPI must be low. SS must remain low until the transmission is complete. If SS goes high, the SPI is forced into idle state. The SS input also controls the serial data output pin, if SS is high (not selected), the serial data output pin is high impedance, and, if SS is low the first bit in the SPI Data Register is driven out of the serial data output pin. Also, if the slave is not selected (SS is high), then the SCK input is ignored and no internal shifting of the SPI shift register takes place. Although the SPI is capable of duplex operation, some SPI peripherals are capable of only receiving SPI data in a slave mode. For these simpler devices, there is no serial data out pin. NOTE When peripherals with duplex capability are used, take care not to simultaneously enable two receivers whose serial outputs drive the same system slave's serial data output line. As long as no more than one slave device drives the system slave's serial data output line, it is possible for several slaves to receive the same transmission from a master, although the master would not receive return information from all of the receiving slaves. If the CPHA bit in SPI Control Register 1 is clear, odd numbered edges on the SCK input cause the data at the serial data input pin to be latched. Even numbered edges cause the value previously latched from the serial data input pin to shift into the LSB or MSB of the SPI shift register, depending on the LSBFE bit. If the CPHA bit is set, even numbered edges on the SCK input cause the data at the serial data input pin to be latched. Odd numbered edges cause the value previously latched from the serial data input pin to shift into the LSB or MSB of the SPI shift register, depending on the LSBFE bit. When CPHA is set, the first edge is used to get the first data bit onto the serial data output pin. When CPHA is clear and the SS input is low (slave selected), the first bit of the SPI data is driven out of the serial data output pin. After the eighth shift, the transfer is considered complete and the received data is transferred into the SPI Data Register. To indicate transfer is complete, the SPIF flag in the SPI Status Register is set. NOTE A change of the bits CPOL, CPHA, SSOE, LSBFE, MODFEN, SPC0 and BIDIROE with SPC0 set in slave mode will corrupt a transmission in progress and has to be avoided.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 489
Chapter 17 Serial Peripheral Interface (SPIV3) Block Description
17.4.3
Transmission Formats
During an SPI transmission, data is transmitted (shifted out serially) and received (shifted in serially) simultaneously. The serial clock (SCK) synchronizes shifting and sampling of the information on the two serial data lines. A slave select line allows selection of an individual slave SPI device, slave devices that are not selected do not interfere with SPI bus activities. Optionally, on a master SPI device, the slave select line can be used to indicate multiple-master bus contention.
MASTER SPI MISO MOSI SCK BAUD RATE GENERATOR SS MISO MOSI SCK SS SLAVE SPI
SHIFT REGISTER
SHIFT REGISTER
VDD
Figure 17-8. Master/Slave Transfer Block Diagram
17.4.3.1
Clock Phase and Polarity Controls
Using two bits in the SPI Control Register1, software selects one of four combinations of serial clock phase and polarity. The CPOL clock polarity control bit specifies an active high or low clock and has no significant effect on the transmission format. The CPHA clock phase control bit selects one of two fundamentally different transmission formats. Clock phase and polarity should be identical for the master SPI device and the communicating slave device. In some cases, the phase and polarity are changed between transmissions to allow a master device to communicate with peripheral slaves having different requirements.
17.4.3.2
CPHA = 0 Transfer Format
The first edge on the SCK line is used to clock the first data bit of the slave into the master and the first data bit of the master into the slave. In some peripherals, the first bit of the slave's data is available at the slave's data out pin as soon as the slave is selected. In this format, the first SCK edge is issued a half cycle after SS has become low. A half SCK cycle later, the second edge appears on the SCK line. When this second edge occurs, the value previously latched from the serial data input pin is shifted into the LSB or MSB of the shift register, depending on LSBFE bit. After this second edge, the next bit of the SPI master data is transmitted out of the serial data output pin of the master to the serial input pin on the slave. This process continues for a total of 16 edges on the SCK line, with data being latched on odd numbered edges and shifted on even numbered edges.
MC3S12RG128 Data Sheet, Rev. 1.05 490 Freescale Semiconductor
Chapter 17 Serial Peripheral Interface (SPIV3) Block Description
Data reception is double buffered. Data is shifted serially into the SPI shift register during the transfer and is transferred to the parallel SPI Data Register after the last bit is shifted in. After the 16th (last) SCK edge: * Data that was previously in the master SPI Data Register should now be in the slave data register and the data that was in the slave data register should be in the master. * The SPIF flag in the SPI Status Register is set indicating that the transfer is complete. Figure 17-9 is a timing diagram of an SPI transfer where CPHA = 0. SCK waveforms are shown for CPOL = 0 and CPOL = 1. The diagram may be interpreted as a master or slave timing diagram because the SCK, MISO, and MOSI pins are connected directly between the master and the slave. The MISO signal is the output from the slave and the MOSI signal is the output from the master. The SS pin of the master must be either high or reconfigured as a general-purpose output not affecting the SPI.
End of Idle State SCK Edge Nr. SCK (CPOL = 0) SCK (CPOL = 1) 1 2 Begin 3 4 5 6 Transfer 7 8 9 10 11 12 End 13 14 15 16 Begin of Idle State
CHANGE O MOSI pin CHANGE O MISO pin SEL SS (O) Master only SEL SS (I) tL MSB first (LSBFE = 0): MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 LSB first (LSBFE = 1): LSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 tL = Minimum leading time before the first SCK edge tT = Minimum trailing time after the last SCK edge tI = Minimum idling time between transfers (minimum SS high time) tL, tT, and tI are guaranteed for the master mode and required for the slave mode. Bit 1 Bit 6 tT tI tL
LSB Minimum 1/2 SCK for tT, tl, tL MSB
Figure 17-9. SPI Clock Format 0 (CPHA = 0)
In slave mode, if the SS line is not deasserted between the successive transmissions then the content of the SPI Data Register is not transmitted, instead the last received byte is transmitted. If the SS line is deasserted for at least minimum idle time (half SCK cycle) between successive transmissions then the content of the SPI Data Register is transmitted.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 491
If next transfer begins here
SAMPLE I MOSI/MISO
Chapter 17 Serial Peripheral Interface (SPIV3) Block Description
In master mode, with slave select output enabled the SS line is always deasserted and reasserted between successive transfers for at least minimum idle time.
17.4.3.3
CPHA = 1 Transfer Format
Some peripherals require the first SCK edge before the first data bit becomes available at the data out pin, the second edge clocks data into the system. In this format, the first SCK edge is issued by setting the CPHA bit at the beginning of the 8-cycle transfer operation. The first edge of SCK occurs immediately after the half SCK clock cycle synchronization delay. This first edge commands the slave to transfer its first data bit to the serial data input pin of the master. A half SCK cycle later, the second edge appears on the SCK pin. This is the latching edge for both the master and slave. When the third edge occurs, the value previously latched from the serial data input pin is shifted into the LSB or MSB of the SPI shift register, depending on LSBFE bit. After this edge, the next bit of the master data is coupled out of the serial data output pin of the master to the serial input pin on the slave. This process continues for a total of 16 edges on the SCK line with data being latched on even numbered edges and shifting taking place on odd numbered edges. Data reception is double buffered, data is serially shifted into the SPI shift register during the transfer and is transferred to the parallel SPI Data Register after the last bit is shifted in. After the 16th SCK edge: * Data that was previously in the SPI Data Register of the master is now in the data register of the slave, and data that was in the data register of the slave is in the master. * The SPIF flag bit in SPISR is set indicating that the transfer is complete. Figure 17-10 shows two clocking variations for CPHA = 1. The diagram may be interpreted as a master or slave timing diagram because the SCK, MISO, and MOSI pins are connected directly between the master and the slave. The MISO signal is the output from the slave, and the MOSI signal is the output from the master. The SS line is the slave select input to the slave. The SS pin of the master must be either high or reconfigured as a general-purpose output not affecting the SPI. The SS line can remain active low between successive transfers (can be tied low at all times). This format is sometimes preferred in systems having a single fixed master and a single slave that drive the MISO data line. * Back-to-back transfers in master mode In master mode, if a transmission has completed and a new data byte is available in the SPI Data Register, this byte is send out immediately without a trailing and minimum idle time. The SPI interrupt request flag (SPIF) is common to both the master and slave modes. SPIF gets set one half SCK cycle after the last SCK edge.
MC3S12RG128 Data Sheet, Rev. 1.05 492 Freescale Semiconductor
Chapter 17 Serial Peripheral Interface (SPIV3) Block Description
End of Idle State SCK Edge Nr. SCK (CPOL = 0) SCK (CPOL = 1) 1 2 3
Begin 4 5 6 7
Transfer 8 9 10 11 12
End 13 14 15 16
Begin of Idle State
CHANGE O MOSI pin CHANGE O MISO pin SEL SS (O) Master only SEL SS (I) tL MSB first (LSBFE = 0): LSB first (LSBFE = 1): tT tI tL
MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB Minimum 1/2 SCK for tT, tl, tL LSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB tL = Minimum leading time before the first SCK edge, not required for back to back transfers tT = Minimum trailing time after the last SCK edge tI = Minimum idling time between transfers (minimum SS high time), not required for back to back transfers
Figure 17-10. SPI Clock Format 1 (CPHA = 1)
17.4.4
SPI Baud Rate Generation
Baud rate generation consists of a series of divider stages. Six bits in the SPI Baud Rate register (SPPR2, SPPR1, SPPR0, SPR2, SPR1, and SPR0) determine the divisor to the SPI module clock which results in the SPI baud rate. The SPI clock rate is determined by the product of the value in the baud rate preselection bits (SPPR2-SPPR0) and the value in the baud rate selection bits (SPR2-SPR0). The module clock divisor equation is shown in Figure 17-11 When all bits are clear (the default condition), the SPI module clock is divided by 2. When the selection bits (SPR2-SPR0) are 001 and the preselection bits (SPPR2-SPPR0) are 000, the module clock divisor becomes 4. When the selection bits are 010, the module clock divisor becomes 8 etc. When the preselection bits are 001, the divisor determined by the selection bits is multiplied by 2. When the preselection bits are 010, the divisor is multiplied by 3, etc. See Table 17-6 for baud rate calculations for all bit conditions, based on a 25-MHz bus clock. The two sets of selects allows the clock to be divided by a non-power of two to achieve other baud rates such as divide by 6, divide by 10, etc.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 493
If next transfer begins here
SAMPLE I MOSI/MISO
Chapter 17 Serial Peripheral Interface (SPIV3) Block Description
The baud rate generator is activated only when the SPI is in the master mode and a serial transfer is taking place. In the other cases, the divider is disabled to decrease IDD current.
BaudRateDivisor = ( SPPR + 1 ) * 2 ( SPR + 1 )
Figure 17-11. Baud Rate Divisor Equation
17.4.5
17.4.5.1
Special Features
SS Output
The SS output feature automatically drives the SS pin low during transmission to select external devices and drives it high during idle to deselect external devices. When SS output is selected, the SS output pin is connected to the SS input pin of the external device. The SS output is available only in master mode during normal SPI operation by asserting SSOE and MODFEN bit as shown in Table 17-2. The mode fault feature is disabled while SS output is enabled. NOTE Care must be taken when using the SS output feature in a multimaster system because the mode fault feature is not available for detecting system errors between masters.
17.4.5.2
Bidirectional Mode (MOSI or MISO)
The bidirectional mode is selected when the SPC0 bit is set in SPI Control Register 2 (see Table 17-8). In this mode, the SPI uses only one serial data pin for the interface with external device(s). The MSTR bit decides which pin to use. The MOSI pin becomes the serial data I/O (MOMI) pin for the master mode, and the MISO pin becomes serial data I/O (SISO) pin for the slave mode. The MISO pin in master mode and MOSI pin in slave mode are not used by the SPI.
Table 17-8. Normal Mode and Bidirectional Mode
When SPE = 1 Master Mode MSTR = 1
Serial Out MOSI
Slave Mode MSTR = 0
Serial In SPI MISO Serial Out MISO MOSI
Normal Mode SPC0 = 0
SPI Serial In
Serial Out
MOMI BIDIROE
Serial In BIDIROE SPI Serial Out SISO
Bidirectional Mode SPC0 = 1
SPI Serial In
MC3S12RG128 Data Sheet, Rev. 1.05 494 Freescale Semiconductor
Chapter 17 Serial Peripheral Interface (SPIV3) Block Description
The direction of each serial I/O pin depends on the BIDIROE bit. If the pin is configured as an output, serial data from the shift register is driven out on the pin. The same pin is also the serial input to the shift register. The SCK is output for the master mode and input for the slave mode. The SS is the input or output for the master mode, and it is always the input for the slave mode. The bidirectional mode does not affect SCK and SS functions. NOTE In bidirectional master mode, with mode fault enabled, both data pins MISO and MOSI can be occupied by the SPI, though MOSI is normally used for transmissions in bidirectional mode and MISO is not used by the SPI. If a mode fault occurs, the SPI is automatically switched to slave mode, in this case MISO becomes occupied by the SPI and MOSI is not used. This has to be considered, if the MISO pin is used for other purpose.
17.4.6
Error Conditions
The SPI has one error condition: * Mode fault error
17.4.6.1
Mode Fault Error
If the SS input becomes low while the SPI is configured as a master, it indicates a system error where more than one master may be trying to drive the MOSI and SCK lines simultaneously. This condition is not permitted in normal operation, the MODF bit in the SPI Status Register is set automatically provided the MODFEN bit is set. In the special case where the SPI is in master mode and MODFEN bit is cleared, the SS pin is not used by the SPI. In this special case, the mode fault error function is inhibited and MODF remains cleared. In case the SPI system is configured as a slave, the SS pin is a dedicated input pin. Mode fault error doesn't occur in slave mode. If a mode fault error occurs the SPI is switched to slave mode, with the exception that the slave output buffer is disabled. So SCK, MISO and MOSI pins are forced to be high impedance inputs to avoid any possibility of conflict with another output driver. A transmission in progress is aborted and the SPI is forced into idle state. If the mode fault error occurs in the bidirectional mode for a SPI system configured in master mode, output enable of the MOMI (MOSI in bidirectional mode) is cleared if it was set. No mode fault error occurs in the bidirectional mode for SPI system configured in slave mode. The mode fault flag is cleared automatically by a read of the SPI Status Register (with MODF set) followed by a write to SPI Control Register 1. If the mode fault flag is cleared, the SPI becomes a normal master or slave again.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 495
Chapter 17 Serial Peripheral Interface (SPIV3) Block Description
17.4.7
Operation in Run Mode
In run mode with the SPI system enable (SPE) bit in the SPI control register clear, the SPI system is in a low-power, disabled state. SPI registers remain accessible, but clocks to the core of this module are disabled.
17.4.8
Operation in Wait Mode
SPI operation in wait mode depends upon the state of the SPISWAI bit in SPI Control Register 2. * If SPISWAI is clear, the SPI operates normally when the CPU is in wait mode * If SPISWAI is set, SPI clock generation ceases and the SPI module enters a power conservation state when the CPU is in wait mode. -- If SPISWAI is set and the SPI is configured for master, any transmission and reception in progress stops at wait mode entry. The transmission and reception resumes when the SPI exits wait mode. -- If SPISWAI is set and the SPI is configured as a slave, any transmission and reception in progress continues if the SCK continues to be driven from the master. This keeps the slave synchronized to the master and the SCK. If the master transmits several bytes while the slave is in wait mode, the slave will continue to send out bytes consistent with the operation mode at the start of wait mode (i.e. If the slave is currently sending its SPIDR to the master, it will continue to send the same byte. Else if the slave is currently sending the last received byte from the master, it will continue to send each previous master byte). NOTE Care must be taken when expecting data from a master while the slave is in wait or stop mode. Even though the shift register will continue to operate, the rest of the SPI is shut down (i.e. a SPIF interrupt will not be generated until exiting stop or wait mode). Also, the byte from the shift register will not be copied into the SPIDR register until after the slave SPI has exited wait or stop mode. A SPIF flag and SPIDR copy is only generated if wait mode is entered or exited during a tranmission. If the slave enters wait mode in idle mode and exits wait mode in idle mode, neither a SPIF nor a SPIDR copy will occur.
17.4.9
Operation in Stop Mode
Stop mode is dependent on the system. The SPI enters stop mode when the module clock is disabled (held high or low). If the SPI is in master mode and exchanging data when the CPU enters stop mode, the transmission is frozen until the CPU exits stop mode. After stop, data to and from the external SPI is exchanged correctly. In slave mode, the SPI will stay synchronized with the master. The stop mode is not dependent on the SPISWAI bit.
MC3S12RG128 Data Sheet, Rev. 1.05 496 Freescale Semiconductor
Chapter 17 Serial Peripheral Interface (SPIV3) Block Description
17.5
Reset
The reset values of registers and signals are described in the Memory Map and Registers section (see Section 17.3, "Memory Map and Register Definition") which details the registers and their bit-fields. * If a data transmission occurs in slave mode after reset without a write to SPIDR, it will transmit garbage, or the byte last received from the master before the reset. * Reading from the SPIDR after reset will always read a byte of zeros.
17.6
Interrupts
The SPI only originates interrupt requests when SPI is enabled (SPE bit in SPICR1 set). The following is a description of how the SPI makes a request and how the MCU should acknowledge that request. The interrupt vector offset and interrupt priority are chip dependent. The interrupt flags MODF, SPIF and SPTEF are logically ORed to generate an interrupt request.
17.6.1
MODF
MODF occurs when the master detects an error on the SS pin. The master SPI must be configured for the MODF feature (see Table 17-2). After MODF is set, the current transfer is aborted and the following bit is changed: * MSTR = 0, The master bit in SPICR1 resets. The MODF interrupt is reflected in the status register MODF flag. Clearing the flag will also clear the interrupt. This interrupt will stay active while the MODF flag is set. MODF has an automatic clearing process which is described in Section 17.3.1.4, "SPI Status Register (SPISR)."
17.6.2
SPIF
SPIF occurs when new data has been received and copied to the SPI Data Register. After SPIF is set, it does not clear until it is serviced. SPIF has an automatic clearing process which is described in Section 17.3.1.4, "SPI Status Register (SPISR)." In the event that the SPIF is not serviced before the end of the next transfer (i.e. SPIF remains active throughout another transfer), the latter transfers will be ignored and no new data will be copied into the SPIDR.
17.6.3
SPTEF
SPTEF occurs when the SPI Data Register is ready to accept new data. After SPTEF is set, it does not clear until it is serviced. SPTEF has an automatic clearing process which is described in Section 17.3.1.4, "SPI Status Register (SPISR)."
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 497
Chapter 17 Serial Peripheral Interface (SPIV3) Block Description
MC3S12RG128 Data Sheet, Rev. 1.05 498 Freescale Semiconductor
Chapter 18 Dual Output Voltage Regulator (VREG3V3V2) Block Description
18.1 Introduction
The VREG3V3 is a dual output voltage regulator providing two separate 2.5 V (typical) supplies differing in the amount of current that can be sourced. The regulator input voltage range is from 3.3 V up to 5 V (typical).
18.1.1
Features
The block VREG3V3 includes these distinctive features: * Two parallel, linear voltage regulators -- Bandgap reference * Low-voltage detect (LVD) with low-voltage interrupt (LVI) * Power-on reset (POR) * Low-voltage reset (LVR)
18.1.2
Modes of Operation
There are three modes VREG3V3 can operate in: * Full-performance mode (FPM) (MCU is not in stop mode) The regulator is active, providing the nominal supply voltage of 2.5 V with full current sourcing capability at both outputs. Features LVD (low-voltage detect), LVR (low-voltage reset), and POR (power-on reset) are available. * Reduced-power mode (RPM) (MCU is in stop mode) The purpose is to reduce power consumption of the device. The output voltage may degrade to a lower value than in full-performance mode, additionally the current sourcing capability is substantially reduced. Only the POR is available in this mode, LVD and LVR are disabled. * Shutdown mode Controlled by VREGEN (see device overview chapter for connectivity of VREGEN). This mode is characterized by minimum power consumption. The regulator outputs are in a high impedance state, only the POR feature is available, LVD and LVR are disabled. This mode must be used to disable the chip internal regulator VREG3V3, i.e., to bypass the VREG3V3 to use external supplies.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 499
Chapter 18 Dual Output Voltage Regulator (VREG3V3V2) Block Description
18.1.3
Block Diagram
Figure 18-1 shows the function principle of VREG3V3 by means of a block diagram. The regulator core REG consists of two parallel sub-blocks, REG1 and REG2, providing two independent output voltages.
REG2 REG VDDR VSSR VDDA
VDDPLL VSSPLL
REG1
VDD
LVD
LVR
LVR
POR
POR
VSSA
VSS
VREGEN
CTRL LVI
REG: Regulator Core LVD: Low Voltage Detect CTRL: Regulator Control LVR: Low Voltage Reset POR: Power-on Reset PIN
Figure 18-1. VREG3V3 Block Diagram
MC3S12RG128 Data Sheet, Rev. 1.05 500 Freescale Semiconductor
Chapter 18 Dual Output Voltage Regulator (VREG3V3V2) Block Description
18.2
External Signal Description
Due to the nature of VREG3V3 being a voltage regulator providing the chip internal power supply voltages most signals are power supply signals connected to pads. Table 18-1 shows all signals of VREG3V3 associated with pins.
Table 18-1. VREG3V3 -- Signal Properties
Name VDDR VSSR VDDA VSSA VDD VSS VDDPLL VSSPLL VREGEN (optional) Port -- -- -- -- -- -- -- -- -- Function VREG3V3 power input (positive supply) VREG3V3 power input (ground) VREG3V3 quiet input (positive supply) VREG3V3 quiet input (ground) VREG3V3 primary output (positive supply) VREG3V3 primary output (ground) VREG3V3 secondary output (positive supply) VREG3V3 secondary output (ground) VREG3V3 (Optional) Regulator Enable Reset State -- -- -- -- -- -- -- -- -- Pull Up -- -- -- -- -- -- -- -- --
NOTE Check device overview chapter for connectivity of the signals.
18.2.1
VDDR, VSSR -- Regulator Power Input
Signal VDDR is the power input of VREG3V3. All currents sourced into the regulator loads flow through this pin. A chip external decoupling capacitor (100 nF...220 nF, X7R ceramic) between VDDR and VSSR can smoothen ripple on VDDR. For entering shutdown mode, pin VDDR should also be tied to ground on devices without a VREGEN pin.
18.2.2
VDDA, VSSA -- Regulator Reference Supply
Signals VDDA/VSSA which are supposed to be relatively quiet are used to supply the analog parts of the regulator. Internal precision reference circuits are supplied from these signals. A chip external decoupling capacitor (100 nF...220 nF, X7R ceramic) between VDDA and VSSA can further improve the quality of this supply.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 501
Chapter 18 Dual Output Voltage Regulator (VREG3V3V2) Block Description
18.2.3
VDD, VSS -- Regulator Output1 (Core Logic)
Signals VDD/VSS are the primary outputs of VREG3V3 that provide the power supply for the core logic. These signals are connected to device pins to allow external decoupling capacitors (100 nF...220 nF, X7R ceramic). In shutdown mode an external supply at VDD/VSS can replace the voltage regulator.
18.2.4
VDDPLL, VSSPLL -- Regulator Output2 (PLL)
Signals VDDPLL/VSSPLL are the secondary outputs of VREG3V3 that provide the power supply for the PLL and oscillator. These signals are connected to device pins to allow external decoupling capacitors (100 nF...220 nF, X7R ceramic). In shutdown mode an external supply at VDDPLL/VSSPLL can replace the voltage regulator.
18.2.5
VREGEN -- Optional Regulator Enable
This optional signal is used to shutdown VREG3V3. In that case VDD/VSS and VDDPLL/VSSPLL must be provided externally. shutdown mode is entered with VREGEN being low. If VREGEN is high, the VREG3V3 is either in full-performance mode or in reduced-power mode. For the connectivity of VREGEN see device overview chapter. NOTE Switching from FPM or RPM to shutdown of VREG3V3 and vice versa is not supported while the MCU is powered.
MC3S12RG128 Data Sheet, Rev. 1.05 502 Freescale Semiconductor
Chapter 18 Dual Output Voltage Regulator (VREG3V3V2) Block Description
18.3
Memory Map and Register Definition
This subsection provides a detailed description of all registers accessible in VREG3V3.
18.3.1
Register Descriptions
The following paragraphs describe, in address order, all the VREG3V3 registers and their individual bits.
18.3.1.1
VREG3V3 -- Control Register (VREGCTRL)
The VREGCTRL register allows to separately enable features of VREG3V3.
Module Base + 0x000
7 6 5 4 3 2 1 0
R W Reset
0
0
0
0
0
LVDS LVIE LVIF 0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 18-2. VREG3V3 -- Control Register (VREGCTRL) Table 18-2. MCCTL1 Field Descriptions
Field 2 LVDS 1 LVIE 0 LVIF Description Low-Voltage Detect Status Bit -- This read-only status bit reflects the input voltage. Writes have no effect. 0 Input voltage VDDA is above level VLVID or RPM or shutdown mode. 1 Input voltage VDDA is below level VLVIA and FPM. Low-Voltage Interrupt Enable Bit 0 Interrupt request is disabled. 1 Interrupt will be requested whenever LVIF is set. Low-Voltage Interrupt Flag -- LVIF is set to 1 when LVDS status bit changes. This flag can only be cleared by writing a 1. Writing a 0 has no effect. If enabled (LVIE = 1), LVIF causes an interrupt request. 0 No change in LVDS bit. 1 LVDS bit has changed.
NOTE On entering the reduced-power mode the LVIF is not cleared by the VREG3V3.
18.4
Functional Description
Block VREG3V3 is a voltage regulator as depicted in Figure 18-1. The regulator functional elements are the regulator core (REG), a low-voltage detect module (LVD), a power-on reset module (POR) and a low-voltage reset module (LVR). There is also the regulator control block (CTRL) which represents the interface to the digital core logic but also manages the operating modes of VREG3V3.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 503
Chapter 18 Dual Output Voltage Regulator (VREG3V3V2) Block Description
18.4.1
REG -- Regulator Core
VREG3V3, respectively its regulator core has two parallel, independent regulation loops (REG1 and REG2) that differ only in the amount of current that can be sourced to the connected loads. Therefore, only REG1 providing the supply at VDD/VSS is explained. The principle is also valid for REG2. The regulator is a linear series regulator with a bandgap reference in its full-performance mode and a voltage clamp in reduced-power mode. All load currents flow from input VDDR to VSS or VSSPLL, the reference circuits are connected to VDDA and VSSA.
18.4.2
Full-Performance Mode
In full-performance mode, a fraction of the output voltage (VDD) and the bandgap reference voltage are fed to an operational amplifier. The amplified input voltage difference controls the gate of an output driver which basically is a large NMOS transistor connected to the output.
18.4.3
Reduced-Power Mode
In reduced-power mode, the driver gate is connected to a buffered fraction of the input voltage (VDDR). The operational amplifier and the bandgap are disabled to reduce power consumption.
18.4.4
LVD -- Low-Voltage Detect
sub-block LVD is responsible for generating the low-voltage interrupt (LVI). LVD monitors the input voltage (VDDA-VSSA) and continuously updates the status flag LVDS. Interrupt flag LVIF is set whenever status flag LVDS changes its value. The LVD is available in FPM and is inactive in reduced-power mode and shutdown mode.
18.4.5
POR -- Power-On Reset
This functional block monitors output VDD. If VDD is below VPORD, signal POR is high, if it exceeds VPORD, the signal goes low. The transition to low forces the CPU in the power-on sequence. Due to its role during chip power-up this module must be active in all operating modes of VREG3V3.
18.4.6
LVR -- Low-Voltage Reset
Block LVR monitors the primary output voltage VDD. If it drops below the assertion level (VLVRA) signal LVR asserts and when rising above the deassertion level (VLVRD) signal LVR negates again. The LVR function is available only in full-performance mode.
18.4.7
CTRL -- Regulator Control
This part contains the register block of VREG3V3 and further digital functionality needed to control the operating modes. CTRL also represents the interface to the digital core logic.
MC3S12RG128 Data Sheet, Rev. 1.05 504 Freescale Semiconductor
Chapter 18 Dual Output Voltage Regulator (VREG3V3V2) Block Description
18.5
Resets
This subsection describes how VREG3V3 controls the reset of the MCU.The reset values of registers and signals are provided in Section 18.3, "Memory Map and Register Definition". Possible reset sources are listed in Table 18-3.
Table 18-3. VREG3V3 -- Reset Sources
Reset Source Power-on reset Low-voltage reset Always active Available only in full-performance mode Local Enable
18.5.1
Power-On Reset
During chip power-up the digital core may not work if its supply voltage VDD is below the POR deassertion level (VPORD). Therefore, signal POR which forces the other blocks of the device into reset is kept high until VDD exceeds VPORD. Then POR becomes low and the reset generator of the device continues the start-up sequence. The power-on reset is active in all operation modes of VREG3V3.
18.5.2
Low-Voltage Reset
For details on low-voltage reset see Section 18.4.6, "LVR -- Low-Voltage Reset".
18.6
Interrupts
This subsection describes all interrupts originated by VREG3V3. The interrupt vectors requested by VREG3V3 are listed in Table 18-4. Vector addresses and interrupt priorities are defined at MCU level.
Table 18-4. VREG3V3 -- Interrupt Vectors
Interrupt Source Low Voltage Interrupt (LVI) Local Enable LVIE = 1; Available only in full-performance mode
18.6.1
LVI -- Low-Voltage Interrupt
In FPM VREG3V3 monitors the input voltage VDDA. Whenever VDDA drops below level VLVIA the status bit LVDS is set to 1. Vice versa, LVDS is reset to 0 when VDDA rises above level VLVID. An interrupt, indicated by flag LVIF = 1, is triggered by any change of the status bit LVDS if interrupt enable bit LVIE = 1. NOTE On entering the reduced-power mode, the LVIF is not cleared by the VREG3V3.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 505
Chapter 18 Dual Output Voltage Regulator (VREG3V3V2) Block Description
MC3S12RG128 Data Sheet, Rev. 1.05 506 Freescale Semiconductor
Appendix A Electrical Characteristics
A.1 General
NOTE The electrical characteristics given in this section are preliminary and should be used as a guide only. Values cannot be guaranteed by Freescale and are subject to change without notice. This supplement contains the most accurate electrical information for the MC3S12RG128 microcontroller available at the time of publication. The information should be considered PRELIMINARY and is subject to change. This introduction is intended to give an overview on several common topics like power supply, current injection etc.
A.1.1
Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate. NOTE This classification is shown in the column labeled "C" in the parameter tables where appropriate. P: C: T: Those parameters are guaranteed during production testing on each individual device. Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. Those parameters are derived mainly from simulations.
D:
A.1.2
Power Supply
The MC3S12RG128 utilizes several pins to supply power to the I/O ports, A/D converter, oscillator, PLL and internal logic. The VDDA, VSSA pair supplies the A/D converter and the internal voltage regulator.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 507
Appendix A Electrical Characteristics
The VDDX, VSSX, VDDR and VSSR pairs supply the I/O pins, VDDR also supplies the internal voltage regulator. VDD1, VSS1, VDD2 and VSS2 are the supply pins for the internal logic, VDDPLL, VSSPLL supply the oscillator and the PLL. VSS1 and VSS2 are internally connected by metal. VDDA, VDDX, VDDR as well as VSSA, VSSX, VSSR are connected by anti-parallel diodes for ESD protection. NOTE In the following context VDD35 is used for either VDDA, VDDR and VDDX; VSS35 is used for either VSSA, VSSR and VSSX unless otherwise noted. IDD35 denotes the sum of the currents flowing into the VDDA, VDDX and VDDR pins. VDD is used for VDD1, VDD2 and VDDPLL, VSS is used for VSS1, VSS2 and VSSPLL. IDD is used for the sum of the currents flowing into VDD1 and VDD2.
A.1.3
Pins
There are four groups of functional pins.
A.1.3.1
I/O pins
Those I/O pins have a nominal level in the range of 3.15V to 5.5V. This class of pins is comprised of all port I/O pins, the analog inputs, BKGD and the RESET pins.The internal structure of all those pins is identical, however some of the functionality may be disabled. E.g. for the analog inputs the output drivers, pull-up and pull-down resistors are disabled permanently.
A.1.3.2
Analog Reference
This group is made up by the VRH and VRL pins.
A.1.3.3
Oscillator
The pins XFC, EXTAL, XTAL dedicated to the oscillator have a nominal 2.5V level. They are supplied by VDDPLL.
A.1.3.4
TEST
This pin is used for production testing only. It must be tied to VSS.
A.1.3.5
VREGEN
This pin is used to enable the on chip voltage regulator.
MC3S12RG128 Data Sheet, Rev. 1.05 508 Freescale Semiconductor
Appendix A Electrical Characteristics
A.1.4
Current Injection
Power supply must maintain regulation within operating VDD35 or VDD range during instantaneous and operating maximum current conditions. If positive injection current (Vin > VDD35) is greater than IDD35, the injection current may flow out of VDD35 and could result in external power supply going out of regulation. Ensure external VDD35 load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power; e.g. if no system clock is present, or if clock rate is very low which would reduce overall power consumption.
A.1.5
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the device. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either VSS35 or VDD35).
Table A-1. Absolute Maximum Ratings1
Num 1 2 3 4 5 6 7 8 9 10 11 15
1 2
Rating I/O, Regulator and Analog Supply Voltage Internal Logic Supply Voltage PLL Supply Voltage 2 Voltage difference VDDX to VDDR and VDDA Voltage difference VSSX to VSSR and VSSA Digital I/O Input Voltage Analog Reference XFC, EXTAL, XTAL inputs TEST input (for test purposes only, tie to VSS) Instantaneous Maximum Current Single pin limit for all digital I/O pins 3 Instantaneous Maximum Current Single pin limit for XFC, EXTAL, XTAL4 Storage Temperature Range
2
Symbol VDD35 VDD VDDPLL VDDX VSSX VIN VRH, VRL VILV VTEST I
D
Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -25 -25 -65
Max 6.5 3.0 3.0 0.3 0.3 6.5 6.5 3.0 6.5 25 25 155
Unit V V V V V V V V V mA mA C
IDL T
stg
Beyond absolute maximum ratings device might be damaged. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. The absolute maximum ratings apply when the device is powered from an external source. 3 All digital I/O pins are internally clamped to V SSX and VDDX, VSSR and VDDR or VSSA and VDDA. 4 Those pins are internally clamped to VSSPLL and VDDPLL.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 509
Appendix A Electrical Characteristics
A.1.6
ESD Protection and Latch-up Immunity
All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for Automotive Grade Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body Model (HBM), the Machine Model (MM) and the Charge Device Model. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification.
Table A-2. ESD and Latch-up Test Conditions
Model Human Body Series Resistance Storage Capacitance Number of Pulse per pin positive negative Machine Series Resistance Storage Capacitance Number of Pulse per pin positive negative Latch-up Minimum input voltage limit Maximum input voltage limit Description Symbol R1 C - Value 1500 100 - 3 3 0 200 - 3 3 -2.5 7.5 V V Ohm pF Unit Ohm pF
R1 C -
Table A-3. ESD and Latch-Up Protection Characteristics
Num C 1 2 3 4 Rating Symbol VHBM VMM VCDM ILAT +100 -100 ILAT +200 -200 Min 2000 200 500 Max - - - - - mA Unit V V V mA
T Human Body Model (HBM) T Machine Model (MM) T Charge Device Model (CDM) T Latch-up Current at TA = 125C positive negative T Latch-up Current at TA = 27C positive negative
5
A.1.7
Operating Conditions
This chapter describes the operating conditions of the device. Unless otherwise noted those conditions apply to all the following data.
MC3S12RG128 Data Sheet, Rev. 1.05 510 Freescale Semiconductor
Appendix A Electrical Characteristics
NOTE Please refer to the temperature rating of the device (C, V, M) with regards to the ambient temperature TA and the junction temperature TJ. For power dissipation calculations refer to Section A.1.8, "Power Dissipation and Thermal Characteristics".
Table A-4. Operating Conditions
Rating I/O, Regulator and Analog Supply Voltage Internal Logic Supply Voltage 1 PLL Supply Voltage 1 Voltage Difference VDDX to VDDR and VDDA Voltage Difference VSSX to VSSR and VSSA Oscillator Bus Frequency MC3S12RG128C Operating Junction Temperature Range Operating Ambient Temperature Range 4 MC3S12RG128V Operating Junction Temperature Range Operating Ambient Temperature Range MC3S12RG128M Operating Junction Temperature Range Operating Ambient Temperature Range
1 4 4
Symbol VDD35 VDD VDDPLL VDDX VSSX fosc fbus
Min 2.97 2.35 2.35 -0.1 -0.1 0.5 0.252
Typ 5 2.5 2.5 0 0 - - - 27
Max 5.5 2.75 2.75 0.1 0.1 16 333
Unit V V V V V MHz MHz
TJ TA TJ TA TJ TA
-40 -40 -40 -40 -40 -40
100 85
C C C C C C
- 27
120 105
- 27
140 125
The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. This applies when this regulator is disabled and the device is powered from an external source. 2 Some blocks e.g. ATD (conversion) require higher bus frequencies for proper operation. 3 single-chip modes only; for expanded modes the max. bus frequency is 25 MHz 4 Please refer to Section A.1.8, "Power Dissipation and Thermal Characteristics" for more details about the relation between ambient temperature TA and device junction temperature TJ.
A.1.8
Power Dissipation and Thermal Characteristics
Power dissipation and thermal characteristics are closely related. The user must assure that the maximum operating junction temperature is not exceeded. The average chip-junction temperature (TJ) in C can be obtained from:
T T T J A = Junction Temperature, [C ] = Ambient Temperature, [C ]
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 511
J
= T + (P * ) A D JA
Appendix A Electrical Characteristics
P
D
= Total Chip Power Dissipation, [W] = Package Thermal Resistance, [C/W]
JA
The total power dissipation can be calculated from:
P P INT = Chip Internal Power Dissipation, [W] D =P INT +P IO
Two cases with internal voltage regulator enabled and disabled must be considered: 1. Internal voltage regulator disabled
P INT =I DD V DD IO +I = DDPLL V DDPLL +I DDA V DDA
P
RDSON IIOi2 i
PIO is the sum of all output currents on I/O ports associated with VDDX and VDDR. For RDSON is valid:
R V OL = ----------- ;for outputs driven low DSON I OL
respectively
R V -V DD5 OH = ----------------------------------- ;for outputs driven high DSON I OH
2. Internal voltage regulator enabled
P INT =I DDR V DDR +I DDA V DDA
IDDR is the current shown in Table A-8 and not the overall current flowing into VDDR, which additionally contains the current flowing into the external loads with output high.
P IO =
RDSON IIOi2 i
PIO is the sum of all output currents on I/O ports associated with VDDX and VDDR.
MC3S12RG128 Data Sheet, Rev. 1.05 512 Freescale Semiconductor
Appendix A Electrical Characteristics
Table A-5. Thermal Package Characteristics1
Num C 1 2 3 4 5 6 7 8 9 10
1 2
Rating
Symbol JA JA JB JC JT JA JA JB JC JT
Min - - - - - - - - - -
Typ - - - - - - - - - -
Max 54 41 31 11 2 51 41 27 14 3
Unit
o o
T Thermal Resistance LQFP112, single sided PCB2 T Thermal Resistance LQFP112, double sided PCB with 2 internal planes3 T Junction to Board LQFP112 T Junction to Case LQFP112 T Junction to Package Top LQFP112 T Thermal Resistance QFP 80, single sided PCB T Thermal Resistance QFP 80, double sided PCB with 2 internal planes T Junction to Board QFP80 T Junction to Case QFP80 T Junction to Package Top QFP80
C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W
o o o o o
o o o
The values for thermal resistance are achieved by package simulations PC Board according to EIA/JEDEC Standard 51-3 3 PC Board according to EIA/JEDEC Standard 51-7
A.1.9
I/O Characteristics
This section describes the characteristics of all I/O pins except EXTAL, XTAL, XFC, TEST and supply pins. All parameters are not always applicable, e.g. not all pins feature pull up/down resistances.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 513
Appendix A Electrical Characteristics
Table A-6. 3.3V I/O Characteristics
Conditions are VDDX=3.3V +/-10% Temperature from -40C to 140C, unless otherwise noted. I/O Characteristics for all I/O pins except EXTAL, XTAL,XFC,TEST and supply pins. Num C 1 P Input High Voltage T Input High Voltage 2 P Input Low Voltage T Input Low Voltage 3 4 C Input Hysteresis C Input Leakage Current (pins in high impedance input mode)1 Vin = VDD35 or VSS35 C Output High Voltage (pins in output mode) Partial Drive IOH = -0.75mA P Output High Voltage (pins in output mode) Full Drive IOH = -4.0mA C Output Low Voltage (pins in output mode) Partial Drive IOL = +0.9mA P Output Low Voltage (pins in output mode) Full Drive IOL = +4.75mA P Internal Pull Up Device Current, tested at V max IL C Internal Pull Up Device Current,tested at VIH min P Internal Pull Down Device Current, tested at VIH min C Internal Pull Down Device Current, tested at VIL max D Input Capacitance T Injection current Single Pin limit Total Device Limit. Sum of all injected currents P Port H, J, P Interrupt Input Pulse filtered3 P Port H, J, P Interrupt Input Pulse passed
3 2
Rating
Symbol V
IH
Min 0.65*VDD35 - - VSS35 - 0.3 - -1
Typ - - - - 250 -
Max - VDD35 + 0.3 0.35*VDD35 - - 1
Unit V V V V mV A
VIH VIL VIL VHYS I
in
5 6 7 8 9 10 11 12 13 14
V
OH
VDD35 - 0.4 VDD35 - 0.4 - - - -6 - 6 - -2.5 -25 - 10
- - - - - - - - 6 -
- - 0.4 0.4 -60 - 60 - - 2.5 25
V V V V A A A A pF mA
V
OH
VOL V
OL
IPUL IPUH IPDH IPDL Cin IICS IICP tPULSE tPULSE
15 16
1
- -
3 -
s s
Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for each 8C to 12C in the temperature range from 50C to 125C. 2 Refer to Section A.1.4, "Current Injection", for more details 3 Parameter only applies in STOP or Pseudo STOP mode.
MC3S12RG128 Data Sheet, Rev. 1.05 514 Freescale Semiconductor
Appendix A Electrical Characteristics
Table A-7. 5V I/O Characteristics
Conditions are 4.5< VDD35 <5.5V Temperature from -40C to 140C, unless otherwise noted I/O Characteristics for all I/O pins except EXTAL, XTAL, XFC, TEST and supply pins. Num C 1 P Input High Voltage T Input High Voltage 2 P Input Low Voltage T Input Low Voltage 3 4 C Input Hysteresis P Input Leakage Current (pins in high impedance input mode)1 measured at Vin = 5.5V and Vin = 0V C Output High Voltage (pins in output mode) Partial Drive IOH = -2mA P Output High Voltage (pins in output mode) Full Drive IOH = -10mA C Output Low Voltage (pins in output mode) Partial Drive IOL = +2mA P Output Low Voltage (pins in output mode) Full Drive IOL = +10mA P Internal Pull Up Device Current, tested at V max IL C Internal Pull Up Device Current, tested at VIH min P Internal Pull Down Device Current, tested at VIH min C Internal Pull Down Device Current, tested at VIL max D Input Capacitance T Injection current Single Pin limit Total Device Limit. Sum of all injected currents P Port H, J, P Interrupt Input Pulse filtered3 P Port H, J, P Interrupt Input Pulse passed
3 2
Rating
Symbol V
IH
Min 0.65*VDD35 - - VSS35 - 0.3 - -1
Typ - - - - 250 -
Max - VDD35 + 0.3 0.35*VDD35 - - 1
Unit V V V V mV A
VIH VIL VIL VHYS I
in
5 6 7 8 9 10 11 12 13 14
V
OH
VDD35 - 0.8 VDD35 - 0.8 - - - -10 - 10 - -2.5 -25 - 10
- - - - - - - - 6 -
- - 0.8 0.8 -130 - 130 - - 2.5 25
V V V V A A A A pF mA
V
OH
VOL V
OL
IPUL IPUH IPDH IPDL Cin IICS IICP tPULSE tPULSE
15 16
1
- -
3 -
s s
Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for each 8C to 12C in the temperature range from 50C to 125C. 2 Refer to Section A.1.4, "Current Injection", for more details 3 Parameter only applies in STOP or Pseudo STOP mode.
A.1.10
Supply Currents
This section describes the current consumption characteristics of the device as well as the conditions for the measurements.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 515
Appendix A Electrical Characteristics
A.1.10.1
Measurement Conditions
All measurements are without output loads. Unless otherwise noted the currents are measured in single chip mode, internal voltage regulator enabled and at 33MHz bus frequency using a 4MHz oscillator in Colpitts mode. Production testing is performed using a square wave signal at the EXTAL input.
A.1.10.2
Additional Remarks
In expanded modes the currents flowing in the system are highly dependent on the load at the address, data and control signals as well as on the duty cycle of those signals. No generally applicable numbers can be given. A very good estimate is to take the single chip currents and add the currents due to the external loads.
Table A-8. Supply Current Characteristics at 33 MHz Bus Frequency
Conditions are shown in Table A-4 unless otherwise noted Num C 1 P 2 P P 3 C P C C P C P C P 4 C C C C C C C 5 C P C C P C P C P
1
Rating Run supply currents (33 MHz) Single Chip, Internal regulator enabled Wait Supply current All modules enabled, PLL on (33 MHz) only RTI enabled 1 Pseudo Stop Current (RTI and COP disabled) 1, 2 -40C 25C 70C 85C "C" Temp Option 100C 105C "V" Temp Option 120C 125C "M" Temp Option 140C Pseudo Stop Current (RTI and COP enabled)
1, 2
Symbol IDD35
Min
Typ
Max 70
Unit mA mA
IDDW 35 7 IDDPS 90 100 250 300 350 400 650 750 1000 IDDPS 120 140 275 325 450 800 1200 IDDS 140
A
1200 2200 4000 A
-40C 25C 70C 85C 105C 125C 140C Stop Current 2 -40C 25C 70C 85C "C" Temp Option 100C 105C "V" Temp Option 120C 125C "M" Temp Option 140C
A 20 35 150 250 300 350 600 700 900 100
1000 2000 3800
PLL off
MC3S12RG128 Data Sheet, Rev. 1.05 516 Freescale Semiconductor
Appendix A Electrical Characteristics
2
At those low power dissipation levels TJ = TA can be assumed
A.2
ATD Characteristics
This section describes the characteristics of the analog to digital converter. The ATD is specified and tested for both the 3.3V and 5V range. For ranges between 3.3V and 5V the ATD accuracy is generally the same as in the 3.3V range but is not tested in this range in production test.
A.2.1
ATD Operating Characteristics In 5V Range
The Table A-9 shows conditions under which the ATD operates. The following constraints exist to obtain full-scale, full range results: VSSA VRL VIN VRH VDDA. This constraint exists since the sample buffer amplifier can not drive beyond the power supply levels that it ties to. If the input level goes outside of this range it will effectively be clipped.
Table A-9. ATD Operating Characteristics
Conditions are shown in Table A-4 unless otherwise noted. Supply Voltage 5V-10% <= VDDA <=5V+10% Num 1 C D Reference Potential Low High 2 3 4 C D D Differential Reference Voltage1 ATD Clock Frequency ATD 10-Bit Conversion Period Clock Cycles2 Conv, Time at 2.0MHz ATD Clock fATDCLK 5 D ATD 8-Bit Conversion Period Clock Cycles Conv, Time at 2.0MHz ATD Clock fATDCLK 6 7
1 2
Rating
Symbol VRL VRH VRH-VRL fATDCLK NCONV10 TCONV10 NCONV10 TCONV10 tREC IREF
Min VSSA VDDA/2 4.50 0.5 14 7 12 6
Typ
Max VDDA/2 VDDA
Unit V V V MHz Cycles s Cycles s s mA
5.00
5.50 2.0 28 14 26 13 20 0.3753
D P
Recovery Time (VDDA=5.0 Volts) Reference Supply current
Full accuracy is not guaranteed when differential voltage is less than 4.75V The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample period of 16 ATD clocks. 3 This applies per ATD module, i.e. for 2 ATD modules this number is doubled.
A.2.2
ATD Operating Characteristics In 3.3V Range
The Table A-10 shows conditions under which the ATD operates. The following constraints exist to obtain full-scale, full range results: VSSA VRL VIN VRH VDDA. This constraint exists since the sample buffer amplifier can not drive beyond the power supply levels that it ties to. If the input level goes outside of this range it will effectively be clipped
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 517
Appendix A Electrical Characteristics
Table A-10. ATD Operating Characteristics
Conditions are shown in Table A-4 unless otherwise noted; Supply Voltage 3.3V-10% <= VDDA <= 3.3V+10% Num C 1 D Reference Potential Low High 2 3 4 C Differential Reference Voltage D ATD Clock Frequency D ATD 10-Bit Conversion Period Clock Cycles1 Conv, Time at 2.0MHz ATD Clock fATDCLK 5 D ATD 8-Bit Conversion Period Clock Cycles1 Conv, Time at 2.0MHz ATD Clock fATDCLK 6 7
1
Rating
Symbol VRL VRH VRH-VRL fATDCLK NCONV10 TCONV10 NCONV8 TCONV8 tREC IREF
Min VSSA VDDA/2 3.0 0.5 14 7 12 6
Typ
Max VDDA/2 VDDA
Unit V V V MHz Cycles s Cycles s s
2
3.3
3.6 2.0 28 14 26 13 20 0.250
D Recovery Time (VDDA=3.3 Volts) P Reference Supply current
mA
The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample period of 16 ATD clocks. 2 This applies per ATD module, i.e. for 2 ATD modules this number is doubled.
A.2.3
Factors influencing accuracy
Three factors - source resistance, source capacitance and current injection - have an influence on the accuracy of the ATD.
A.2.3.1
Source Resistance:
Due to the input pin leakage current as specified in Table A-7 in conjunction with the source resistance there will be a voltage drop from the signal source to the ATD input. The maximum source resistance RS specifies results in an error of less than 1/2 LSB (2.5mV) at the maximum leakage current. If device or operating conditions are less than worst case or leakage-induced error is acceptable, larger values of source resistance is allowable.
A.2.3.2
Source capacitance
When sampling an additional internal capacitor is switched to the input. This can cause a voltage drop due to charge sharing with the external and the pin capacitance. For a maximum sampling error of the input voltage 1LSB, then the external filter capacitor, Cf 1024 * (CINS- CINN).
MC3S12RG128 Data Sheet, Rev. 1.05 518 Freescale Semiconductor
Appendix A Electrical Characteristics
A.2.3.3
Current injection
There are two cases to consider. 1. A current is injected into the channel being converted. The channel being stressed has conversion values of $3FF ($FF in 8-bit mode) for analog inputs greater than VRH and $000 for values less than VRL unless the current is higher than specified as disruptive conditions. 2. Current is injected into pins in the neighborhood of the channel being converted. A portion of this current is picked up by the channel (coupling ratio K), This additional current impacts the accuracy of the conversion depending on the source resistance. The additional input voltage error on the converted channel can be calculated as VERR = K * RS * IINJ, with IINJ being the sum of the currents injected into the two pins adjacent to the converted channel.
Table A-11. ATD Electrical Characteristics
Conditions are shown in Table A-4 unless otherwise noted Num 1 2 C C T Rating Max input Source Resistance Total Input Capacitance Non Sampling Sampling Disruptive Analog Input Current Coupling Ratio positive current injection Coupling Ratio negative current injection Symbol RS CINN CINS INA Kp Kn -2.5 Min - Typ - Max 1 10 22 2.5 10-4 10-2 mA A/A A/A Unit K pF
3 4 5
C C C
A.2.4
ATD accuracy (5V Range)
Table A-12 specifies the ATD conversion performance excluding any errors due to current injection, input capacitance and source resistance.
Table A-12. 5V ATD Conversion Performance
Conditions are shown in Table A-4 unless otherwise noted VREF = VRH - VRL = 5.12V. Resulting to one 8 bit count = 20mV and one 10 bit count = 5mV fATDCLK = 2.0MHz Num 1 2 3 4 5 6 7 8 C P P P P P P P P 10-Bit Resolution 10-Bit Differential Nonlinearity 10-Bit Integral Nonlinearity 10-Bit Absolute Error 8-Bit Resolution 8-Bit Differential Nonlinearity 8-Bit Integral Nonlinearity 8-Bit Absolute Error
1 1
Rating
Symbol LSB DNL INL AE LSB DNL INL AE
Min - -1 -2.5 -3 - -0.5 -1.0 -1.5
Typ 5 - 1.5 2 20 - 0.5 1.0
Max - +1 +2.5 3 - 0.5 1.0 1.5
Unit mV Counts Counts Counts mV Counts Counts Counts
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 519
Appendix A Electrical Characteristics
1
These values include quantization error which is inherently 1/2 count for any A/D converter.
A.2.5
ATD accuracy (3.3V Range)
Table A-13 specifies the ATD conversion performance excluding any errors due to current injection, input capacitance and source resistance.
Table A-13. 3.3V ATD Conversion Performance
Conditions are shown in Table A-4 unless otherwise noted VREF = VRH - VRL = 3.328V. Resulting to one 8 bit count = 13mV and one 10 bit count = 3.25mV fATDCLK = 2.0MHz Num 1 2 3 4 5 6 7 8
1
C P P P P P P P P 10-Bit Resolution
Rating
Symbol LSB DNL INL AE LSB DNL INL AE
Min - -1.5 -3.5 -5 - -0.5 -1.5 -2.0
Typ 3.25 - 1.5 2.5 13 - 1.0 1.5
Max - +1.5 +3.5 +5 - 0.5 1.5 2.0
Unit mV Counts Counts Counts mV Counts Counts Counts
10-Bit Differential Nonlinearity 10-Bit Integral Nonlinearity 10-Bit Absolute Error 8-Bit Resolution 8-Bit Differential Nonlinearity 8-Bit Integral Nonlinearity 8-Bit Absolute Error
1 1
These values include the quantization error which is inherently 1/2 count for any A/D converter.
For the following definitions see also Figure A-1. Differential Non-Linearity (DNL) is defined as the difference between two adjacent switching steps.
Vi - Vi - 1 DNL ( i ) = ------------------------ - 1 1LSB
The Integral Non-Linearity (INL) is defined as the sum of all DNLs: n
INL ( n ) =
i=1
Vn - V0 DNL ( i ) = ------------------- - n 1LSB
MC3S12RG128 Data Sheet, Rev. 1.05 520 Freescale Semiconductor
Appendix A Electrical Characteristics
DNL
LSB Vi-1
$3FF $3FE $3FD $3FC $3FB $3FA $3F9 $3F8 $3F7 $3F6 $3F5
10-Bit Absolute Error Boundary Vi 8-Bit Absolute Error Boundary
$FF
$FE
10-Bit Resolution
$3F4 $3F3
$FD
9 8 7 6 5 4 3 2 1 0 5 3.25 10 6.5 15 9.75 20 25 30 35 40 45 13 16.25 19.5 22.75 26 29.25
Ideal Transfer Curve
2
10-Bit Transfer Curve
1
8-Bit Transfer Curve
5V 3.3V Range
5055 5060 5065 5070 5075 5080 5085 5090 5095 5100 5105 5110 5115 5120 3286 3289 3292 3295 3299 3302 3305 3309 3312 3315 3318 3321 3324 3328
Vin mV
Figure A-1. ATD Accuracy Definitions
NOTE Figure A-1 shows only definitions, for specification values refer to Table A-12 and Table A-13.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 521
8-Bit Resolution
Appendix A Electrical Characteristics
A.3
Nu m 1 2 3 4
Voltage Regulator Operating Conditions
Table A-14. Voltage Regulator Electrical Parameters
C P P P P Characteristic Input Voltages Output Voltage Core Full Performance Mode Output Voltage PLL Full Performance Mode Low Voltage Interrupt1 Assert Level Deassert Level Low Voltage Reset2 Assert Level Power-on Reset3 Assert Level Deassert Level Symbol VVDDR, A VDD 2.35 VDDPLL 2.35 VLVIA VLVID VLVRA VPORA VPORD 4.00 4.15 2.25 0.97 -- 2.54 4.37 4.52 2.35 -- -- 2.75 4.66 4.77 -- -- 2.05 V V V V V V 2.54 2.75 V Min 2.97 Typical -- Max 5.5 Unit V
5 6
P C
1
Monitors VDDA, active only in Full Performance Mode. Indicates I/O & ADC performance degradation due to low supply voltage. 2 Monitors V , active only in Full Performance Mode. MCU is monitored by the POR in Reduced Power Mode DD 3 Monitors V . Active in all modes. DD
NOTE The electrical characteristics given in this section are preliminary and should be used as a guide only. Values in this section cannot be guaranteed by Freescale and are subject to change without notice.
A.4
Chip Power-up and LVI/LVR graphical explanation
Voltage regulator sub modules LVI (low voltage interrupt), POR (power-on reset) and LVR (low voltage reset) handle chip power-up or drops of the supply voltage. Their function is described in the VREG3V3 block guide.
MC3S12RG128 Data Sheet, Rev. 1.05 522 Freescale Semiconductor
Appendix A Electrical Characteristics
V
VLVID VLVIA
VDDA
VDD
VLVRD VLVRA VPORD
t
LVI
LVI enabled
POR
LVI disabled due to LVR
LVR
Figure A-2. Voltage Regulator - Chip Power-up and Voltage Drops (not scaled)
A.5
A.5.1
Output Loads
Resistive Loads
The on-chip voltage regulator is intended to supply the internal logic and oscillator circuits allows no external DC loads.
A.5.2
Capacitive Loads
The capacitive loads are specified in Table A-15. Ceramic capacitors with X7R dielectricum are required.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 523
Appendix A Electrical Characteristics
Table A-15. Voltage Regulator - Capacitive Loads
Num 1 2 Characteristic VDD external capacitive load VDDPLL external capacitive load Symbol CDDext CDDPLLext Min 400 90 Typical 440 220 Max 12000 5000 Unit nF nF
A.6
Reset, Oscillator and PLL
This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and Phase-Locked-Loop (PLL).
A.6.1
Startup
Table A-16 summarizes several startup characteristics explained in this section. Detailed description of the startup behavior can be found in the Clock and Reset Generator (CRG) Block User Guide.
Table A-16. Startup Characteristics
Conditions are shown in Table A-4 unless otherwise noted Num C 1 2 3 4 Rating Symbol PWRSTL nRST PWIRQ tWRS Min 2 192 20 14 196 Typ Max Unit tosc nosc ns tcyc
D Reset input pulse width, minimum input time D Startup from Reset D Interrupt pulse width, IRQ edge-sensitive mode D Wait recovery startup time
A.6.1.1
POR
Both the deassert level VPORD and the assert level VPORA (Table A-14) are derived from the VDD supply. They are also valid if the device is powered externally. After releasing the POR reset the oscillator and the clock quality check are started. If after a time tCQOUT no valid oscillation is detected, the MCU will start using the internal self clock. The fastest startup time possible is given by nuposc.
A.6.1.2
SRAM Data Retention
Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing code if VDD35 is out of specification limits, the SRAM contents integrity is guaranteed if after the reset the PORF bit in the CRG Flags Register has not been set.
A.6.1.3
External Reset
When external reset is asserted for a time greater than PWRSTL the CRG module generates an internal reset, and the CPU starts fetching the reset vector without doing a clock quality check, if there was an oscillation before reset.
MC3S12RG128 Data Sheet, Rev. 1.05 524 Freescale Semiconductor
Appendix A Electrical Characteristics
A.6.1.4
Stop Recovery
Out of STOP the controller can be woken up by an external interrupt. A clock quality check as after POR is performed before releasing the clocks to the system.
A.6.1.5
Pseudo Stop and Wait Recovery
The recovery from Pseudo STOP and Wait are essentially the same since the oscillator was not stopped in both modes. The controller can be woken up by internal or external interrupts. After twrs the CPU starts fetching the interrupt vector.
A.6.2
Oscillator
The device features an internal Colpitts and Pierce oscillator. The selection of Colpitts oscillator or Pierce oscillator/external clock depends on the XCLKS signal which is sampled during reset.By asserting the XCLKS input during reset this oscillator can be bypassed allowing the input of a square wave. Before asserting the oscillator to the internal system clocks the quality of the oscillation is checked for each start from either power-on, STOP or oscillator fail. tCQOUT specifies the maximum time before switching to the internal self clock mode after POR or STOP if a proper oscillation is not detected. The quality check also determines the minimum oscillator start-up time tUPOSC. The device also features a clock monitor. A Clock Monitor Failure is asserted if the frequency of the incoming clock signal is below the Assert Frequency fCMFA.
Table A-17. Oscillator Characteristics
Conditions are shown in Table A-4 unless otherwise noted Num C 1a 1b 2 3 4 5 6 7 8 9 10 11 12
1
Rating
Symbol fOSC fOSC iOSC tUPOSC tCQOUT fCMFA fEXT tEXTL tEXTH tEXTR tEXTF CIN VDCBIAS
Min 0.5 0.5 100
Typ
Max 16 40
Unit MHz MHz A
C Crystal oscillator range (Colpitts) C Crystal oscillator range (Pierce) 1 P Startup Current C Oscillator start-up time (Colpitts) D Clock Quality check time-out P Clock Monitor Failure Assert Frequency P External square wave input frequency 4 D External square wave pulse width low D External square wave pulse width high D External square wave rise time D External square wave fall time D Input Capacitance (EXTAL, XTAL pins) C DC Operating Bias in Colpitts Configuration on EXTAL Pin
82 0.45 50 0.5 7.2 7.2 100
1003 2.5 200 66
ms s KHz MHz ns ns
1 1 7 1.1
ns ns pF V
Depending on the crystal a damping series resistor might be necessary fosc = 4MHz, C = 22pF. 3 Maximum value is for extreme cases using high Q, low frequency crystals
2
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 525
Appendix A Electrical Characteristics
4
XCLKS =0 during reset
A.6.3
Phase Locked Loop
The oscillator provides the reference clock for the PLL. The PLLs Voltage Controlled Oscillator (VCO) is also the system clock source in self clock mode.
A.6.3.1
XFC Component Selection
This section describes the selection of the XFC components to achieve good filter characteristics. Cp VDDPLL Cs fosc 1 refdv+1 fref fcmp R Phase K Detector Loop Divider 1 synr+1
Figure A-3. Basic PLL functional diagram
XFC Pin
VCO KV fvco
1 2
The following procedure can be used to calculate the resistance and capacitance values using typical values for K1, f1 and ich from Table A-18. The grey boxes show the calculation for fVCO = 50MHz and fref = 1MHz. E.g., these frequencies are used for fOSC = 4MHz and a 25MHz bus clock. The VCO Gain at the desired VCO frequency is approximated by: ( f 1 - f vco ) ---------------------K 1 1V ( 60 - 50 ) --------------------- 100
KV = K1 e
= - 100 e
= -90.48MHz/V
The phase detector relationship is given by:
K = - i ch K V
ich is the current in tracking mode.
= 316.7Hz/
MC3S12RG128 Data Sheet, Rev. 1.05 526 Freescale Semiconductor
Appendix A Electrical Characteristics
The loop bandwidth fC should be chosen to fulfill the Gardner's stability criteria by at least a factor of 10, typical values are 50. = 0.9 ensures a good transient response.
2 f ref f ref 1 f C < ------------------------------------------ ---- f C < ------------ ;( = 0.9 ) 4 10 10 2 + 1 + fC < 25kHz
And finally the frequency relationship is defined as
f VCO n = ------------ = 2 ( synr + 1 ) f ref
= 50
With the above values the resistance can be calculated. The example is shown for a loop bandwidth fC=10KHz:
2 n fC R = ---------------------------- = 2**50*10kHz/(316.7Hz/)=9.9k =~ 10k K
The capacitance Cs can now be calculated as:
0.516 2 C s = --------------------- -------------- ;( = 0.9 ) = 5.19nF =~ 4.7nF fC R fC R
The capacitance Cp should be chosen in the range of:
2
C s 20 C p C s 10
Cp = 470pF
A.6.3.2
Jitter Information
The basic functionality of the PLL is shown in Figure A-3. With each transition of the clock fcmp, the deviation from the reference clock fref is measured and input voltage to the VCO is adjusted accordingly.The adjustment is done continuously with no abrupt changes in the clock output frequency. Noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock jitter. This jitter affects the real minimum and maximum clock periods as illustrated in Figure A-4.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 527
Appendix A Electrical Characteristics
0
1
2
3
N-1
N
tmin1 tnom tmax1 tminN tmaxN
Figure A-4. Jitter Definitions
The relative deviation of tnom is at its maximum for one clock period, and decreases towards zero for larger number of clock periods (N). Defining the jitter as:
t min ( N ) t max ( N ) J ( N ) = max 1 - -------------------- , 1 - -------------------- N t nom N t nom
For N < 100, the following equation is a good fit for the maximum jitter:
j1 J ( N ) = ------- + j 2 N
J(N)
1
5
10
20
N
Figure A-5. Maximum bus clock jitter approximation
This is very important to notice with respect to timers, serial modules where a pre-scaler will eliminate the effect of the jitter to a large extent.
MC3S12RG128 Data Sheet, Rev. 1.05 528 Freescale Semiconductor
Appendix A Electrical Characteristics
Table A-18. PLL Characteristics
Conditions are shown in Table A-4 unless otherwise noted Num C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
1 2
Rating
Symbol fSCM fVCO |trk| |Lock| |unl| |unt| tstab tacq tal K1 f1 | ich | | ich | j1 j1 j2
Min 1 8 3 0 0.5 6
Typ
Max 5.5 66 4 1.5 2.5 8
Unit MHz MHz %1 %1 %1 %1 ms ms ms MHz/V MHz A A
P Self Clock Mode frequency D VCO locking range D Lock Detector transition from Acquisition to Tracking mode D Lock Detection D Un-Lock Detection D Lock Detector transition from Tracking to Acquisition mode C PLLON Total Stabilization delay (Auto Mode) 2 D PLLON Acquisition mode stabilization delay 2 D PLLON Tracking mode stabilization delay 2 D Fitting parameter VCO loop gain D Fitting parameter VCO loop frequency D Charge pump current acquisition mode D Charge pump current tracking mode C Jitter fit parameter 1 (fBUS = 25MHz) C Jitter fit parameter 1 (fBUS = 33MHz) C Jitter fit parameter 22 (fBUS = 25MHz)
3 2
0.5 0.3 0.2 -100 60 38.5 3.5 1.1 1.5 0.13
% % %
% deviation from target frequency fOSC = 4MHz, fBUS = 25MHz equivalent fVCO = 50MHz: REFDV = 0x03, SYNR = 0x18, Cs = 4.7nF, Cp = 470pF, Rs = 10k. 3f OSC = 4MHz, fBUS = 33MHz equivalent fVCO = 66MHz: REFDV = 0x03, SYNR = 0x20, Cs = 22nF, Cp = 2.2nF, Rs = 4.7k
A.7
MSCAN
Table A-19. MSCAN Wake-up Pulse Characteristics
Conditions are shown in Table A-4 unless otherwise noted Num C 1 2 Rating Symbol tWUP tWUP 5 Min Typ Max 1 Unit s s
P MSCAN Wake-up dominant pulse filtered P MSCAN Wake-up dominant pulse pass
A.8
SPI
This section provides electrical parametrics and ratings for the SPI. In Table A-20 the measurement conditions are listed.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 529
Appendix A Electrical Characteristics
Table A-20. Measurement Conditions
Description Drive mode Load capacitance CLOAD, on all outputs Thresholds for delay measurement points Value full drive mode 50 (20% / 80%) VDDX Unit -- pF V
A.8.1
Master Mode
In Figure A-6 the timing diagram for master mode with transmission format CPHA=0 is depicted.
SS1 (OUTPUT) 2 SCK (CPOL = 0) (OUTPUT) SCK (CPOL = 1) (OUTPUT) 5 MISO (INPUT) 10 MOSI (OUTPUT)
1.if configured as an output. 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
1 4 4
12
13
3
12
13
6 MSB IN2 BIT 6 . . . 1 9 MSB OUT2 BIT 6 . . . 1 LSB OUT LSB IN 11
Figure A-6. SPI Master Timing (CPHA=0)
In Figure A-7 the timing diagram for master mode with transmission format CPHA=1 is depicted.
MC3S12RG128 Data Sheet, Rev. 1.05 530 Freescale Semiconductor
Appendix A Electrical Characteristics
SS1 (OUTPUT) 1 2 SCK (CPOL = 0) (OUTPUT) 4 SCK (CPOL = 1) (OUTPUT) 5 MISO (INPUT) 9 MOSI (OUTPUT) PORT DATA
1.If configured as output 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
12
13
3
4
12
13
6 MSB IN2 BIT 6 . . . 1 11 LSB IN
MASTER MSB OUT2
BIT 6 . . . 1
MASTER LSB OUT
PORT DATA
Figure A-7. SPI Master Timing (CPHA=1)
In Table A-21 the timing characteristics for master mode are listed.
Table A-21. SPI Master Mode Timing Characteristics
Num 1 1 2 3 4 5 6 9 10 11 12 13 Characteristic SCK Frequency SCK Period Enable Lead Time Enable Lag Time Clock (SCK) High or Low Time Data Setup Time (Inputs) Data Hold Time (Inputs) Data Valid after SCK Edge Data Valid after SS fall (CPHA=0) Data Hold Time (Outputs) Rise and Fall Time Inputs Rise and Fall Time Outputs Symbol Min fsck tsck tlead tlag twsck tsu thi tvsck tvss tho trfi trfo 1/2048 2 -- -- -- 8 8 -- -- 20 -- -- Typ -- -- 1/2 1/2 1/2 -- -- -- -- -- -- -- Max 1/2 2048 -- -- -- -- -- 30 15 -- 8 8 fbus tbus tsck tsck tsck ns ns ns ns ns ns ns Unit
A.8.2
Slave Mode
In Figure A-8 the timing diagram for slave mode with transmission format CPHA=0 is depicted.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 531
Appendix A Electrical Characteristics
SS (INPUT) 1 SCK (CPOL = 0) (INPUT) 2 SCK (CPOL = 1) (INPUT) 10 7 MISO (OUTPUT) see note 5 MOSI (INPUT) NOTE: Not defined! MSB IN SLAVE MSB 6 BIT 6 . . . 1 LSB IN 9 BIT 6 . . . 1 4 4 12 13 8 11 11 SEE NOTE 12 13 3
SLAVE LSB OUT
Figure A-8. SPI Slave Timing (CPHA=0)
In Figure A-9 the timing diagram for slave mode with transmission format CPHA=1 is depicted.
SS (INPUT) 1 2 SCK (CPOL = 0) (INPUT) 4 SCK (CPOL = 1) (INPUT) 9 MISO (OUTPUT) see note 7 MOSI (INPUT) NOTE: Not defined! SLAVE 5 MSB IN MSB OUT 6 BIT 6 . . . 1 LSB IN 4 12 13 12 13 3
11 BIT 6 . . . 1 SLAVE LSB OUT
8
Figure A-9. SPI Slave Timing (CPHA=1)
In Table A-22 the timing characteristics for slave mode are listed.
MC3S12RG128 Data Sheet, Rev. 1.05 532 Freescale Semiconductor
Appendix A Electrical Characteristics
Table A-22. SPI Slave Mode Timing Characteristics
Num 1 1 2 3 4 5 6 7 8 9 10 11 12 13
1
Characteristic SCK Frequency SCK Period Enable Lead Time Enable Lag Time Clock (SCK) High or Low Time Data Setup Time (Inputs) Data Hold Time (Inputs) Slave Access Time (time to data active) Slave MISO Disable Time Data Valid after SCK Edge Data Valid after SS fall Data Hold Time (Outputs) Rise and Fall Time Inputs Rise and Fall Time Outputs
Symbol Min fsck tsck tlead tlag twsck tsu thi ta tdis tvsck tvss tho trfi trfo DC 4 4 4 4 8 8 -- -- -- -- 20 -- -- Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max 1/4 -- -- -- -- -- 20 22 30 + tbus 1 30 + tbus 1 -- 8 8
Unit fbus tbus tbus tbus tbus ns ns ns ns ns ns ns ns ns
tbus added due to internal synchronization delay
A.9
External Bus Timing
A timing diagram of the external multiplexed-bus is illustrated in Figure A-10 with the actual timing values shown on Table A-23 in 5V range. All major bus signals are included in the diagram. While both a data write and data read cycle are shown, only one or the other would occur on a particular bus cycle.
A.9.1
General Muxed Bus Timing
The expanded bus timings are highly dependent on the load conditions. The timing parameters shown assume a balanced load across all outputs.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 533
Appendix A Electrical Characteristics
1, 2 3 ECLK PE4 5 9 Addr/Data (read) PA, PB data 6 15 addr 7 12 Addr/Data (write) PA, PB data addr 8 14 data 13 16 10 data 11 4
17 Non-Multiplexed Addresses PK5:0 20 ECS PK7
18
19
21
22
23
24 R/W PE2
25
26
27 LSTRB PE3
28
29
30 NOACC PE7
31
32
33 IPIPE0 IPIPE1, PE6,5
34
35
36
Figure A-10. General External Bus Timing
MC3S12RG128 Data Sheet, Rev. 1.05 534 Freescale Semiconductor
Appendix A Electrical Characteristics
Table A-23. Expanded Bus Timing Characteristics In 5V Range
Conditions are shown in Table A-4 unless otherwise noted, CLOAD = 50pF. Supply Voltage 5V-10% <= VDDX <=5V+10% Num C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Rating Symbol fo tcyc PWEL
1
Min 0 40 19 19
Typ
Max 25.0
Unit MHz ns ns ns
P Frequency of operation (E-clock) P Cycle time D Pulse width, E low D Pulse width, E high D Address delay time D Address valid time to E rise (PWEL-tAD) D Muxed address hold time D Address hold to data valid D Data hold to address D Read data setup time D Read data hold time D Write data delay time D Write data hold time D Write data setup time1 (PWEH-tDDW) D Address access time1 (tcyc-tAD-tDSR) D E high access time
1 (PW EH-tDSR)
PWEH tAD tAV tMAH tAHDS tDHA tDSR tDHR tDDW tDHW tDSW tACCA tACCE tCSD tACCS tCSH tCSN tRWD tRWV tRWH tLSD tLSV tLSH tNOD tNOV tNOH tP0D tP0V tP1D tP1V
8 11 2 7 2 13 0 7 2 12 19 6 16 11 2 8 7 14 2 7 14 2 7 14 2 2 11 2 11 25 7
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
D Chip select delay time D Chip select access time1 (tcyc-tCSD-tDSR) D Chip select hold time D Chip select negated time D Read/write delay time D Read/write valid time to E rise (PWEL-tRWD) D Read/write hold time D Low strobe delay time D Low strobe valid time to E rise (PWEL-tLSD) D Low strobe hold time D NOACC strobe delay time D NOACC valid time to E rise (PWEL-tNOD) D NOACC hold time D IPIPE[1:0] delay time D IPIPE[1:0] valid time to E rise (PWEL-tP0D) D IPIPE[1:0] delay time1 (PWEH-tP1V)
D IPIPE[1:0] valid time to E fall
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 535
Appendix A Electrical Characteristics
1
Affected by clock stretch: add N x tcyc where N=0,1,2 or 3, depending on the number of clock stretches.
MC3S12RG128 Data Sheet, Rev. 1.05 536 Freescale Semiconductor
Appendix B Package Information
Appendix B Package Information
B.1 General
This section provides the physical dimensions of the MC3S12RG128 packages.
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 537
Appendix B Package Information
B.2
PIN 1 IDENT
112-pin LQFP package
4X 112 1
0.20 T L-M N
4X 28 TIPS 85 84
0.20 T L-M N
J1 J1 C L
4X
P
VIEW Y
108X
G
X X=L, M OR N
VIEW Y B L M B1 V1 V
J
AA
28
57
F D 0.13
M
BASE METAL
29
56
T L-M N
N A1 S1 A S
SECTION J1-J1 ROTATED 90 COUNTERCLOCKWISE
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DATUMS L, M AND N TO BE DETERMINED AT SEATING PLANE, DATUM T. 4. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE, DATUM T. 5. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE. DIMENSIONS A AND B INCLUDE MOLD MISMATCH. 6. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.46. MILLIMETERS MIN MAX 20.000 BSC 10.000 BSC 20.000 BSC 10.000 BSC --1.600 0.050 0.150 1.350 1.450 0.270 0.370 0.450 0.750 0.270 0.330 0.650 BSC 0.090 0.170 0.500 REF 0.325 BSC 0.100 0.200 0.100 0.200 22.000 BSC 11.000 BSC 22.000 BSC 11.000 BSC 0.250 REF 1.000 REF 0.090 0.160 8 0 7 3 13 11 11 13
C2 C 0.050 2
VIEW AB 0.10 T
112X
SEATING PLANE
3 T
R
R2 0.25
GAGE PLANE
R
R1
C1 (Y) (Z) VIEW AB
(K) E
1
DIM A A1 B B1 C C1 C2 D E F G J K P R1 R2 S S1 V V1 Y Z AA 1 2 3
Figure B-1. 112-pin LQFP mechanical dimensions (case no. 987)
MC3S12RG128 Data Sheet, Rev. 1.05 538 Freescale Semiconductor
Appendix B Package Information
B.3
80-pin QFP package
L
60 61 41 40
S
S
B B P
D
L
H A-B
B
V 0.05 D
M
M
C A-B
-A-
-B-
S
S
D
0.20
0.20
-A-,-B-,-DDETAIL A
DETAIL A
80 1 20
21
-D0.20
M
F
A H A-B S
S
D
S
0.05 A-B J
S
N
0.20 E C -CSEATING PLANE
M
C A-B
D
S
M DETAIL C -HH G
DATUM PLANE
D 0.20
M
C A-B
S
D
S
SECTION B-B
VIEW ROTATED 90
0.10 M
U T
DATUM PLANE
-H-
R
K W X DETAIL C
Q
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -A-, -B- AND -D- TO BE DETERMINED AT DATUM PLANE -H-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -C-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT.
DIM A B C D E F G H J K L M N P Q R S T U V W X
MILLIMETERS MIN MAX 13.90 14.10 13.90 14.10 2.15 2.45 0.22 0.38 2.00 2.40 0.22 0.33 0.65 BSC --0.25 0.13 0.23 0.65 0.95 12.35 REF 5 10 0.13 0.17 0.325 BSC 0 7 0.13 0.30 16.95 17.45 0.13 --0 --16.95 17.45 0.35 0.45 1.6 REF
Figure B-2. 80-pin QFP Mechanical Dimensions (case no. 841B)
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 539
Appendix C Printed Circuit Board Proposal
Appendix C Printed Circuit Board Proposal
Table C-1. Suggested External Component Values
Component C1 C2 C3 C4 C5 C6 C7 C8 C9 / CS C10 / CP C11 / CDC R1 / R R2 / RB R3 / RS Q1 Quartz Purpose VDD1 filter cap VDD2 filter cap VDDA filter cap VDDR filter cap VDDPLL filter cap VDDX filter cap OSC load cap OSC load cap PLL loop filter cap PLL loop filter cap DC cutoff cap PLL loop filter res Colpitts mode only, if recommended by quartz manufacturer See PLL Specification chapter Pierce mode only See PLL specification chapter Type ceramic X7R ceramic X7R ceramic X7R X7R/tantalum ceramic X7R X7R/tantalum Value 100 ... 220nF 100 ... 220nF 100nF >= 100nF 100nF >= 100nF
See PLL specification chapter
The PCB must be carefully laid out to ensure proper operation of the voltage regulator as well as of the MCU itself. The following rules must be observed: * Every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the corresponding pins (C1 - C6). * Central point of the ground star should be the VSSR pin. * Use low ohmic low inductance connections between VSS1, VSS2 and VSSR. * VSSPLL must be directly connected to VSSR. * Keep traces of VSSPLL, EXTAL and XTAL as short as possible and occupied board area for C7, C8, C11 and Q1 as small as possible. * Do not place other signals or supplies underneath area occupied by C7, C8, C10 and Q1 and the connection area to the MCU. * Central power input should be fed in at the VDDA/VSSA pins.
MC3S12RG128 Data Sheet, Rev. 1.05 540 Freescale Semiconductor
Appendix C Printed Circuit Board Proposal
VREGEN
VDDX
C6 VSSX
VSSA
C3
VDDA
VDD1 C1 VSS1 VSS2 C2 VDD2
VSSR C4 VDDR C5 C9 R1 C10 C8 Q1 VSSPLL VDDPLL C7
Figure C-1. Recommended PCB Layout for 112LQFP Colpitts Oscillator
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 541
C11
Appendix C Printed Circuit Board Proposal
VDDX
C6
VREGEN
VSSX
VSSA
C3
VDDA
VDD1 VSS2
C1 C2
VSS1 VDD2
VSSR C4 C5 VDDR C11
C8
C7 Q1
C10
R1
Figure C-2. Recommended PCB Layout for 80QFP Colpitts Oscillator
MC3S12RG128 Data Sheet, Rev. 1.05 542 Freescale Semiconductor
C9
VSSPLL VDDPLL
Appendix C Printed Circuit Board Proposal
VREGEN
VDDX
C6 VSSX
VSSA
C3
VDDA
VDD1 C1 VSS1 VSS2 C2 VDD2
VSSR R3 C5 R2 Q1 C9 C10 C8 C7 VSSPLL C4 VDDR VDDPLL R1
Figure C-3. Recommended PCB Layout for 112LQFP Pierce Oscillator
MC3S12RG128 Data Sheet, Rev. 1.05 Freescale Semiconductor 543
Appendix C Printed Circuit Board Proposal
VDDX
C6
VREGEN
VSSX
VSSA
C3
VDDA
VDD1 VSS2
C1 C2
VSS1 VDD2
VSSPLL
VSSR C4 C5 VDDR
R2 Q1 C8 C7 R3
C10
R1
Figure C-4. Recommended PCB Layout for 80QFP Pierce Oscillator
MC3S12RG128 Data Sheet, Rev. 1.05 544 Freescale Semiconductor
C9
VSSPLL VDDPLL
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FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. (c) Freescale Semiconductor, Inc. 2005, 2006. All rights reserved. MC3S12RG128V1 Rev. 1.05 11/2006

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